CN111577242A - Sand production signal synchronous acquisition system based on FPGA - Google Patents
Sand production signal synchronous acquisition system based on FPGA Download PDFInfo
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- CN111577242A CN111577242A CN202010381688.8A CN202010381688A CN111577242A CN 111577242 A CN111577242 A CN 111577242A CN 202010381688 A CN202010381688 A CN 202010381688A CN 111577242 A CN111577242 A CN 111577242A
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Abstract
The embodiment of the invention discloses a system for synchronously acquiring a sand production signal based on an FPGA (field programmable gate array), which comprises: the ultrasonic signal processing device comprises a sensor array consisting of at least two ultrasonic signal sensors, a data acquisition circuit, a logic control circuit and a data processing circuit; the sensor array is arranged on the outer wall of a pipeline in an oil-gas well to be detected; the data acquisition circuit converts output signals acquired by the sensor array into digital signals; the logic control circuit controls the time sequence of the data acquisition circuit, and screens and caches the digital signals based on a set threshold; and the data processing circuit performs data processing on the screened digital signals cached by the logic control circuit so as to obtain processing data capable of representing the sand production rate.
Description
Technical Field
The embodiment of the invention relates to the technical field of oil and gas well monitoring, in particular to a sand production signal synchronous acquisition system based on an FPGA (field programmable gate array).
Background
In the production operation process of oil and gas well, along with the continuous deepening of oil and gas field development intensity, if the condition of producing sand appears in the oil gas stream that carries in the oil and gas well pipeline, can cause very big to damage for equipment, serious problems such as low efficiency separation and pipe blockage. Therefore, sand production from oil and gas wells is one of the major problems encountered in the industrial production of oil and gas. Therefore, the sand production rate of the oil and gas well is monitored in real time. The sand production condition and the sand production rule can be timely mastered, so that the production condition of the oil-gas well can be diagnosed, and a basis is provided for sand prevention and control. Based on this, it is necessary to monitor sand production from oil and gas wells.
At present, the monitoring scheme for the sand production signal mainly adopts an acquisition system mainly comprising a data acquisition card to carry out on-site acquisition on data, and then carries out post-processing on the acquired data. The method has certain feasibility, can accurately analyze the sand production condition of the oil-gas well, but has more problems, such as that the data volume of the sand production signal is continuously increased, continuous signal acquisition not only has large data volume, but also has more invalid data volume, and the actual analysis result is influenced; secondly, under the complex geological condition, the random variation of the sand production amount of the oil and gas well pipeline is larger, but most of the sand production data collected by the data acquisition card is information in a certain time period, so that the real-time monitoring of the sand production signal is unlikely to meet the requirement; thirdly, the acquisition system is single, the flexibility is poor, the influence of complex environment is large, and the specificity is not strong; and finally, the method mostly depends on the inherent software operation interface and has high cost and the like.
Disclosure of Invention
In view of this, the embodiments of the present invention are intended to provide a system for synchronously acquiring a sand production signal based on an FPGA; the sand production monitoring performance can be improved, and the sand production condition of the oil and gas well is effectively monitored in real time.
The technical scheme of the embodiment of the invention is realized as follows:
in a first aspect, an embodiment of the present invention provides a system for synchronously acquiring a sand production signal based on an FPGA, where the system includes: the ultrasonic signal processing device comprises a sensor array consisting of at least two ultrasonic signal sensors, a data acquisition circuit, a logic control circuit and a data processing circuit; the sensor array is arranged on the outer wall of a pipeline in an oil-gas well to be detected; the data acquisition circuit converts output signals acquired by the sensor array into digital signals; the logic control circuit controls the time sequence of the data acquisition circuit, and screens and caches the digital signals based on a set threshold; and the data processing circuit performs data processing on the screened digital signals cached by the logic control circuit so as to obtain processing data capable of representing the sand production rate.
The embodiment of the invention provides a sand production signal synchronous acquisition system based on an FPGA (field programmable gate array); because the sensor array is used for collecting the original signals, compared with single sensor signal processing, the method can enhance the required useful signals and inhibit useless interference and noise, and therefore, in the process of sand production monitoring of the oil-gas well pipeline, sand grains obtained by processing the collected ultrasonic array signals impact the sand production rate in the oil-gas pipeline, and compared with the existing single ultrasonic sensor, the method can monitor the sand production rate in the oil-gas well pipeline more accurately and in real time.
Drawings
Fig. 1 is a schematic composition diagram of a synchronous sand production signal acquisition system based on an FPGA according to an embodiment of the present invention;
fig. 2 is a schematic composition diagram of another FPGA-based sanding signal synchronous acquisition system according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an interaction structure of a logic control circuit and a data processing circuit according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a storage structure according to an embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
In order to improve the performance of sand production monitoring, an embodiment of the present invention is to provide a system 1 for synchronously acquiring sand production signals based on an FPGA, and referring to fig. 1, the system 1 may include: the ultrasonic signal processing device comprises a sensor array 11 consisting of at least two ultrasonic signal sensors, a data acquisition circuit 12, a logic control circuit 13 and a data processing circuit 14; the sensor array 11 is arranged on the outer wall of a pipeline in an oil and gas well to be detected; the data acquisition circuit 12 converts the output signals acquired by the sensor array 11 into digital signals; the logic control circuit 13 controls the time sequence of the data acquisition circuit 12, and screens and caches the digital signals based on a set threshold; the data processing circuit 14 performs data processing on the screened digital signals buffered by the logic control circuit 13, so as to obtain processing data capable of representing the sand production rate.
In order to clearly illustrate the technical solution of the embodiment of the present invention, referring to fig. 1, the number of the ultrasonic signal sensors 101 in the sensor array 11 may be exemplarily set to 8, and the numbers are respectively set to 101a to 101 h. It is to be understood that the above numbers and numbering are only used to illustrate the technical solutions. The number and the number of the ultrasonic signal sensors 101 in the sensor array 11 are not specifically limited in the embodiments of the present invention.
For the system 1 shown in fig. 1, in some examples, as shown in fig. 2, the data acquisition circuit 12 may include a data preprocessing circuit 121 and an Analog-to-Digital (a-D) conversion circuit 122; the data preprocessing circuit 121 includes N identical single-ended to differential conversion circuits, and the a-D conversion circuit 122 includes N/2 dual-channel a-D conversion chips; n denotes the number of ultrasonic sensors 101 in the sensor array 11. Based on the data acquisition circuit 12, specifically, the single-ended to differential conversion circuits are in one-to-one correspondence with the ultrasonic signal sensors 101, that is, the input end of each single-ended to differential conversion circuit is connected to the output end of the corresponding ultrasonic signal sensor 101; for the a-D conversion circuit 122, each two single-ended to differential conversion circuits correspond to one dual-channel a-D conversion chip, that is, the output ends of each two single-ended to differential conversion circuits are connected to the input ends of the corresponding dual-channel a-D conversion chips. In implementing this example, preferably, the dual-channel a-D conversion chip may preferably use an AD9650 analog-to-digital conversion chip, as described with 8 ultrasonic signal sensors 101 shown in fig. 1, so that the single-end-to-differential conversion circuit is 8-way, and the number of the dual-channel a-D conversion chips is 4.
For the system 1 shown in fig. 1, in some examples, the logic control circuit 13 may implement timing control through a Field-Programmable Gate Array (FPGA) chip, and the number of the FPGA chip may be preferably half of the number of the dual-channel a-D conversion chips, and the data processing circuit 14 may specifically use an ARM processor to perform data processing through a corresponding algorithm program, so as to obtain processing data capable of representing the sand production rate. Specifically, each FPGA chip may include a control subsystem and a dual Access Memory (RAM); the a-D controller 131 is configured to control data acquisition of the corresponding a-D conversion circuit 13, and the dual-port RAM132 is configured to store data acquired by the corresponding a-D conversion circuit 13. Preferably, each FPGA chip includes 4 dual port RAMs.
For the system 1 shown in fig. 1, in some examples, the logic control circuit 13 and the data processing circuit 14 may communicate with each other through a variable Static Memory Controller (FSMC) so that the data processing circuit 14 can read the screened digital signals cached by the logic control circuit 13 at a high speed.
Specifically, the dual-port RAM132 adopts a true dual-port mode, and has two paths of read enable, write data, read address, write address, and read data ports. The two ports of the dual port RAM132 allow for simultaneous writing or reading of data into the RAM. One port is operated by the logic control circuit 13 to record the collected data, and the other port is used to send data to the data processing circuit 14, and at the same time, the data processing circuit 14 can also send an instruction to clear the data in the storage area of the dual-port RAM 132.
In more detail, the data processing circuit 14 is connected to the dual-port RAM132 through a variable static Memory Controller (FSMC) bus, and in some examples, the data processing circuit 14 may read the acquired data stored in the dual-port RAM132 and determine the data to be processed corresponding to each ultrasonic signal sensor based on the phase delay time of each ultrasonic signal sensor in the sensor array; weighting and summing the data to be processed corresponding to each ultrasonic signal sensor according to a preset weight value to obtain a power spectrogram of the sand impacting the inner wall of the oil-gas pipeline; and outputting the sand production rate of the sand impacting the oil and gas pipeline according to the power spectrogram.
According to the technical scheme of the embodiment of the invention, as the sensor array is used for collecting the original signals, compared with single sensor signal processing, the required useful signals can be enhanced, and useless interference and noise can be inhibited, so that in the process of sand production monitoring of the oil-gas well pipeline, sand grains obtained by processing the collected ultrasonic array signals impact the sand production rate in the oil-gas pipeline, and compared with the existing single ultrasonic sensor, the sand production rate in the oil-gas well pipeline can be monitored more accurately in real time.
It should be noted that, for processing array signals, the synchronicity of acquisition is an important index for determining the quality of the system. For the system 1 structure provided in this embodiment, in the implementation process, the factors causing the asynchronization may include different path delays experienced by analog signals acquired by the sensor array on each channel, different sampling clock and sampling configuration time of the multiple two-channel a-D conversion chips, and asynchronization of start time of the FPGA chip acquisition. In view of the above factors, the embodiment of the present invention further sets the system 1 in a manner of combining software and hardware, thereby implementing a stable and efficient synchronous design.
Regarding the aspect of hardware design, firstly, it is considered that the output signals acquired by the sensor array need to pass through complex transmission paths such as the data acquisition circuit 12, the logic control circuit 13 and the data processing circuit 14, and the path delay is difficult to estimate due to the difference of layout and wiring among the channels. Therefore, in order to improve the signal quality and reduce unnecessary errors, in addition to strictly complying with the basic requirements of device layout and wiring, in combination with the symmetry possessed by the "funnel-type" circuit structure of the system 1 shown in fig. 2, in some examples, the data acquisition circuit 12, the logic control circuit 13 and the data processing circuit 14 in the system 1 may perform 4-layer layout and wiring by using Cadence software, and perform the identical layout and wiring strategies between the data preprocessing circuit 121 and the a-D conversion circuit 122, and between the data processing circuit 13 in the data acquisition circuit 12 by means of module multiplexing, so as to make the paths transmitted by the signals of the channels identical, and to avoid the delay errors introduced by the path factors to the greatest extent.
In addition, in order to ensure that the a-D conversion chips in the data acquisition circuit 12 can work synchronously, the problems of clock circuit delay and configuration circuit delay of the sampling clock need to be solved. Therefore, in some examples, a single homologous clock is used between the a-D conversion chips to drive a plurality of a-D conversion chips simultaneously, and the sampling clock can reach each a-D conversion chip synchronously through strict equal-length wiring rules; and for the configuration circuit, an equal-length wiring strategy is also adopted to reduce the configuration delay error to the maximum extent. By optimizing the layout and wiring design, the requirement of the synchronization performance is met on the basis of hardware.
In order to ensure a better synchronization effect, the embodiment of the invention can also perform logic synchronization from software through program optimization design on the basis of ensuring system synchronization in the aspect of hardware design. The software synchronization mainly aims at the problem of configuration delay of Serial Peripheral Interfaces (SPI) of an FPGA chip and an A-D conversion chip and the problem of acquisition and storage delay of data by the FPGA chip.
For the former, the parallel processing capability of the FPGA can be utilized to program logic for the control subsystem composed of the a-D controller 131, so as to implement synchronous configuration for the a-D conversion chip devices. For the latter, the arbitration is realized by combining a data processing mechanism of an FPGA + ARM architecture and through synchronous interactive logic signals between the two mechanisms. As shown in fig. 3, taking two FPGA chips as an example, by applying a synchronous logic signal, such as the control synchronous write signal Wr _ start and the synchronous read signal Rd _ start shown in fig. 3, data read (Rd _ start) write (Wr _ start) enable of 4 dual-port RAM buffers (dpram) in each FPGA is synchronously controlled by an ARM through an interactive signal multiplexing line, so that the joint operation of the two FPGA chips and the synchronous data acquisition and buffer process of 8 channels are realized by using program logic.
It should be noted that, after the synchronization performance of the system 1 is improved and optimized according to the above example, it is also necessary to consider that the frequency of the sand production signal is mainly concentrated between 20k and 500kHz, if the sand production signal is collected at a sampling rate of 10MHz, the effective data scale of the first wave is about 200 to 500 sampling points, and because the setting of the actual threshold value is according to the actual situation on site, according to the difference between different well conditions, a reasonable value can be taken, so that the flexibility and the adaptability of the system can be greatly improved. Based on this, in some examples, a threshold value adapted to the pipe to be inspected and the amount of data of the sampling point that needs to be retained can be set by analyzing the signal characteristics of the sand hitting the inner wall of the pipe. In order to prevent false triggering caused by noise and other useless signals, continuous threshold judgment can be preferably performed on a plurality of sampling points to ensure the sampling reliability, and the sampling points judged by the threshold are retained, and the sampling points not judged by the threshold are discarded. Effective threshold setting can reduce the data storage amount of the sampling point under the condition of not influencing the data integrity, thereby reducing the resource consumption of the FPGA and reducing the calculation burden of the subsequent data processing circuit 14 for realizing algorithm operation.
In addition, in order to completely and effectively restore the analog signals of each data channel and for the convenience of post-algorithm processing, in some examples, each channel may take 512 data points for storage and processing before and after threshold triggering. In order to improve the real-time data caching efficiency of multiple channels, double-port RAMs in an FPGA are used for data caching for each channel, the storage depth is 1024, the data caching is formed according to the same parallel grouping mode, so that the logic expression is that 8 parallel data storage channels are used by an FPGA chip selectively, and the FPGA chip controls the operation of a storage module consisting of the double-port RAMs by responding to commands sent by an ARM through interactive signals. A plurality of simple subsystems are combined to form a high-performance and low-cost storage system, so that the performance requirement of a high-speed acquisition system on real-time updating and storing of big data is met. The IP core of the dual-port RAM can effectively improve the system performance and provide faster interface connection speed.
More specifically, in order to implement the corresponding and staggered transmission of the acquired data and the channel data, the selected storage structure combines the FSMC communication protocol of the ARM and the IP core characteristics of the dual-port RAM of the FPGA chip, and performs high-speed parallel transmission of the data on the multi-channel data in a high-bit cross addressing and multi-bank parallel manner, the specific storage structure of the data is as shown in fig. 4, taking four dual-port RAMs included in one FPGA chip as an example, respectively mapping the FSMC addresses to the dual-port RAM buffers of each channel, performing high-bit address comparison through a program, identifying the body number to be read, and reading the in-vivo data according to the in-vivo address, and through reasonable movement, enabling the request source to access the corresponding body, thereby implementing the accurate corresponding and reading of the channel data, and effectively improving the data transmission rate through the method.
In addition, the system 1 further comprises an upper computer 15 connected with the output of the data processing circuit 14, and is configured to display the position information of the sand impacting the inner wall of the oil and gas pipeline through a numerical display control and/or a waveform diagram display control. Specifically, the upper computer 15 is connected to the output end of the data processing circuit 14 by a Universal Asynchronous Receiver/Transmitter (UART) bus. In detail, the upper computer 15 can read a frame of data sent by the ARM processor, determine the frame header, the number of bytes of each frame of data, and the frame end, if all three determination elements are met, retain the data, send the data to the data processing module, and then return to continue reading the next frame of data. If one item of the frame head, the number of bytes of each frame of data and the frame tail does not accord with the item, the frame of data is selected to be abandoned, and the reading of new data is returned. After format conversion and algorithm processing, the data are transmitted to a numerical value display control and a oscillogram display control to be displayed in real time and drawn.
The embodiment of the invention combines the index requirements of the sand production signals of the oil and gas wells, designs the AD 9650-based multi-channel acquisition circuit, and realizes the acquisition of signals of the linear array distributed probes. In addition, in order to reduce the invalid communication data volume, accurately capture an effective signal area and synchronously cache multi-channel data, a sand production signal threshold value extraction detection step is designed, and a multi-body parallel cache module solution is provided. The system has high-efficiency and quick acquisition and processing capacity on the sand production signal data of the oil and gas well, meets the data acquisition requirement under the complex environment, effectively improves the precision and efficiency of the real-time monitoring of the sand production signal of the oil and gas well, and has important significance on the monitoring and processing of the sand production signal of the oil and gas well.
It is understood that in this embodiment, "part" may be part of a circuit, part of a processor, part of a program or software, etc., and may also be a unit, and may also be a module or a non-modular.
In addition, each component in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit. The integrated unit can be realized in a form of hardware or a form of a software functional module.
Based on the understanding that the technical solution of the present embodiment essentially or a part contributing to the prior art, or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium, and include several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to execute all or part of the steps of the method of the present embodiment. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
It should be noted that: the technical schemes described in the embodiments of the present invention can be combined arbitrarily without conflict.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. The utility model provides a sanding signal synchronous acquisition system based on FPGA which characterized in that, the system includes: the ultrasonic signal processing device comprises a sensor array consisting of at least two ultrasonic signal sensors, a data acquisition circuit, a logic control circuit and a data processing circuit; the sensor array is arranged on the outer wall of a pipeline in an oil-gas well to be detected; the data acquisition circuit converts output signals acquired by the sensor array into digital signals; the logic control circuit controls the time sequence of the data acquisition circuit, and screens and caches the digital signals based on a set threshold; and the data processing circuit performs data processing on the screened digital signals cached by the logic control circuit so as to obtain processing data capable of representing the sand production rate.
2. The system of claim 1, wherein the data acquisition circuit comprises a data preprocessing circuit and an analog-to-digital signal a-D conversion circuit; the data preprocessing circuit comprises N identical single-ended to differential conversion circuits, and the A-D conversion circuit comprises N/2 double-channel A-D conversion chips; n represents the number of ultrasonic sensors in the sensor array;
the logic control circuit realizes time sequence control through FPGA chips, and the number of the FPGA chips is half of that of the two-channel A-D conversion chips; the data processing circuit adopts an ARM processor to process data through an algorithm program, and processing data capable of representing the sand production rate are obtained.
3. The system according to claim 2, wherein each said FPGA chip includes a control subsystem and a number of dual-port random access memories RAM; the A-D controller is used for controlling data acquisition of the corresponding A-D conversion circuit, and the double-port RAM is used for storing the data acquired by the corresponding A-D conversion circuit.
4. The system of claim 1, wherein the logic control circuitry communicates with the data processing circuitry via a variable static memory controller (FSMC).
5. The system of claim 2, wherein the data acquisition circuit, the logic control circuit and the data processing circuit use Cadence software to perform 4-layer layout and wiring, and completely the same layout and wiring strategy is performed between the data preprocessing circuit and the a-D conversion circuit as well as between the data preprocessing circuit and the logic control circuit in the data acquisition circuit respectively in a module multiplexing manner, so that the paths transmitted by the signals of the channels are the same, and delay errors introduced by path factors are avoided to the greatest extent.
6. The system of claim 2, wherein a source clock is used between the a-D conversion chips to drive a plurality of a-D conversion chips simultaneously, and a sampling clock can reach each a-D conversion chip synchronously through strict equal-length wiring rules; for a configuration circuit of the A-D conversion chip, an equal-length wiring strategy is also adopted to reduce configuration delay errors to the maximum extent.
7. The system of claim 2, wherein the control subsystem consisting of the a-D controller is programmed with logic by the FPGA chip to achieve synchronous configuration of the a-D conversion chip devices.
8. The system of claim 2, wherein the ARM processor transmits synchronous logic signals by using an interactive signal multiplexing line, so that data read (Rd _ start) and write (Wr _ start) enablement of 4 dual-port RAMs in each FPGA chip can be synchronously controlled, and joint operation of the two FPGA chips and a multi-channel data synchronous acquisition and buffering process are realized by using program logic.
9. The system of claim 2, wherein for each lane, 512 data points are taken before and after threshold triggering for storage and processing; and the data caching is carried out on each channel by adopting a double-port RAM in the FPGA chip, the storage depth is 1024, and the data storage channels are formed according to the same parallel grouping mode, so that the data storage channels which are logically parallel are used by the FPGA chip selectively, and the FPGA chip controls the operation of a storage module group consisting of the double-port RAMs by responding to a command sent by an ARM through an interactive signal.
10. The system of claim 9, wherein the multi-channel data storage structure combines the FSMC communication protocol of the ARM and the IP core characteristics of the dual-port RAM of the FPGA chip to perform high-speed parallel data transmission by high-bit cross addressing and multi-bank parallel.
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| CN202010381688.8A CN111577242A (en) | 2020-05-08 | 2020-05-08 | Sand production signal synchronous acquisition system based on FPGA |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114577436A (en) * | 2022-04-15 | 2022-06-03 | 中国科学院西北生态环境资源研究院 | Acoustic wave type sand collector for sand flow |
| CN114577435A (en) * | 2022-04-15 | 2022-06-03 | 中国科学院西北生态环境资源研究院 | Unidirectional non-sand-accumulation gradient sand collector based on sound wave conversion |
-
2020
- 2020-05-08 CN CN202010381688.8A patent/CN111577242A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114577436A (en) * | 2022-04-15 | 2022-06-03 | 中国科学院西北生态环境资源研究院 | Acoustic wave type sand collector for sand flow |
| CN114577435A (en) * | 2022-04-15 | 2022-06-03 | 中国科学院西北生态环境资源研究院 | Unidirectional non-sand-accumulation gradient sand collector based on sound wave conversion |
| CN114577435B (en) * | 2022-04-15 | 2022-11-25 | 中国科学院西北生态环境资源研究院 | Unidirectional non-sand-accumulation gradient sand collector based on sound wave conversion |
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