CN2700945Y - System for optimizing disturbance withstanding capability and data transmission rate for printer parallel interface - Google Patents

Abstract

The utility model relates to a system for optimizing disturbance withstanding capability and data transmission rate for printer parallel interface, comprising an IEEE1284 module and a printer controller module, which is characterized in that the datawire input loop of the printer parallel interface is joined with a digitalization interference protection module which comprises the first parameter register, the first input comparator, the first delay counter, the first delay comparator, the first sampling latch, the second sampling latch and the first output comparator. The anti-interference ability of the printer parallel interface and the causation and digitalization conversion process between the data transmission speed are quasi-batching disclosed, providing a simple and feasible digitalization anti-interference scheme. The conflict between the anti-interference and the data transmission speed of the printer is solved or alleviated making the two latent capacities of anti-interference ability and data transmission speed of the printer parallel interface exert more adequately. The utility model can be extensively used to the technical field of printers.

Description

Optimize the system of printer parallel interface antijamming capability and message transmission rate

Technical field:

The utility model relates to field of computer technology, relates in particular to a kind of jamproof system of printer parallel interface.

Background technology:

The IEEE1284 high speed parallel interface is one of the most widely used printer interface standard at present.In the Interface design of high-speed printer (HSP), the designing quality of antijamming capability and message transmission rate aspect is to user environment adaptability, job stability and the print speed important influence of printer product.

High speed development along with PC main frame soft hardware performance, the print job of more complicated at present, as Chinese character laser printing and graphic image output application, almost all or more and more adopt the bigger rastered picture compress mode of transmitted data amount, thus more and more higher to the requirement of the message transmission rate of printer parallel port.In order to satisfy the requirement of message transmission rate aspect, we often have to sacrifice the performance of interference prevention aspect, thereby the performance of host interface controller or the requirement of interface electric circumstance are improved thereupon.On the other hand,, generally have to again in present most product designs message transmission rate is limited within the 500K Byte/S for reduction interference prevention ability within reason, thus very unfavorable to the performance of giving full play to high speed laser printer.

Shown in Figure 1 is the anti-interference solution of a kind of typical printer parallel interface.XCtrol[3..0] expression printer parallel port 4 input control line: nInit, nSelectIn, nAutoFd, nStrobe; XD[7..0] 8 bidirectional data lines of expression; XStatus[4..0] 5 output state line: Perror of expression, nAck, Busy, nFault, Select.Fig. 2 a and Fig. 2 b are conventional printer parallel interface anti-interference electrical schematic diagrams commonly used: W is the limited amplitude protection diode, and Rup is the logic pull-up resistor, and T is the anti-phase reshaper of schmitt.In the side circuit design, generally satisfy condition: R＜＜Rup, R＜＜Rsr (phase inverter input resistance), so the parameter of R and C is selected and the V+ and the V-parameter of schmitt reshaper, determined the antijamming capability of this circuit and the message transmission rate that may reach basically.

Typical R C low-pass filter network has advantages such as the simple and hardware cost of circuit is low, but in the contradiction that exists some to be difficult to take into account aspect raising interference prevention ability and the data rate.For example: select bigger RC time constant favourable, but that the performance of message transmission rate aspect is easy to become is bad to improving the interference prevention ability.For example: according to IEEE1284 parallel interface standard, the signal pulse width of the nStrobe signal wire under high speed ECP mode of operation may be little of 500ns (referring to Fig. 3).According to the transient analysis knowledge of pulsing circuit, we know that the selection of RC parameter generally need be satisfied 3RC＜500ns in order to satisfy the requirement of larger data transfer rate.Further the engineering estimation shows, in order to satisfy the requirement of 1Mbyte/S left and right sides data rate, this circuit effectively breadth extreme of the disturbing pulse of filtering is not easy to surpass 40ns, if so in non-signal spacing (40ns..500ns in this example), impulse disturbances occurs, as long as amplitude breaks through the threshold voltage V+ (about 1.6V) and the V-(about 0.8V) of schmitt reshaper, just cause printing error code or other stability problems probably so.

In the parallel port of main frame and printer is plugged into mode, many in the observed interference of equipment end with the appearance of monopulse " burr " form, but saltus step ring even random series pulse also have the generation example by chance.If disturb and appear at data line, cause the printing error code problem easily; If disturb and appear at control line, except error code, also often cause the confusion of IEEE1284 interface protocol state machine.Investigate the solution of above-mentioned routine, disturb effective guard plot (=＜40ns) and signaling zone (＞=have a very wide transitional region between 500ns), be the external manifestation of limit interferences protection and data rate capabilities lifting.In other words, if manage the lower limit of this transitional region is improved, but the upper limit remains unchanged even moves down, and is equivalent to above-mentioned two the main performance index that promote the printer parallel interface simultaneously so, and high-speed printer (HSP) is used highly significant.With regard at present common product design application technology, as if traditional simulation interference prevention technology is difficult to effectively and high performance price ratio ground solves this class problem.

Summary of the invention:

The purpose of this utility model is to provide a kind of economical and practical digitizing jamproof system, make that the antijamming capability of printer parallel interface and the potentiality of message transmission rate two aspects are all brought into play more fully, solve or the anti-interference and message transmission rate of buffering printer parallel interface between contradiction, effectively remedy the deficiency of above-mentioned traditional solution.

The utility model comprises the IEEE1284 module, the printer controller module, in the data line input circuit of printer parallel interface, add digital immunity module, this numeral immunity module comprises first parameter register, first input comparator, first delay counter, first delay comparator, the first sampling latch, the second sampling latch.

The mode of operation of this numeral immunity module is:

First parameter register is data rule of thumb, set the value of the count threshold X of undesired signal;

First input comparator is first sampling latch and the data line signal relatively, the various saltus steps of real time monitoring data line signal; When the logic level of two groups of respective signal lines is identical, the output of first input comparator is counting controling signal CountEn2 just effectively, allow first delay counter under the effect of Clock clock, to count synchronously, require the first sampling latch to be in " data maintenance " state; When the logic level of two groups of respective signal lines not simultaneously, the counting controling signal CountEn2 that the output of first input comparator is invalid carries out " reset clearly 0 " operation to first delay counter, requires the first sampling latch to carry out " sampling is upgraded " operation simultaneously;

When first delay counter is equal to or greater than the value of pre-set limit count threshold X of first parameter register in its count value, produce just effectively sampling control signal Sample2, require the first sampling latch to carry out " sampling is upgraded " operation; The renewal data source of the first sampling latch is from the output of the first sampling latch;

The second sampling latch is exactly the data line input signal DI[7..0 that has removed undesired signal to the output of IEEE1284 module].

The utility model also comprises first output comparator, compares the first sampling latch and the second sampling latch in real time, whether stablizes available indicator signal ReadyDx to follow-up IEEE1284 module output data line signal;

Parameter register of the present utility model can obtain the dynamic optimization setting of count threshold X by the CPU optimized Algorithm.

Count threshold X of the present utility model should satisfy following formula:

Xmin＝＜X＜Xmax，

Xmin＝Round(Tnoise/Tclock)，

Xmax＝Round(Tsignal/Tclock-2)，

Wherein, Xmax is illustrated under the maximum data transfer rate expectation value qualifications, the restriction of the maximum occurrences of pre-value X; Round represents the result of subsequent calculations is carried out rounding operation; Tclock represents the cycle of sampling clock; Tsignal represents to be subjected to the equivalent pulse width of the unit element that may occur in the signal wire of anti-interference process, also is the equivalent parameters of message transmission rate expectation value; Tnoise represents to design the disturbing pulse width of the maximum of hypothesis.

The input of the data line signal in the utility model can be isolated by RC low-pass filter network and bidirectional bus transceiver, but the scope that the selection of RC parameter should exert an influence away from the design expectation value to data speed.

Principle of the present utility model is that printer parallel interface input signal is at first sent into digital immunity module, after the undesired signal that removal may exist, exports to follow-up IEEE1284 logic module again.

The utility model is fit to subordinate's interference model: the maximum interference pulse width on arbitrary data line is not more than Tnoise, but allows the disturbing pulse duration to surpass Tnoise, and its advantage is:

1) accurate inner link and the digitizing conversion method thereof that has disclosed quantitatively between printer parallel interface antijamming capability and the message transmission rate.

2) the digital hardware solution of a cover simple possible has been proposed;

3) the CPU control interface of introducing by the programmable parameter register not only can further optimal control mechanism, and increased the dirigibility of clock frequency selection in the utility system;

4) contradiction between the anti-interference and message transmission rate of solution or buffering printer parallel interface makes that the antijamming capability of printer parallel interface and the potentiality of message transmission rate two aspects are all brought into play more fully;

5) the utility model is applicable to the product design technology that adopts FPGA or ASIC.

Description of drawings:

Fig. 1: the typical anti-interference principle piece of printer parallel interface figure

Fig. 2 a, 2b: based on the anti-interference schematic diagram (the nStrobe signal wire is an example) of RC analog filtering technology

Fig. 3: the sequential chart example of the segment signal line of high-speed parallel mouth under the ECP mode of operation

Fig. 4: the introducing position description figure of the digitizing immunity module of printer parallel port

Fig. 5: the basic comprising form of digitizing immunity module

Fig. 6: the data line impulse disturbances is removed the process synoptic diagram

Embodiment:

Fig. 4 has provided the introducing location drawing of the digitizing immunity module of the utility model printer parallel interface.The maximum interference pulse width that the utility model design hypothesis appears on arbitrary data line is not more than Tnoise, but allows the disturbing pulse duration to surpass Tnoise.According to the appearance position of undesired signal and the feature of duration, digital immunity module of the present utility model has basic structure as shown in Figure 5.

As Fig. 5, digital immunity module of the present utility model comprises first parameter register able to programme, first input comparator, first delay counter, first delay comparator, the first sampling latch, the second sampling latch and first output comparator, first parameter register able to programme is data rule of thumb, set the value of the count threshold X of undesired signal; First input comparator is by comparing first sampling latch and the data line signal, the various saltus steps of real time monitoring data line signal; When the logic level of two groups of respective signal lines is identical, first input comparator will be exported just effectively counting controling signal CountEn2, allow first delay counter under the effect of Clock clock, to count synchronously, require the first sampling latch to be in " data maintenance " state; When the logic level of two groups of respective signal lines not simultaneously, first input comparator will be exported invalid counting controling signal CountEn2, first delay counter is carried out " reset clearly 0 " operation, require the first sampling latch to carry out " sampling is upgraded " operation simultaneously; When the count value of first delay counter is equal to or greater than the value of pre-set limit count threshold X of first parameter register, produce just effectively sampling control signal Sample2, require the second sampling latch to carry out " sampling is upgraded " operation; The renewal data source of the second sampling latch is from the output of the first sampling latch; The output of the second sampling latch is exactly the data line input signal DI[7..0 that has removed undesired signal].

First output comparator is exported positive useful signal ReadyDx, represents the output data DI[7..0 of second latch] stable.In this structure owing to only data line signal is carried out the digitizing anti-interference process, so the synchronous indicating signal ReadyDx that need provide data line to use to follow-up logic.

The programmable parameter register provides the setting of X limit value.The X limit value can be one or several fixing empirical data, also can realize the dynamic optimal setting by cpu i/f.Optimum is provided with data and generally need obtains by CPU adaptive learning algorithm.

In the maximum occurrences limited range of X, pre-value X obtains big more, and the interference range that protection can effectively be provided is also just big more, but leave for the IEEE1284 module the associated responses logic time delay nargin also can be more little.Surpass certain scope, along with the rising of pre-value X, message transmission rate also can descend to some extent in theory, but does not almost have the loss of extra transitional region between the two, and antijamming capability and message transmission rate have the ability of automatic conversion.

Fig. 6 waveform synoptic diagram can be used for illustrating the elimination process of impulse disturbances on the data line.Main frame is delivered to data on the data line, arrives the input end D[7..0 of digital immunity module constantly at t0], through arriving the output terminal DI[7..0 of digital immunity module after the Δ t=t1-t0=Tnoise delay].D[7..0] dashed area in the signal waveform represents if impulse disturbances appears in data line during this period, disappear as long as in the front and back position that disturbs initial point Tnoise, disturb, can be imitated inhibition no matter monopulse interference or train pulse disturb all so, otherwise be still had the possibility that error code takes place.For the time point behind data line normal signal saltus step (constantly) and the delay Tnoise thereof,, require so equally in the front and back position of this time point, to disturb to disappear, otherwise still have the possibility that error code takes place if follow other impulse disturbances to take place as t0.

Contrast test shows, adopts the inventive method in the laser printer design of Controller, and impulse disturbances protective capacities and main frame parallel port environmental suitability all are significantly improved; In addition, because the RC parameter in the input circuit can obtain less even part is saved, so more than the message transmission rate under the ECP mode of operation can be up to per second 1M Byte, apparent in view raising has been arranged than conventional scheme (generally being nominally at 250..500Kbyte/S).

Claims (3)

1, a kind of system that optimizes printer parallel interface antijamming capability and message transmission rate, comprise the IEEE1284 module, the printer controller module, it is characterized in that adding in the data line input circuit of printer parallel interface digital immunity module, this numeral immunity module comprises first parameter register, first input comparator, first delay counter, first delay comparator, the first sampling latch, the second sampling latch; Wherein the first sampling latch connects the data line and the second sampling latch; First input comparator connects the data line and first delay counter; First delay comparator connects the parameter register and first delay counter, and connects the second sampling latch; The second sampling latch connects the IEEE1284 module.

2, the system of optimization printer parallel interface antijamming capability as claimed in claim 1 and message transmission rate is characterized in that also comprising first output comparator, connects the first sampling latch and the second sampling latch, and connects the IEEE1284 module.

3, the system of optimization printer parallel interface antijamming capability as claimed in claim 1 or 2 and message transmission rate is characterized in that the input of data line signal is isolated by RC low-pass filter network and bidirectional bus transceiver.

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