CN2671008Y - Anti-interference printer parallel interface control system - Google Patents

Abstract

The utility model relates to an anti-interference printer parallel interface control system, comprising an IEEE1284 protocol module and a printer controller module. The control line return circuit of the printer parallel interface is added with a digitalization interference protection module which comprises a parameter register A, an input comparator A, a delay counter A, a delay comparator A, a sampling latch A and a sampling latch C. The interfering signal is dislodged through the module, and is output to a subsequent IEEE1284 logical module. A digitalization conversion approach is established between the anti-interference performance and the data rate of the parallel interface control line in the utility model. Under the condition of keeping higher data transmission rate, single pulse interference and sequence pulse interference in the control line can be suppressed actively, with the capacity of automatic dynamic regulation of the data rate. The utility model can be extensively used to printer control field.

Description

Jamproof printer parallel interface control system

Technical field:

The utility model relates to field of computer technology, relates in particular to a kind of jamproof printer parallel interface control system.

Background technology:

The IEEE1284 high speed parallel interface is one of the most widely used printer interface standard at present.In the Interface design of high-speed printer (HSP), the designing quality of antijamming capability and message transmission rate aspect is to user environment adaptability, job stability and the print speed important influence of printer product.

High speed development along with PC main frame soft hardware performance, the print job of more complicated at present, as Chinese character laser printing and graphic image output application, almost all or more and more adopt the bigger rastered picture compress mode of transmitted data amount, thus more and more higher to the requirement of the message transmission rate of printer parallel port.In order to satisfy the requirement of message transmission rate aspect, people often have to sacrifice the performance of interference prevention aspect, thereby the performance of host interface controller or the requirement of interface electric circumstance are improved thereupon.On the other hand,, generally have to again in present most product designs message transmission rate is limited within the 500K Byte/S for reduction interference prevention ability within reason, thus very unfavorable to the performance of giving full play to high speed laser printer.

Shown in Figure 1 is the anti-interference solution of a kind of typical printer parallel interface.XCtrol[3..0] expression printer parallel port 4 input control line: nInit, nSelectIn, nAutoFd, nStrobe; XD[7..0] 8 bidirectional data lines of expression; XStatus[4..0] 5 output state line: Perror of expression, nAck, Busy, nFault, Select.Fig. 2 a and Fig. 2 b are conventional printer parallel interface anti-interference electrical schematic diagrams commonly used: W is the limited amplitude protection diode, and Rup is the logic pull-up resistor, and T is the anti-phase reshaper of schmitt.In the side circuit design, generally satisfy condition: R＜＜Rup, R＜＜Rsr (phase inverter input resistance), so the parameter of R and C is selected and the V+ and the V-parameter of schmitt reshaper, determined the antijamming capability of this circuit and the message transmission rate that may reach basically.

Typical R C low-pass filter network has advantages such as the simple and hardware cost of circuit is low, but in the contradiction that exists some to be difficult to take into account aspect raising interference prevention ability and the data rate.For example: select bigger RC time constant favourable, but that the performance of message transmission rate aspect is easy to become is bad to improving the interference prevention ability.For example: according to IEEE1284 parallel interface standard, may be little in the signal pulse width of the nStrobe signal wire under the high speed ECP mode of operation to below the 500ns (referring to Fig. 3).According to the transient analysis knowledge of pulsing circuit, we know that the selection of RC parameter generally need be satisfied 3RC＜500ns in order to satisfy the requirement of larger data transfer rate.Further the engineering estimation shows, in order to satisfy the requirement of 1Mbyte/S left and right sides data rate, this circuit effectively breadth extreme of the disturbing pulse of filtering is not easy to surpass 40ns, if so in non-signal spacing (40ns..500ns in this example), impulse disturbances occurs, as long as amplitude breaks through the threshold voltage V+ (about 1.6V) and the V-(about 0.8V) of schmitt reshaper, just cause printing error code or other stability problems probably so.

In the parallel port of main frame and printer is plugged into mode, many in the observed interference of equipment end with the appearance of monopulse " burr " form, but saltus step ring and random series pulse also have the generation example by chance.If disturb and appear at data line, cause the printing error code problem easily; If disturb and appear at control line, except error code, also often cause the confusion of IEEE1284 interface protocol state machine.Investigate the solution of above-mentioned routine, be to disturb effective guard plot (=＜40ns) and signaling zone (＞=have a very wide transitional region between 500ns), be the external manifestation of limit interferences protection and data rate capabilities lifting.In other words, if manage the lower limit of this transitional region is improved, but the upper limit remains unchanged even moves down, and is equivalent to above-mentioned two the main performance index that promote the printer parallel interface simultaneously so, and high-speed printer (HSP) is used highly significant.With regard at present common product design application technology, traditional simulation interference prevention technology is difficult to effectively and high performance price ratio ground solves this class problem.

The utility model content:

The purpose of this utility model is the control line interference problem at printer, and a kind of simple and practical jamproof system is provided.

Jamproof printer parallel interface control system of the present utility model, comprise the IEEE1284 protocol module, the printer controller module, it is characterized in that adding in the control line loop of printer parallel interface digitizing interference prevention module, this digitizing interference prevention module comprises parameter register A, input comparator A, delay counter A, delay comparator A, sampling latch A and sampling latch C, wherein input comparator A Access Control line and sampling latch a-signal, delay counter A and sampling latch A insert the counting controling signal of input comparator A output, and parameter register A connects cpu i/f, and delay comparator A connects the output of delay counter A and parameter register A, sampling latch C accesses the output of sample latch A and delay comparator A, exports control signal by control line to the IEEE1284 protocol module.

Control line input in the utility model can be by RC low-pass filter network and schmitt reshaper and external interface isolation.If data speed is had higher requirement, should note selecting suitable RC parameter value, in order to avoid the design expectation value is produced significantly influence.

Principle of the present utility model is to insert additional digitizing interference prevention module in the control line loop of printer parallel interface, removes after the undesired signal, exports to follow-up IEEE1284 logic module again; The pattern that the utility model is removed undesired signal is:

1), sets the value of the count threshold X of undesired signal by parameter register A data rule of thumb;

2) input comparator A is by latch A and the control line signal input Ctrol[3..0 that relatively takes a sample], the various saltus steps of real time monitoring control line signal input; When the logic level of two groups of respective signal lines is identical, input comparator A will export just effectively counting controling signal CountA, to the operation that delay counter A carries out " counting synchronously ", sampling latch A be carried out the operation of " data maintenance "; When the logic level of two groups of respective signal lines not simultaneously, input comparator A will export invalid counting controling signal CountA, and delay counter A is carried out the operation of " reset clearly 0 ", A carries out the operation of " sampling is upgraded " to the sampling latch;

3) when the count value of delay counter A is equal to or greater than the value of pre-set limit count threshold X of parameter register A, delay comparator A will produce just effectively sampling control signal SampleC, sampling latch C is carried out the operation of " sampling is upgraded ", and the new data of taking a sample more is from the output of sampling latch A;

4) the output CtrolQ[3..0 of sampling latch C] be exactly the control line signal of having removed undesired signal.

The utility model is fit to the interference model of following harshness:

1) on 1 or many control lines impulse disturbances can appear simultaneously;

2) the breadth extreme Tnoise_p of monopulse interference is not more than limiting design value Tnoise;

3) the maximum duration T noise_c that disturbs of train pulse in the protocols limit scope without limits.

The characteristics of the utility model method are:

1) keeping under the higher data transmission rate precondition, the monopulse that the width that can effectively suppress to occur on the control line is not more than Tnoise disturbs;

2) keeping under the higher data transmission rate precondition, the train pulse that can effectively suppress to occur on the control line disturbs, duration of disturbance in the agreement allowed band without limits;

3) when the train pulse interference occurs, the utlity model has the ability that automatic dynamic is adjusted data rate;

4) a kind of certainly relational expression of amount and the digitizing transformation way of simple possible between the antijamming capability of parallel port control line and data rate, have been established.CPU control interface by the introducing of programmable parameter register, not only can increase the dirigibility (selecting) of engineering design as clock frequency, and can be according to actual needs further optimal control parameter, this digitizing transformation way is switched in a wider context flexibly;

5) the utility model also can be applied to above the combination of part control line;

6) the utility model is fit to adopt the product design technology of FPGA or ASIC.

Description of drawings:

Fig. 1: the typical anti-interference principle piece of printer parallel interface figure

Fig. 2 a, 2b: based on the anti-interference schematic diagram (the nStrobe signal wire is an example) of RC analog filtering technology

Fig. 3: the sequential chart example of the segment signal line of high-speed parallel mouth under the ECP mode of operation

Fig. 4: the introducing position description figure of the digitizing immunity module of printer parallel port

Fig. 5: the basic comprising form of digitizing immunity module

Fig. 6: the waveform synoptic diagram that impulse disturbances is eliminated and the automaticdata transfer rate is dynamically adjusted

Embodiment:

Referring to Fig. 5, the utility model digitizing interference prevention module partly is made up of input comparator A, delay counter A, delay comparator A, programmable parameter register A, sampling latch A and sampling latch C etc., input comparator A is by the output Ctrolm[3..0 of the latch A that relatively takes a sample] and through the control line input Ctrol[3..0 after the isolation of Schmitt reshaper], the various level of real time monitoring input control signal line change.When the logic level of two groups of respective signal lines is identical, input comparator A will export just effectively counting controling signal CountA, cause delay counter A to carry out the operation of " counting synchronously ", and sampling latch A carries out the operation of " data maintenance ".When the logic level of two groups of respective signal lines not simultaneously, for example cause Ctrol[3..0 owing to main frame excitation or external interference signal] when changing, input comparator A will export invalid counting controling signal CountA, counter A is carried out the operation of " reset clearly 0 ", simultaneously sampling latch A is carried out the operation of " sampling is upgraded ".When the count value of delay counter A is equal to or greater than the pre-set limit X of parameter register A, delay comparator A will produce just effectively sampling control signal SampleC, sampling latch C is carried out the operation of " sampling is upgraded ", and the new data of taking a sample more is from the output of sampling latch A.When the SampleC signal is just effective, the signal that is temporarily stored among the sampling latch A has stably kept being no less than the X*Tclcok time, show it is not that monopulse or the train pulse that will be eliminated disturbs, so have reason to think that it has been exactly our needed signal.

Parameter register A is the programmable parameter register, and the setting of X limit value is provided.The X limit value can be one or several alternative empirical data, also can realize the dynamic optimal setting by cpu i/f.Optimum is provided with data and generally need obtains by CPU adaptive learning algorithm, can obtain the dynamic optimal setting of count threshold X by the CPU optimized Algorithm.

Above-mentioned count threshold X can be according to the following formula value that concerns:

Xmin＝＜X＜Xmax，

Xmin＝Round(Tnoise/Tclock)，

Xmax＝Round(Tsignal/Tclock-2)，

Wherein, Xmax is illustrated under the maximum data transfer rate expectation value qualifications, the restriction of the maximum occurrences of pre-value X; Round represents the result of subsequent calculations is carried out rounding operation; Tclock represents the cycle of sampling clock; Tsignal represents the minimum signal pulse width that may occur in the control line, with the expectation value close association of message transmission rate; Tnoise=Tnoise_p,, the width that the maximum monopulse that can effectively suppress that the expression design is wished disturbs.

In the present embodiment, if sampling clock frequency Clock=40MHz, pre-value x=10, so effective all impulse disturbances within the filtering 250ns, the impulse disturbances protective capacities is considerably beyond the solution of routine.In the maximum occurrences limited range of X, pre-value X obtains big more, and the interference range that protection can effectively be provided is also just big more, but leave for the IEEE1284 module the associated responses logic time delay nargin also can be more little.Surpass certain scope, along with the rising of pre-value X, message transmission rate will begin to descend, and show to enter and need obtain the zone of interference prevention capability improving by reducing message transmission rate.

Fig. 6 waveform synoptic diagram can be used for illustrating that antijamming capability and message transmission rate have the ability of automatic conversion.Still closing with a part of signal logic in the ECP mode of operation is example: nStrobe represents the original gating control signal of main frame parallel port controller drives; XLpStrb represents that original nStrobe signal is subjected to certain and disturbs the output that appears at the Schmitt reshaper afterwards, and wherein dashed area represents that this zone exists a train pulse to disturb, and the primitive logic relation is obviously destroyed; / LpStrb represents to remove to disturb the waveform of handling corresponding with nStrobe through this patent method, and the primitive logic relation is correctly recovered; Busy represents to be sent back to by the printer parallel interface answer signal of main frame, the transmission cycle that notice main frame parallel port controller is finished this byte.Referring to the nStrobe signal waveform, at nStrobe_1 ^StBe not interfered owing to circuit in the byte transmission cycle, wood interference prevention circuit postponed Tnoise the time after horse back signal is delivered to follow-up module and returns the Busy answer signal, so host computer side parallel port controller can finish this transmission cycle quickly, and message transmission rate is improved; Be interfered owing to control line in the nStrobe_2nd transmission cycle, could " separate out " correct control signal the time delay that this interference protection circuit often needs to add from control signal wire, the width in this transmission cycle is turned down message transmission rate automatically so main frame has to postpone.This shows that the utility model method not only can be eliminated the control line impulse disturbances better, and have the dynamic adjustments ability of certain data transfer rate.

Contrast test shows that additional the utility model scheme has excellent inhibition ability to various control line impulse disturbances on the anti-interference basis of conventional parallel interface.In addition, because that the RC parameter in the control line input circuit can obtain is less, so realize message transmission rate more than the per second 1M Byte being not difficult under the ECP mode of operation.

Claims (2)

1, a kind of jamproof printer parallel interface control system, comprise the IEEE1284 protocol module, the printer controller module, it is characterized in that adding in the control line loop of printer parallel interface digitizing interference prevention module, this digitizing interference prevention module comprises parameter register A, input comparator A, delay counter A, delay comparator A, sampling latch A and sampling latch C, wherein input comparator A Access Control line and sampling latch a-signal, delay counter A and sampling latch A insert the counting controling signal of input comparator A output, and parameter register A connects cpu i/f, and delay comparator A connects the output of delay counter A and parameter register A, sampling latch C accesses the output of sample latch A and delay comparator A, exports control signal by control line to the IEEE1284 protocol module.

2, jamproof printer parallel interface control system as claimed in claim 1 is characterized in that the control line input is by RC low-pass filter network and schmitt reshaper and external interface isolation.

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