CN2697827Y - Internal set type package structure - Google Patents
Internal set type package structure Download PDFInfo
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- CN2697827Y CN2697827Y CNU2004200079265U CN200420007926U CN2697827Y CN 2697827 Y CN2697827 Y CN 2697827Y CN U2004200079265 U CNU2004200079265 U CN U2004200079265U CN 200420007926 U CN200420007926 U CN 200420007926U CN 2697827 Y CN2697827 Y CN 2697827Y
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Abstract
The utility model relates to an internal set type package structure, comprising a ceramic plate board, a ceramic back cover and an interior connecting layer, wherein, the ceramic plate board is provided with a hollow hole which penetrates top and bottom and is used to contain with the chip. The ceramic back cover is arranged on the lower surfaces of the ceramic plate board and the chip and is provided with a plurality of penetrating holes which aim to the metal pad of the surface of the chip. The penetrating holes are filled with plugs which are connected with the metal pad. The interior connecting layer is arranged at the bottom of the ceramic back cover, and transfers the signal generated by the chip to the outside.
Description
Technical field
The utility model relates to a kind of in-building type encapsulating structure (Build-Up Layer Packaging), especially a kind of in-building type encapsulating structure of low-thermal-expansion (Low Thermal Extension Build-up LayerPackaging).
Background technology
Along with the fast development of semiconductor technology, produce the requirement of volume microminiaturization, function diversification and the processing speed of processor.For reaching this requirement, tie point (I/O) quantity that primarily must increase processor is to satisfy the demand that multifunctional signal is handled.One typical method is to make the configuration of tie point by distribution mode around low-density, is transformed into highdensity matrix form distribution (Array Pad) mode.At the same time, for cooperating high-density matrix formula tie point distribution (Pitch≤200 μ m), the encapsulation technology of processor also by conventional wire welding encapsulation (Wire-Bonding) technology, is developed to Flip-Chip Using (the Flip Chip Package) technology that directly links to each other with base plate for packaging through Solder Bumps (Bump).
Please refer to Fig. 1, show a typical flip chip packaging structure.This flip chip packaging structure is respectively made interconnect layer 12 and following interconnect layer 14 in the both sides up and down of core substrate 10 to increase a layer technology (Build-Up Layer) based on a core substrate (Core Substrate) 10.The below of following interconnect layer 14 leads to signal transmission pins 16, correspond to the slot (not icon) on the motherboard, and chip 20 is inverted on the interconnect layer 12, and sees through a plurality of chip 20 lower surfaces that are made in, and the metal coupling 22 that becomes array to distribute is thought connection.As above-mentioned, the signal that chip produced must pass through projection 22, last interconnect layer 12, core substrate 10, following interconnect layer 14 and stitch 16 in regular turn, signal can be passed to the other parts of motherboard.
As above-mentioned, be able to transmitting between the interconnect layer 12 and 14 up and down in order to make signal, (Plated Through Hole, PTH) (not icon) is as the passage that connects must to make via on core substrate 10.Generally speaking, under the thin excessively situation of core substrate, encapsulating structure is easy to generate distortion, and causes the fracture of internal connection line.Therefore, the thickness of core substrate must be improved.Yet, along with the thickness of core substrate improves, except the increase that causes package thickness and interconnect length, also improve on core substrate boring (drilling) simultaneously making the degree of difficulty of via, and the density refractory that causes via is with lifting.This shows that in next generation processor, under the situation that tie point number and density further increase, traditional Flip-Chip Using technology has faced a bottleneck.And bumpless in-building type encapsulation (Bumpless Build-Up Layer Packaging, BBUL) technology is taken advantage of a situation and is risen, with as follow-on encapsulation technology.
Please refer to Fig. 2 A to 2F, show a typical bumpless in-building type package fabrication process.At first shown in Fig. 2 A, in a base plate for packaging 100, make an emptying aperture 102 running through this base plate for packaging 100, and, attach a back cover 110 in the lower surface of this base plate for packaging 100.This back cover 110 also covers the lower surface 102a of aforementioned emptying aperture simultaneously, holds chip (Die) 200 with the space that forms a upward opening.Subsequently, shown in Fig. 2 B, chip 200 is inserted in this emptying aperture 102, and remove back cover 110, make outside the metal gasket 202 of chip 200 lower surfaces is exposed to.
Next, shown in Fig. 2 C, make a dielectric layer 122 at the base plate for packaging 100 and the lower surface of chip 200 and cover each metal gasket 202, and in dielectric layer, get out perforation 124, make outside each metal gasket 202 is exposed to the laser drill technology.Subsequently, shown in Fig. 2 D, make a metal pattern 126 in the lower surface of dielectric layer 122, and this metal pattern 126 is connected to metal gasket 202.Then, shown in Fig. 2 E, repeat the manufacturing process of earlier figures 2C and D, below this metal level 126, make other dielectric layer and metal pattern, to finish the making of interconnect layer 120.At last, shown in Fig. 2 F, make a welding resistance photomask (Solder Mask) 130 again in the lower surface of interconnect layer 120, and use mode of printing (Print) coating scolder (Solder) 140 in the perforate of this welding resistance photomask 130, and then connect stitch 150 on scolder 140, to finish this encapsulation flow process.
As described above, bumpless in-building type encapsulating structure embeds chip 200 in the base plate for packaging 100, and directly at the lower surface of chip 200 and base plate for packaging 100 with built-in layer technology (Build-Up Layer) wiring, draw signal transmission pins 150 subsequently again.With respect to the conventional flip chip encapsulation technology, in the bumpless in-building type encapsulating structure, only need pass through interconnect layer 120 from the signal of chip 200, can be passed to stitch 150 outputs.Therefore, not only reduce package thickness, also reduced the power consumption in the signal transduction process simultaneously.Preresearch estimates, bumpless in-building type encapsulating structure the stray inductance of encapsulating structure can be reduced at least 30%, and therefore the power consumption of signal transmission reduce more than 25% also for the conventional flip chip encapsulation technology.
Secondly, along with the component count increase of processor volume microminiaturization and unit capacity, the time delay (RC time delay) by interconnect caused becomes the main factor that influences assembly operation speed gradually.Generally speaking, the time delay that interconnect caused, the product that is equivalent to the capacitance (C) of dielectric layer between the resistance value (R) of plain conductor and plain conductor, therefore the desire time delay that reduces interconnect has two methods: one is to use metal than low-resistance value, and (for example: copper) as plain conductor, another then is to use the material with low-k K as the dielectric layer between plain conductor.
It should be noted that general employed low-k K material, more fragile than traditional dielectric material, therefore be easy to be subjected to the external force effect and impaired.And, in traditional Flip-Chip Using technology, use projection to connect chip and base plate for packaging, and the dielectric material that covers chip surface often must bear the mechanical external force that projection imposes.Therefore, if the dielectric material of the low-k K of working strength deficiency, the interconnect of chip surface often is damaged easily, and causes the yield of encapsulation finished product to reduce.On the other hand, in bumpless in-building type encapsulation technology, shown in Fig. 2 A, chip 200 embeds in the base plate for packaging 100, and the signal of metal gasket 202 outwards transmits through interconnect layer 120, and does not need to use projection.Thereby can avoid mechanical external force to act on the chip 200, with the problem that prevents to be derived because of the dielectric material that uses low-k K.
But in bumpless in-building type encapsulation technology, chip is made of the low thermal coefficient of expansion material, as: silicon, GaAs etc.; Base plate for packaging is made of high-molecular organic material.That is, what base plate for packaging of chip is made of different materials, and these two kinds of material coefficient of thermal expansion coefficients have evident difference.Illustrate: general base plate for packaging material commonly used, its thermal coefficient of expansion is about 20 * 10
-6/ ℃, and the thermal coefficient of expansion of silicon only has 4.5 * 10
-6/ ℃.Therefore, heating and cooling circulation and chip in package fabrication process operate the variations in temperature that is caused, can on chip and base plate for packaging, produce different change in size amounts, and produce internal stress cause chip and metal level be connected fracture or interconnect chaps, even cause the encapsulating structure inefficacy.
In addition, shown in Fig. 2 C to E, bumpless in-building type encapsulation technology is directly carried out laser drill (Laser Drilling) and built-in layer steps such as (Build-Up Layer) on the surface of base plate for packaging 100 after chip 200 embeds base plate for packaging 100.If above-mentioned laser drill with increase a layer step and flaw occurs, except the yield of meeting influence encapsulation finished product, be difficult to take out and reuse owing to embed the chip 200 of base plate for packaging 100, also can cause the loss of normal chip, and cause packaging cost significantly to rise.
The utility model content
In view of this, the utility model proposes a kind of low-thermal-expansion in-building type encapsulating structure, at traditional Flip-Chip Using technology, the blocked up and high defective that consumed energy of its encapsulating structure improves.
Another purpose of the present utility model is at typical bumpless in-building type encapsulation technology, and the material of chip and base plate for packaging is different and the internal stress that produces proposes solution.Simultaneously, also in the encapsulation step at bumpless in-building type encapsulation technology, the chip that embeds base plate for packaging is difficult to reusable shortcoming, improves.
Low-thermal-expansion in-building type encapsulating structure of the present utility model comprises a ceramic substrate, a ceramic back cover and an interconnect layer.In ceramic substrate, have an emptying aperture that runs through up and down holding chip, and ceramic back cover is positioned at the lower surface of ceramic substrate and chip, and has a plurality of perforation to expose the metal gasket of chip surface.A plurality of conductor connectors are inserted the perforation of ceramic back cover, and are connected to the metal gasket of chip surface, and a wire pattern is positioned at the lower surface of ceramic back cover, and are connected to the conductor connector.The interconnect layer is positioned at the lower surface of this wire pattern and ceramic back cover, so that the chip signal that wire pattern was spread out of is guided to the external world.
Can describe in detail and appended graphic being further understood by following utility model about advantage of the present utility model and spirit.
Description of drawings
Fig. 1 is the generalized section of a typical flip chip packaging structure.
Fig. 2 A to F is the generalized section that a typical bumpless in-building type encapsulating structure carries out the Chip Packaging manufacturing process.
Fig. 3 A to E is that the utility model low-thermal-expansion in-building type encapsulating structure carries out the Chip Packaging manufacturing process, the generalized section of a preferred embodiment.
Fig. 4 is the schematic diagram that the utility model department of computer science unifies preferred embodiment.
The reference numeral explanation
12 times interconnect layer 14 of last interconnect layer
Pin 16,150 projections 22,510
Base plate for packaging 100 emptying apertures 102,312,402
Back cover 110 metal gaskets 202,502
Welding resistance photomask 130 scolders 140
Substrate is given birth to embryo 310 back covers and is given birth to embryo 320
Solid 600 computer systems 700
In-building type encapsulating structure 780 power supply units 790
Embodiment
Please refer to shown in Fig. 3 A to E, carry out a preferred embodiment of Chip Packaging with low-thermal-expansion in-building type encapsulating structure of the present utility model.At first, as shown in Figure 3A, in a ceramic green embryo flat board (not shown), cut out a substrate and give birth to embryo 310, then, make emptying aperture 312 with stamping machine (Puncher) or perforation laser (Via Laser) and run through the upper and lower surface that substrate is given birth to embryo 310.This emptying aperture 312 is in order to hold chip to be packaged.On the other hand, in another thin ceramic green embryo flat board (not shown), cut out a back cover and give birth to embryo 320, this back cover is given birth to the rough aforesaid base plate that is equal to of size of embryo 320 and is given birth to embryo 310.Subsequently, make a plurality of perforation (Via) 322 in wherein with perforation laser.These perforation 322 correspond to the metal gasket of chip surface to be packaged.
Subsequently, shown in Fig. 3 B, give birth in the perforation 322 of embryo, insert conductor connector 330, then, make wire pattern 340 is given birth to embryo 320 in back cover lower surface again at aforementioned back cover.Next, shown in Fig. 3 C, aforesaid base plate is given birth to embryo 310 aim at and pressurize with back cover life embryo 320 and coincide, carry out the manufacturing process of high temperature sintering again.It should be noted that the inside that living embryo 310 of aforesaid base plate and back cover are given birth to embryo 320 has a high proportion of cement (Binder), so that the ceramic powders typing.And the manufacturing process of this high temperature sintering can be removed the cement in living embryo 310 and 320, and the material that sees through between each powder particle is mobile, and ceramic powders is consolidated.Simultaneously,, also there is material to flow, therefore,, can makes substrate give birth to embryo 310 and combine with the living embryo 320 of back cover through this high temperature sintering manufacturing process because substrate is given birth to embryo 310 and back cover is given birth on the composition surface of embryo 320.Also therefore, give birth to embryo 310 and back cover and give birth on the composition surface of embryo 320 enough diffuse are arranged as long as guarantee substrate, substrate 310 can be inequality with back cover 320 employed living embryo materials.
As described above, because high temperature sintering has been removed the cement in the living embryo, substrate is given birth to embryo 310 and is given birth to embryo 320 behind sintering with back cover, and the big appointment of its size reduces 10% to 30% and do not wait.Therefore; when the living embryo 310 of making substrate is given birth to embryo 320 with back cover; must be in advance the minimizing of this size be counted; give birth to the substrate 410 that embryo 310 sintering are produced to guarantee substrate; its inner emptying aperture 402 sizes are enough to hold chip; simultaneously, back cover is given birth to the back cover 420 that embryo 320 sintering are produced, and the metal gasket of chip surface can be aimed in respectively bore a hole 422 position, its inside.
Subsequently, shown in Fig. 3 D,, make interconnect layer 440 to increase a layer technology (Build-up Layer), and this interconnect layer 440 is with the dielectric layer material of organic material as its inside at the lower surface of back cover 420 with wire pattern 340.Generally speaking, aforementioned wire pattern 340 can be the online layer of the fan-out (Fan Out) of a signal line, and from top to bottom also comprise a ground plane 442 and a packaging power accommodating layer 444 at interconnect layer 440, wherein, packaging power accommodating layer 444 provides another driving voltage, exports to outside the encapsulating structure with the signal that chip is produced.In addition, aforementioned wire pattern 340 also can only transmit the usefulness of signal, and interconnect layer 440 from top to bottom includes the online layer of a fan-out, a ground plane and a packaging power accommodating layer at least.It should be noted that in the utility model substrate 410 provides enough intensity,, and have the characteristics of high-density line with the interconnect layer 440 that increases layer fabrication techniques with support interconnect layer 440.
At last, shown in Fig. 3 E, chip is inverted in the emptying aperture 402 of substrate 410, and the metal gasket 502 on chip 500 surfaces is aimed at 422 the position of respectively boring a hole.It should be noted that because chip 500 and substrate 410 constitute by high-intensity ceramic material, therefore, between chip 500 and substrate 410, be filled with solid 600 and think fixed.Simultaneously, for the interior connector 330 of metal gasket 502 and perforation that makes chip surface has good engaging, with regard to a preferred embodiment, can make projection (Bump) 510 on the surface of metal gasket 502, to be connected to connector 330.
Hence one can see that, sees through encapsulating structure of the present utility model, and the signal that chip produces is passed to the lower surface of encapsulating structure according to seeing through metal gasket 502, projection 510, connector 330, wire pattern 340 and interconnect layer 440.And, generally speaking,, can also make a welding resistance photomask (not shown), with the position of definition tie point at the lower surface of this interconnect layer 440.In the opening of welding resistance photomask, make projection (soldered ball) again or draw pin (Pin), so that this encapsulating structure is connected on the motherboard.
Following table shows the material coefficient of thermal expansion coefficient value of generally commonly using in encapsulating structure.As shown in Table, main body (i.e. substrate 410 wherein and back cover 420) that it should be noted that the utility model encapsulating structure is made of ceramic material (comprising glass material).And, with regard to a preferred embodiment, this ceramic material can aluminium nitride (AlN) or carborundum (SiC) as main component.Wherein, illustrate with regard to aluminium nitride: the thermal coefficient of expansion of aluminium nitride is 4.5 * 10
-6/ ℃, be 3 * 10 compared to the thermal coefficient of expansion of silicon (being the constituent of chip)
-6/ ℃, the difference of the two only has 1.5 * 10
-6/ ℃.Therefore, can avoid,, and cause online fracture because of the difference of chip 500 with the material coefficient of expansion of ceramic back cover 420 in the junction of 330 of metal gasket 502 and connectors.
| Material | Thermal coefficient of expansion (* 10 -6/℃) | |
| Conventional package substrates | BT resin (bismaleimide-triazine) | 18 |
| Conventional package substrates | Polyimides (Polyimide, PI) | 21 |
| Ceramic substrate | Aluminium nitride (AlN) | 4.5 |
| Ceramic substrate | Carborundum (SiC) | 4.6 |
| Chip | Silicon (Si) | 3 |
Please refer to shown in Figure 4, the schematic diagram of the utility model computer system 700 1 preferred embodiments.As shown in FIG., this computer system 700 is arranged on the circuit board 800, comprises a bus 720, an internal memory 740, a chip 760, an in-building type encapsulating structure 780 and a power supply unit 790.Wherein, bus 720 is in order to connection internal memory 740, in-building type encapsulating structure 780 and power supply unit 790, and chip 760 directly is installed in in-building type encapsulating structure 780, and through this encapsulating structure 780 signal is passed to bus 720.In order to encapsulate this chip 760, this in-building type encapsulating structure 780 comprises a ceramic substrate, a ceramic back cover and an interconnect layer.In ceramic substrate, have an emptying aperture that runs through up and down holding chip 760, and ceramic back cover is positioned at the lower surface of ceramic substrate and chip 760.Chip 760 is positioned in this emptying aperture in flip-chip (Flip-chip) mode, and sees through the interconnect layer, transmits signal to bus 720.
Above-mentioned chip 760 can be the running of a microprocessor (Microprocessor) with the control computer system, also can be that a System on Chip/SoC is with the signal transmission on the control circuit board.In addition, this chip also can be a communication chip, transmits to carry out wireless or wired signal with construction one communication chip system.
Than traditional Flip-Chip Using technology, the technology that the utility model uses low-thermal-expansion in-building type encapsulating structure to encapsulate has following advantage:
One, in traditional flip chip packaging structure, base plate for packaging with high-molecular organic material (as
BT resin and polyimides) constitute, its thermal coefficient of expansion is hot swollen much larger than chip
Coefficient expands.Therefore, on the composition surface of chip and base plate for packaging, easily because of thermal coefficient of expansion
Difference and produce tangible internal stress, even cause the online disconnected of chip and base plate for packaging
Split.Otherwise base plate for packaging of the present utility model is constituted with ceramic material, and can keep away
Exempt to cause online fracture because of the difference of the coefficient of expansion of chip and ceramic bases.
Two, in traditional flip chip packaging structure, as shown in Figure 1, must provide a core base
Include chip 20, two interconnect layers 12 and 14, and core substrate 10 up and down less
Thickness.Otherwise shown in Fig. 3 E, encapsulating structure of the present utility model is with ceramic base
In the hole 402.Therefore, the thickness of encapsulating structure of the present utility model is lower.
Three, as shown in Figure 1, in the conventional flip chip encapsulating structure, the signal that chip 20 is produced
Otherwise shown in Fig. 3 E, in the encapsulating structure of the present utility model, chip 500 produces
Signal outwards can be transmitted.The distance of signal transmission therebetween is shorter, has also therefore reduced
Power consumption in the signal transduction process.
And, the utlity model has following advantage than typical bumpless in-building type encapsulation technology:
One, shown in Fig. 2 E, in typical bumpless in-building type encapsulation, base plate for packaging 100 with
Macromolecular material (as BT resin and polyimides) formation, its thermal coefficient of expansion is far away
Thermal coefficient of expansion greater than chip 200.Therefore, at chip 200 and base plate for packaging 100
The composition surface, easily the difference because of thermal coefficient of expansion produces tangible internal stress, and causes
Online fracture.Otherwise the utility model adopts ceramic substrate 410 and ceramic back cover 420,
The thermal coefficient of expansion of itself and chip is close, thereby can avoid chip 500 and ceramic back cover
Produce internal stress between 420 and cause online fracture.
Two, shown in Fig. 2 A and B, in typical bumpless in-building type encapsulation, chip 200 exists
The beginning step of package fabrication process promptly embeds among the base plate for packaging 100.Therefore, if
Be flaw to occur in the step of subsequent figure 2C to E, except the yield of influence encapsulation finished product,
The chip 200 that embeds base plate for packaging often must be given up in the lump together with base plate for packaging 100.
Otherwise, in the low-thermal-expansion in-building type encapsulation technology of the present utility model, shown in Fig. 3 E,
Can after definite encapsulating structure be normal, again chip 500 be inserted, and can avoid aforementioned
Because of the chip that flaw the caused consume of encapsulating structure, to reduce packaging cost.
In addition, the utility model proposes a kind of chip packaging method, at first, give birth to embryo with ceramic material one substrate, correspond to chip and have an emptying aperture in the living embryo of this substrate, simultaneously, also give birth to embryo with ceramic material one back cover, and have a plurality of perforation in the living embryo of this back cover, correspond to the metal gasket of chip surface respectively.Subsequently, insert conductor and plug in the perforation, and make wire pattern is given birth to embryo at this back cover lower surface.Next, back cover is given birth to embryo and the tight pressing of the living embryo of substrate, and carry out high temperature sintering, with back cover and the substrate that forms mutual binding, wherein, back cover is given birth to the embryo sintering by back cover and is formed, and substrate is formed by the living embryo sintering of substrate.Then, make the lower surface of interconnect layer to increase layer mode at back cover.At last, again chip to be packaged is inverted in the emptying aperture of back cover, and, the metal gasket that is positioned at chip surface is connected to respectively is positioned at the conductor connector of boring a hole.
Though the utility model discloses as above with preferred embodiment; yet it is not in order to limit the utility model; those skilled in the art is not in breaking away from spirit and scope of the present utility model; can do a little change and retouching, therefore protection range of the present utility model should with accompanying Claim the person of being defined be as the criterion.
Claims (9)
1. an in-building type encapsulating structure is characterized in that, this encapsulating structure comprises:
One chip has the lower surface that a plurality of metal gaskets are made in this chip;
One ceramic substrate has an emptying aperture that runs through up and down to hold this chip;
One ceramic back cover is positioned at the lower surface of this ceramic substrate and this chip, has a plurality of perforation to expose this metal gasket;
A plurality of conductor connectors fill in this perforation, and are electrically connected to this metal gasket;
One wire pattern is positioned at the lower surface of this pottery back cover, and connects this conductor connector; And
One interconnect layer is positioned at the lower surface of this wire pattern and this pottery back cover.
2. encapsulating structure as claimed in claim 1 is characterized in that, this ceramic substrate and this pottery back cover combine through hot pressing and sintering technique.
3. encapsulating structure as claimed in claim 1 is characterized in that, also comprises a plurality of projections, places the surface of this metal gasket respectively, in order to connect this metal gasket and this conductor connector.
4. encapsulating structure as claimed in claim 1 is characterized in that, also comprises a welding resistance photomask, is made in the lower surface of this interconnect layer.
5. encapsulating structure as claimed in claim 4 is characterized in that, also comprises a plurality of stitch, soldered ball or producing lug in the opening of this welding resistance photomask, and electrically connects this metal gasket through this interconnect layer.
6. encapsulating structure as claimed in claim 1 is characterized in that, this wire pattern is the online layer of the fan-out of a signal line.
7. encapsulating structure as claimed in claim 1 is characterized in that, this interconnect layer comprises the online layer of at least one ground plane, a packaging power accommodating layer and a fan-out.
8. encapsulating structure as claimed in claim 1 is characterized in that, this interconnect layer is with built-in layer fabrication techniques.
9. encapsulating structure as claimed in claim 1 is characterized in that, this wire pattern is a metal pattern layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2004200079265U CN2697827Y (en) | 2004-03-12 | 2004-03-12 | Internal set type package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2004200079265U CN2697827Y (en) | 2004-03-12 | 2004-03-12 | Internal set type package structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2697827Y true CN2697827Y (en) | 2005-05-04 |
Family
ID=34768026
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNU2004200079265U Expired - Lifetime CN2697827Y (en) | 2004-03-12 | 2004-03-12 | Internal set type package structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2697827Y (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104952745A (en) * | 2015-07-08 | 2015-09-30 | 华进半导体封装先导技术研发中心有限公司 | Fan-out package structure adopting late chip assembly and production technology of fan-out package structure |
| CN104966677A (en) * | 2015-07-08 | 2015-10-07 | 华进半导体封装先导技术研发中心有限公司 | Fan out type chip package device and preparation method thereof |
| CN105047630A (en) * | 2015-07-08 | 2015-11-11 | 华进半导体封装先导技术研发中心有限公司 | Chip back assembly active buried structure and manufacturing process thereof |
-
2004
- 2004-03-12 CN CNU2004200079265U patent/CN2697827Y/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104952745A (en) * | 2015-07-08 | 2015-09-30 | 华进半导体封装先导技术研发中心有限公司 | Fan-out package structure adopting late chip assembly and production technology of fan-out package structure |
| CN104966677A (en) * | 2015-07-08 | 2015-10-07 | 华进半导体封装先导技术研发中心有限公司 | Fan out type chip package device and preparation method thereof |
| CN105047630A (en) * | 2015-07-08 | 2015-11-11 | 华进半导体封装先导技术研发中心有限公司 | Chip back assembly active buried structure and manufacturing process thereof |
| CN104952745B (en) * | 2015-07-08 | 2017-12-22 | 华进半导体封装先导技术研发中心有限公司 | Fan-out package structure and its production technology are assembled after chip |
| CN104966677B (en) * | 2015-07-08 | 2018-03-16 | 华进半导体封装先导技术研发中心有限公司 | Fan-out-type chip package device and preparation method thereof |
| CN105047630B (en) * | 2015-07-08 | 2018-05-22 | 华进半导体封装先导技术研发中心有限公司 | Active embedment encapsulating structure and its production technology are assembled after chip |
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Expiration termination date: 20140312 Granted publication date: 20050504 |