CN2669486Y

CN2669486Y - Multi-clock frequency changing circuit

Info

Publication number: CN2669486Y
Application number: CNU2003201225743U
Authority: CN
Inventors: 彬王; 王彬
Original assignee: Shanghai Huahong Integrated Circuit Co Ltd
Current assignee: Shanghai Huahong Integrated Circuit Co Ltd
Priority date: 2003-12-18
Filing date: 2003-12-18
Publication date: 2005-01-05
Anticipated expiration: 2013-12-18

Abstract

The utility model discloses a multi-clock frequency changing circuit, aiming to provide a changing circuit which can implement seamless transition in different clock frequency. The utility model comprises a clock synchronizer and a clock gating circuit; the clock synchronizer is composed of a D flip-flop which respectively synchronizes the inceptive clock and the destination clock; the gating circuit comprises two or gates and one and gate, making the same clock only output one path clock signal and isolating the original all the time, so the desired clock is created ultimately.

Description

Clock frequency switching circuit for a long time

Technical field

The utility model relates to a kind of commutation circuit of the frequency of clock for a long time, in particular, relates to Circuits System seamlessly switches to another kind of operating frequency from a kind of operating frequency commutation circuit structure.

Background technology

At present, in many application, particularly in the portable use, often need under multiple clock frequency, switch.For example, when adopting powered battery, make circuit working under lower frequency, thereby reduce power consumption.

But there is following problem in the present commutation circuit of clock for a long time when carrying out the clock switching:

1. be easy to generate metastable state, cause circuit state uncertain.When a kind of clock frequency switches to another clock frequency, if these two kinds of clocks are non-homogeneous clocks, cause trigger to be in metastable state easily, thereby make circuit be in unpredictable state, thereby reduce the fail safe of circuit, and cause function to be made mistakes.

2. when carrying out the clock switching, can produce burr on clock signal, this burr also can cause the reduction of fail safe and circuit function to be made mistakes.

The drawback of poor stability, the poor stability when deficiency on these prior aries has caused clock to switch.

The utility model content

The purpose of this utility model is the above-mentioned deficiency at prior art, proposes a kind of commutation circuit that can realize seamless transitions under the different clock frequencies.

Above-mentioned purpose of the present utility model is achieved through the following technical solutions: comprise clock synchronizer and clock gating circuit; Described clock synchronizer is made of d type flip flop, and initial clock and target clock are carried out respectively synchronously; Clock clk1 imports the clock end of described d type flip flop 1 and the clock end of described d type flip flop 3 respectively; Clock clk2 imports the clock end of described d type flip flop 2 and the clock end of described d type flip flop 4 respectively; The D end input control switching signal of described d type flip flop 1, the S end links to each other with the output Q3 of d type flip flop 3, and output Q1 links to each other with the D end of d type flip flop 4 after anti-phase; The D of described d type flip flop 2 end is provided with not gate 10, makes the control switching signal of D end input after anti-phase, and the S end links to each other with the output Q4 of d type flip flop 4, and output Q2 holds with the D of d type flip flop 3 after anti-phase and links to each other; Between the D of the output Q1 of described d type flip flop 1 and described d type flip flop 4 end, be provided with not gate 8; Between the D of the output Q2 of described d type flip flop 2 and described d type flip flop 3 end, be provided with not gate 9; Described gating circuit comprises 2 or 5,6 and one and door 7, makes same clock can only export one tunnel clock signal, with original isolating all the time, finally generates required clock; Described or door 5 with the output signal of described d type flip flop 1 and clock clk1 mutually or; Described or door 6 with the output signal of described d type flip flop 2 and clock clk2 mutually or; Described and door 7 will be described or the output signal of door 5,6 and back export clock signal clk_out after the switching.

Compare with prior art, the utlity model has following beneficial effect: no matter solved the switching problem under the multiple clock frequency, still be non-homogeneous clock for the homology clock, can switch easily, eliminate sub state, filtered burr, increased stability and fail safe.

Description of drawings

Fig. 1 is the circuit theory diagrams of the utility model double-interface card Working mode switching method.

Embodiment

Below in conjunction with drawings and Examples the utility model is further described.

As shown in Figure 1, clock clk1 imports the clock end of d type flip flop 1 and the clock end of d type flip flop 3 respectively; Clock clk2 imports the clock end of d type flip flop 2 and the clock end of d type flip flop 4 respectively; The D end input control switching signal of d type flip flop 1, the S end links to each other with the output Q3 of d type flip flop 3, and output Q1 links to each other with the D end of d type flip flop 4 after anti-phase; The D of d type flip flop 2 end is provided with not gate 10, makes the control switching signal of D end input after anti-phase, and the S end links to each other with the output Q4 of d type flip flop 4, and output Q2 holds with the D of d type flip flop 3 after anti-phase and links to each other; Between the D of the output Q1 of d type flip flop 1 and d type flip flop 4 end, be provided with not gate 8; Between the D of the output Q2 of d type flip flop 2 and d type flip flop 3 end, be provided with not gate 9; Or door 5 with the output signal of d type flip flop 1 and clock clk1 mutually or; Or door 6 with the output signal of d type flip flop 2 and clock clk2 mutually or; With door 7 will or the output signal of door 5,6 and back output switching after clock signal clk_out.

The significance signal of top-level module is as shown in table 1.

Significance signal in table 1 clock switch circuit

Signal	Direction	Meaning	Remarks
Signal	Direction	Meaning	Remarks	?switch	?IN	The clock switching signal	0: select clk1 1: select clk2
?Clk1	?IN	Clock 1		?switch	?IN	The clock switching signal	0: select clk1 1: select clk2
?Clk1	?IN	Clock 1		?Clk2	?IN	Clock 2
?Clk_out	?OUT	Clock signal after the switching		?Clk2	?IN	Clock 2

Clock switch circuit provided by the utility model can seamlessly switch between homology clock and non-homogeneous clock, metastable state when it can eliminate switching and the burr on the clock signal.Its operation principle is: after control switching signal switch enters this circuit, be divided into two-way:

One the tunnel directly delivers to the synchronizer circuit of clk1 clock zone, and the signal after is Q1 synchronously.The Q1 signal deliver to clock clk1 or door 5 in, carry out gate operation, obtain the clk1_gate signal;

Another kind is delivered to earlier in the not gate 8, obtains ~ switch, and this signal is delivered to the synchronous circuit of clk2 clock zone, and the signal after is Q2 synchronously.Signal Q2 delivers to clock clk2 or door 6, carries out the gate operation, obtains the clock signal clk2_gate of clk2 behind gate.

This two-way clock signal of Clk1_gate and clk2_gate is again by carrying out and operation, the clock signal clk_out after finally obtaining switching with door 7.

After guaranteeing that control signal Q1 and Q2 in the gating circuit can be ineffective simultaneously, in this circuit, introduced following measure: Q1 and Q2 to pass through not gate 8 and not gate 9 respectively earlier, receive the D end of d type flip flop (4,3) respectively.For fear of the appearance of burr, asserts signal at first will be carried out with another clock synchronously.

1. metastable elimination

Clock switches and is mainly undertaken by trigger.When non-homogeneous clock switches, may cause the metastable state in the circuit.For eliminating metastable state, adopted synchronizer circuit in the clock switch circuit.This circuit carries out control signal and source clock and target clock respectively synchronously, thereby guarantees for any one trigger in the circuit, before and after switching, clock signal and data-signal all be pass through synchronous, thereby eliminated metastable state.

2. the filtration of burr

Burr on the clock signal may have a strong impact on circuit function.In order to filter the burr in the circuit, above-mentioned synchronizer circuit and gating circuit combine, and can eliminate in handoff procedure.

Because gate-control signal and clock signal are asynchronous, this may cause the burr on the clock.By introducing two synchronizer circuits, can eliminate this hidden danger.

For certain trigger in the synchronizer, its set end and clock are asynchronous, and this also may introduce burr.Therefore, in circuit, introduced another again to synchronizer circuit.Asserts signal is at first passed through synchronizer, carries out synchronously with another clock, receives on the trigger of synchronizer of another clock zone again, with the shielding control signal corresponding.

In sum, the asynchronous burr that causes of asserts signal and clock signal is filtered by latter two trigger in the synchronizer; Burr possible on the clock gated logic is filtered by preceding two triggers in the synchronizer.Like this, no matter switch generation at any time, appearance that can be not jagged.

Claims

1, a kind of frequency switching circuit of clock for a long time is characterized in that: comprise clock synchronizer and clock gating circuit; Described clock synchronizer is made of d type flip flop, and initial clock and target clock are carried out respectively synchronously;

Clock clk1 imports the clock end of described d type flip flop (1) and the clock end of described d type flip flop (3) respectively; Clock clk2 imports the clock end of described d type flip flop (2) and the clock end of described d type flip flop (4) respectively;

The D end input control switching signal of described d type flip flop (1), the S end links to each other with the output Q3 of d type flip flop (3), and output Q1 links to each other with the D end of d type flip flop (4) after anti-phase;

The D of described d type flip flop (2) end is provided with not gate (10), makes the control switching signal of D end input after anti-phase, and the S end links to each other with the output Q4 of d type flip flop (4), and output Q2 holds with the D of d type flip flop (3) after anti-phase and links to each other;

Between the D of the output Q1 of described d type flip flop (1) and described d type flip flop (4) end, be provided with not gate (8); Between the D of the output Q2 of described d type flip flop (2) and described d type flip flop (3) end, be provided with not gate (9);

Described gating circuit comprises 2 or (5,6) and one and door (7), makes same clock can only export one tunnel clock signal, with original isolating all the time, finally generates required clock;

Described or door (5) with the output signal of described d type flip flop (1) and clock clk1 mutually or; Described or door (6) with the output signal of described d type flip flop (2) and clock clk2 mutually or; Described and door (7) will be described or the output signal of door (5,6) and back export clock signal clk_out after the switching.