CN2634530Y - Bus interface circuit - Google Patents
Bus interface circuit Download PDFInfo
- Publication number
- CN2634530Y CN2634530Y CN 03256071 CN03256071U CN2634530Y CN 2634530 Y CN2634530 Y CN 2634530Y CN 03256071 CN03256071 CN 03256071 CN 03256071 U CN03256071 U CN 03256071U CN 2634530 Y CN2634530 Y CN 2634530Y
- Authority
- CN
- China
- Prior art keywords
- interface circuit
- bus
- signal wire
- equipment
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Small-Scale Networks (AREA)
Abstract
The utility model relates to a bus interface circuit arranged between the controller in security technology precaution field and the monitored equipment which is provided with address coding. The bus interface circuit comprises a signal wire, ground wire, a first interface circuit, a second interface circuit, a third interface circuit and a fourth interface circuit and is further provided with transmission protocol. An output interface of a first chip of the controller is accessed to the signal wire via the first interface circuit; the signal wire is accessed to an input interface of the device via the third interface circuit, an output interface of the device is accessed to the signal wire via the fourth interface circuit, and the signal wire is accessed to the input interface of the first chip via the second interface circuit, the signal wire transits the inspection tour and command of the controller and the response signal which the equipment gives to the controller. The utility model can further be provided with a power source wire that supplies power to the equipment. The bus interface circuit of the utility model has less engineering layout and more monitoring equipment, which facilitates to expand the system capacity.
Description
Technical field
The utility model relates to the safety technological guard field, particularly relates to the bus interface circuit between safety technological guard field middle controller and its watch-dog.
Background technology
In the safety technological guard field, the anti-theft and alarm device adopts the multiple-way system bus interface to the monitoring of equipment more at present, is generally five-wire system and four-wire system, and wherein power drives, monitoring, control take lead respectively.The five-wire system bus interface is provided with a power lead, a power ground, a monitor signal line, a control signal wire and a signal ground.The four-wire system bus interface is provided with the ground wire of a power lead, a monitor signal line, a control signal wire and a power supply/signal common.The multiple-way system bus interface has a watch-dog in engineering few, and wiring is many, and power system capacity is not easy problems such as expansion, brings a lot of inconvenience to the engineering practical application.
The utility model content
The purpose of this utility model is to overcome the problem that above prior art exists, a kind of bus interface circuit is provided, reduce the wiring of engineering bus interface to be used for the safety technological guard field, but increase the quantity of watch-dog, and the monitoring to equipment can navigate on definite device address, and makes things convenient for the expanding system capacity.
For achieving the above object, the utility model provides a kind of bus interface circuit, comprise signal wire, two buses of ground wire and have host-host protocol, be characterized in that described bus interface circuit is arranged between the controller and its equipment of monitoring in the safety technological guard field, this equipment has geocoding; Described bus interface circuit also comprises four interface circuits, and wherein first interface circuit is an amplification and rectification circuit, and second interface circuit is lowering and stabilizing blood pressure and shaping circuit, and the 3rd interface circuit comprises filtering shaping circuit, and the 4th interface circuit is an amplification and rectification circuit; One delivery outlet of first chip of described controller inserts signal wire through first interface circuit, this signal wire is through the 3rd interface circuit access device one input port, equipment one delivery outlet inserts signal wire through the 4th interface circuit, this signal wire is connected to an input port of first chip through second interface circuit, and described signal wire transfer control is given the answer signal of controller to the patrolling and examining of equipment, order and equipment.
Described signal wire is also to power devices.
Described the 3rd interface circuit also comprises the energy storage energy supply circuit, described signal wire through this energy storage energy supply circuit to power devices.
Described signal wire is connected to second chip, one input port of equipment through the output terminal of the 3rd interface circuit, and the 3rd chip one delivery outlet of equipment is connected on the signal wire through the 4th interface circuit.
Described second chip is the VD5027 chip, and the 3rd chip U3 is the LM331 chip, and the host-host protocol of described bus interface circuit is 1100*[HIGH]+[HEAD]+8 bit address sign indicating number+4 bit data positions+[TAL]+500 microsecond time-delay+9 millisecond counters counting.
Described signal wire is connected to four-core sheet one input port of equipment through the output terminal of the 3rd interface circuit, and this four-core sheet one delivery outlet is connected on the signal wire through the 4th interface circuit.
Described signal wire is for there being the polarity bus.
Described signal wire BUS
+Be nonpolarity bus.
Described the 3rd interface circuit is provided with Yi Qiaodui, and signal wire and ground wire insert the 3rd interface circuit through this bridge heap.
Described bus interface circuit also comprises a power lead to power devices.
The utility model bus interface circuit is finished to the monitoring and the control of equipment the controller in the safety technological guard field with a signal wire, simultaneously also can be with power drives line and this signal wire time-sharing multiplex, can by three-wire system bus interface and two-wire system bus interface dual mode and by computer programming finish controller to the monitoring of equipment and control and equipment to the replying of controller, the engineering wiring is few; And the utility model can make a plurality of equipment by being connected in parallel on two/three buses by being provided with of its bus interface, and the equipment that can monitor is many; The utility model can navigate to the monitoring of equipment and determine on the device address in addition, and as long as system is and the equipment that connects different geocodings expanding system capacity easily.
Below in conjunction with accompanying drawing and embodiment the utility model is further described.
Description of drawings
Fig. 1 is the circuit theory diagrams of the utility model first embodiment.
Fig. 2 is the circuit theory diagrams of the utility model second embodiment.
Fig. 3 is the circuit theory diagrams of the utility model the 3rd embodiment.
Embodiment
The utility model bus interface circuit is arranged between controller in the safety technological guard field and the equipment to realize monitoring and the control of controller to equipment, and the utility model requirement equipment has geocoding.The utility model bus interface circuit is finished to the monitoring and the control of equipment the controller in the safety technological guard field with a signal wire, also power drives line and this signal wire time-sharing multiplex can be had three-wire system bus interface and two-wire system bus interface dual mode simultaneously.The three-wire system bus interface is provided with a power lead, signal wire and power lead and the shared ground wire of signal wire, and wherein power lead is used for power supply, and the signal wire transfer control is given the answer signal of controller to the patrolling and examining of equipment, order and equipment.The signal wire of two-wire system bus interface and power lead share a bus, and this bus not only had been used to power but also transfer control is given the answer signal of controller to the patrolling and examining of equipment, order and equipment, and another root bus then is with reference to ground wire.
Can divide because of the two-wire system bus interface has polarity and nonpolarity two kinds, and the signal that the polarity bus is wherein arranged is a voltage signal, the different amplitudes of voltage, width means unlike signal; The signal of nonpolarity bus is a current signal, and the expression unlike signal that varies in size of electric current below is that the utility model is described in further detail for example so that polarity and non-polar two-wire system bus interface to be arranged respectively.
The utility model first embodiment for polarity two-wire system bus interface is arranged, is provided with signal wire BUS as shown in Figure 1
+, ground wire BUS
-Two buses and four interface circuits.These four interface circuits are that controller is to signal wire BUS
+The first interface circuit BLOCK1 of last signaling, controller acknowledge(ment) signal line BUS
+The second interface circuit BLOCK2 of last signal, equipment acknowledge(ment) signal line BU
S+ go up the 3rd interface circuit BLOCK3 of signal, equipment is to signal wire BUS
+The 4th interface circuit BLOCK4 of signaling.
Wherein the first interface circuit BLOCK1 is an amplification and rectification circuit, is provided with two NPN triode T1, T2, and the base stage of its second triode T2 is connected to the collector of the first triode T1, and the emitter of these two triode T1, T2 links to each other through resistance.Input signal can be through the input of the base stage of the first triode T1, through first, second triode T1, T2, exports signal wire BUS from the emitter of the second triode T2 to through diode
+, the first interface circuit BLOCK1 exports after input signal can being amplified shaping thus.
The second interface circuit BLOCK2 is lowering and stabilizing blood pressure and shaping circuit, is provided with resistance, stabilivolt and two NPN triode T3, T4.Signal wire BUS
+Input signal import the base stage of the 3rd triode T3 through resistance, stabilivolt, the collector of the 3rd triode T3 inserts the base stage of the 4th triode T4, the collector of the 3rd, the 4th triode T3, T4 connects high level through resistance respectively, grounded emitter.Signal wire BUS thus
+Signal after the shaping of resistance, stabilivolt step-down, voltage stabilizing and triode by the output of the collector of the 4th triode T4.Signal wire BUS
+Resistance grounded.Ground wire BUS
-Ground connection.
The 3rd interface circuit BLOCK3 comprises two parts circuit, and first is the energy storage energy supply circuit, is provided with diode and a pair of storage capacitor, the signal on the signal wire BUS can be by two u utmost point Guan Houxiang storage capacitors chargings so that provide power supply for equipment.Second portion is a filtering shaping circuit, signal wire BUS
+Insert the base stage of the 5th triode T5 through resistance, the emitter of the 5th triode T5 and the 6th triode T6 connects high level through diode respectively, the 5th triode T5 and the 6th triode T6 are the PNP triode, and output signal is from the collector output of the 6th triode T6.Ground wire BUS
-Ground connection.
The 4th interface circuit BLOCK4 is an amplification and rectification circuit, and input signal is imported after resistance is imported the 7th triode T7 base stage from its DATAOUT mouth, and through a diode signal is delivered to signal wire BUS again after the emitter output by the 7th triode T7
+On.The emitter resistance grounded of the 7th triode T7, collector connects high level.
The first chip U1 is that controller output end starts to control the chip of making usefulness among Fig. 1, and the second chip U2 and the 3rd chip U3 are the equipment end chip, the signal wire BUS of controller end and equipment end
+, ground wire BUS
-Directly link together.In the present embodiment, the first chip U1 selects 77E58 for use, and the second chip U2 selects VD5027 for use, and the 3rd chip U3 selects LM331 for use.
At control end, the P20 mouth of the first chip U1 connects the input end of the first interface circuit BLOCK1 as delivery outlet, and the delivery outlet of the first interface circuit BLOCK1 inserts signal wire BUS
+, then the signal of the first chip U1 is delivered to signal wire BUS through the first interface circuit BLOCK1
+On, controller is to signal wire BUS thus
+Send signal.Signal wire BUS
+Insert the second interface circuit BLOCK2, the signal on it is delivered to the first chip U1 input port P21 after the second interface circuit BLOCK2 step-down, voltage stabilizing and shaping, so controller received signal line BUS
+On signal.
In equipment end, signal wire BUS
+Be divided into two-way after inserting the 3rd interface circuit BLOCK3, the diode of leading up to charges to storage capacitor, for equipment provides power supply; Deliver to the input end DATAIN of the second chip U2 of equipment end after the filtered shaping in another road from the collector output of the 6th triode T6 of the 3rd interface circuit BLOCK3, thus equipment end acknowledge(ment) signal line BUS
+On signal.The second chip U2 received signal line BUS
+On signal and judge whether this signal issues the signal of oneself, and data bit is delivered to D0～D3.The device signal that equipment end detects (fault, alert, normal etc. three kinds of status signals) is converted into voltage signal and delivers to the 7th pin of the 3rd chip U3, carry out V/F (voltage/frequency) conversion through the 3rd chip U3, the pulse signal that obtains is exported through its 3rd pin DATAOUT, this output signal is delivered to the input end of the 4th interface circuit BLOCK4, delivers to signal wire BUS after the 4th interface circuit BLOCK4 amplifies shaping
+On, so equipment end is delivered to signal wire BUS with signal
+On.
In sum, the first interface circuit BLOCK1 of the utility model bus interface circuit, signal that the first chip U1 is sent amplifies to be shaped as and is convenient to signal wire BUS
+The signal that transmits; The 3rd interface circuit BLOCK3 is with signal wire BUS
+Be divided into two, one for equipment provides power supply, and the signal on another is shaped as the signal that the second chip U2 of equipment end can receive and sends to the second chip U2; The 4th interface circuit BLOCK4 sends equipment end and the answer signal after its 3rd chip U3 handles amplifies to be shaped as and is convenient to signal wire BUS
+The signal of last transmission; Again by the second interface circuit BLOCK2 with signal wire BUS
+On this answer signal be shaped as the signal that the first chip U1 can receive.
In addition, because in the utility model bus interface transmission mode, controller and equipment can send data on bus, in order to prevent data collision, need the host-host protocol that both sides admit.This agreement comprises data definition and time coordination.The second chip U2 is different with the 3rd chip U3's, affects the difference of agreement to a great extent.When the second chip U2 selects VD5027, when the 3rd chip U3 selected LM331, the agreement middle controller of first embodiment was to signal wire BUS
+The sign indicating number of sending out must be the VD5027 sign indicating number, otherwise VD5027 is not familiar with controller received signal line BUS
+On when sign indicating number, its decoding rule must be abideed by the signaling rule of LM331, otherwise the sign indicating number that translates is wrong.As follows:
The data definition of VD5027: 8 address bit+4 data bit
[LOW]=45 microsecond low level; [HIGH]=45 microsecond high level
[OPEN]＝[LOW]+7*[HIGH]+[LOW]+[HIGH]+6*[LOW]
[LOG0]＝[LOW]+[HIGH]+7*[LOW]+[HIGH]+6*[LOW]
[LOG1]＝[LOW]+7*[HIGH]+[LOW]+7*[HIGH]
[HEAD]＝48*[LOW]
[TAL]＝[LOG1]+[LOG0]
During signaling, send out address bit earlier, send out data bit again, address bit and data bit all are to send out low level earlier to send out a high position again.Press the rule of VD5027, send out before the address bit, send out a HEAD sign indicating number, distribute data bit and send out a TAL sign indicating number as end mark.
LM331 is a V/F converter, and transformation result is 9 milliseconds a count pulse, the state difference that equipment detects, the number difference of pulse.
Finish to do well from the VD5027 signaling, need 500 microseconds (different state detection circuits need asynchronism(-nization)) to Equipment Inspection.
Because be that power lead, signal wire are multiplexing, so need charging before the signaling, 50 milliseconds it is enough.
So the agreement of embodiment 1 is:
1100*[HIGH]+[HEAD]+8 bit address sign indicating number+4 bit data positions+[TAL]+500 microsecond time-delay+9 millisecond counters counting
The utility model second embodiment as shown in Figure 2, also for polarity two-wire system bus interface is arranged, its with the different functions of the second chip U2 and the 3rd chip U3 that are of first embodiment by a chip---four-core sheet U23 finishes.Four-core sheet U23 selects PIC712 for use in the present embodiment.
This four-core sheet U23 is by the 3rd interface circuit BLOCK3 received signal line BUS
+On data, and decipher according to agreement.The detectable signal of equipment is converted into voltage signal, delivers to the RA0 mouth of four-core sheet, the four-core sheet with signal Processing after according to result to signal wire BUS
+On data give a response, i.e. answer signal, answer signal is delivered to the 4th interface circuit BLOCK4 input end by delivery outlet DATAOUT.
Because the first chip U1 selects for use 77E58 and four-core sheet U23 to select PIC712 for use, this two chip can be programmed, so the data definition of second embodiment can freely be reached an agreement on by control end and equipment end both sides, needs only and guarantees that signal is undistorted; The coordination of time also can mutual agreement, only otherwise influence signals collecting, processing gets final product.
The utility model the 3rd embodiment is nonpolarity two-wire system bus interface as shown in Figure 3, and its four interface circuit BLOCK1, BLOCK2, BLOCK3 and BLOCK4 are different with second embodiment's.
The second triode T2 of the first interface circuit BLOCK1 is the PNP pipe, and its collector directly meets signal wire BUS
+The second interface circuit BLOCK2 is provided with stabilivolt and parallel resistor and electric capacity, signal wire BUS
+Behind stabilivolt, export the P21 mouth of the first chip U1 to, and through this resistance and capacity earth.
The 3rd interface circuit BLOCK3 first and the second portion circuit, sets up Yi Qiaodui, the signal wire BUS among this embodiment in second embodiment
+With ground wire BUS
-Directly receive device interior unlike first and second embodiment, but be connected to device interior by the bridge heap of the 3rd interface circuit BLOCK3, signal wire is BUS behind the bridge heap
++, ground wire is GND.Signal wire BUS
++On signal import first and the second portion circuit of the 3rd interface circuit BLOCK3, finish the function that power supply and signal shaping are provided for equipment.Equipment end receives BUS
++The receiving course of last signal and first embodiment, second embodiment receive BUS
+Reception process identical.
The 4th interface circuit BLOCK4 is connected to the signal wire BUS of the 3rd interface circuit
++And between ground wire GND, be provided with the 7th triode T7 and resistance R.Input signal is imported the 7th triode T7 base stage from its DATAOUT mouth, and delivers to signal wire BUS by the collector output of the 7th triode T7
++On, the grounded emitter of the 7th triode T7.
The current signal of controller is delivered to signal wire BUS by the first interface circuit BLOCK1 with signal by the P20 mouth output of the first chip U1
+Signal wire BUS
+Signal through the second interface circuit BLOCK2, give the input port P21 of the first chip U1.Signal wire BUS
+On signal be delivered to the DATAIN end of four-core sheet U23 through the 3rd interface circuit BLOCK3.Four-core sheet U23 is to the processing procedure of data on the signal wire and identical with second embodiment to the processing procedure of detectable signal.Four-core sheet U23 delivers to answer signal the DATAOUT end of the 4th interface circuit BLOCK4 by the RA1 mouth.This answer signal is controlled the triode among the 4th interface circuit BLOCK4, thereby changes the electric current on the bus.
What second embodiment was identical together is that the host-host protocol of this embodiment is consulted by both party.
The key distinction of three-wire system bus interface and two-wire system bus interface is that the three-wire system bus interface also is provided with a power lead in the utility model, in order to power supply, its signal wire is used for transfer control the patrolling and examining of equipment, order and equipment is given the answer signal of controller and power supply is not provided.Before two-wire system bus interface middle controller is wanted signaling thus, must give equipment charge earlier, and three buses have been shaped on a power lead, then do not need charging.Therefore acting in three-wire system bus interface and the two-wire system bus interface of the 3rd interface circuit BLOCK3 also distinguished to some extent: in the two-wire system, the 3rd interface circuit BLOCK3 is with signal wire BUS
+Be divided into two, one for equipment provides power supply, the signal that another second chip U2 that is shaped as detecting devices can receive; Three-wire system the 3rd interface circuit BLOCK3 directly is the acceptable signal of the second chip U2 of detecting devices with the signal shaping on the signal wire.In the three-wire system bus interface, power lead is identical with ground wire, all is that direct slave controller end wins over.
The utility model bus interface circuit is arranged between controller in the safety technological guard field and the equipment to realize monitoring and the control of controller to equipment, controller is finished with a signal wire the monitoring and the control of equipment, simultaneously also can be with power drives line and this signal wire time-sharing multiplex, promptly by three-wire system bus interface and two-wire system bus interface dual mode and by computer programming finish controller to the monitoring of equipment and control and equipment to the replying of controller, make that the bus interface wiring is few in the engineering; And the utility model can make a plurality of equipment by being connected in parallel on two/three buses by being provided with of its bus interface, makes its equipment that can monitor increase; Bus interface transmission mode requirement equipment of the present utility model in addition has geocoding, can navigate to the monitoring of equipment and determine on the device address, system as long as and connect the equipment of different geocodings can the expanding system capacity.
Claims (10)
1, a kind of bus interface circuit comprises signal wire BUS
+, ground wire BUS
-Two buses and have host-host protocol is characterized in that described bus interface circuit is arranged between the controller and its equipment of monitoring in the safety technological guard field, and this equipment has geocoding; Described bus interface circuit also comprises four interface circuits, wherein the first interface circuit BLOCK1 is an amplification and rectification circuit, the second interface circuit BLOCK2 is lowering and stabilizing blood pressure and shaping circuit, the 3rd interface circuit BLOCK3 comprises filtering shaping circuit, and the 4th interface circuit BLOCK4 is an amplification and rectification circuit; The delivery outlet of the first chip U1 of described controller inserts signal wire BUS through the first interface circuit BLOCK1
+, this signal wire BUS
+Through the 3rd interface circuit BLOCK3 access device one input port, equipment one delivery outlet inserts signal wire BUS through the 4th interface circuit BLOCK2
+, this signal wire BUS
+Be connected to the input port of the first chip U1, described signal wire BUS through the second interface circuit BLOCK2
+Transfer control is given the answer signal of controller to the patrolling and examining of equipment, order and equipment.
2, bus interface circuit according to claim 1 is characterized in that described signal wire BUS
+Also to power devices.
3, bus interface circuit according to claim 1 is characterized in that described the 3rd interface circuit BLOCK3 also comprises the energy storage energy supply circuit, described signal wire BUS
+Through this energy storage energy supply circuit to power devices.
4, bus interface circuit according to claim 1 is characterized in that described signal wire BUS
+Be connected to the second chip U2, one input port of equipment through the output terminal of the 3rd interface circuit BLOCK3, the 3rd chip U3 one delivery outlet of equipment is connected to signal wire BUS through the 4th interface circuit BLOCK4
+On.
5, bus interface circuit according to claim 4, it is characterized in that the described second chip U2 is the VD5027 chip, the 3rd chip U3 is the LM331 chip, and the host-host protocol of described bus interface circuit is 1100*[HIGH]+[HEAD]+8 bit address sign indicating number+4 bit data positions+[TAL]+500 microsecond time-delay+9 millisecond counters counting.
6, bus interface circuit according to claim 1 is characterized in that described signal wire BUS
+Be connected to four-core sheet U23 one input port of equipment through the output terminal of the 3rd interface circuit BLOCK3, this four-core sheet U23 one delivery outlet is connected to signal wire BUS through the 4th interface circuit BLOCK4
+On.
7, according to claim 1,2,3,4,5 or 6 described bus interface circuits, it is characterized in that described signal wire BUS
+For the polarity bus is arranged.
8, according to claim 1,2,3,4,5 or 6 described bus interface circuits, it is characterized in that described signal wire BUS
+Be nonpolarity bus.
9, bus interface circuit according to claim 8 is characterized in that described the 3rd interface circuit is provided with Yi Qiaodui, signal wire BUS
+With ground wire BUS
-Insert the 3rd interface circuit through this bridge heap.
10, bus interface circuit according to claim 1 is characterized in that also comprising a power lead to power devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03256071 CN2634530Y (en) | 2003-07-29 | 2003-07-29 | Bus interface circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03256071 CN2634530Y (en) | 2003-07-29 | 2003-07-29 | Bus interface circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2634530Y true CN2634530Y (en) | 2004-08-18 |
Family
ID=34295261
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 03256071 Expired - Fee Related CN2634530Y (en) | 2003-07-29 | 2003-07-29 | Bus interface circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2634530Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108920982A (en) * | 2015-10-30 | 2018-11-30 | 深圳国微技术有限公司 | A kind of anti-tamper shielded layer for safety chip |
-
2003
- 2003-07-29 CN CN 03256071 patent/CN2634530Y/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108920982A (en) * | 2015-10-30 | 2018-11-30 | 深圳国微技术有限公司 | A kind of anti-tamper shielded layer for safety chip |
| CN108985106A (en) * | 2015-10-30 | 2018-12-11 | 深圳国微技术有限公司 | A kind of anti-tamper shielded layer for safety chip |
| CN108985106B (en) * | 2015-10-30 | 2021-07-20 | 深圳国微技术有限公司 | Tamper-proof shielding layer for security chip |
| CN108920982B (en) * | 2015-10-30 | 2021-08-17 | 深圳国微技术有限公司 | Tamper-proof shielding layer for security chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN2862193Y (en) | Data gathering system | |
| CN205959200U (en) | A latch circuit for I2C bus data transmission | |
| CN107766200A (en) | A kind of I2C monitoring bus system and monitoring method | |
| CN107831702A (en) | A kind of synchronous serial signal acquisition and control device based on gigabit Ethernet | |
| CN213934874U (en) | RS485 serial bus communication equipment based on monitoring technology | |
| CN2634530Y (en) | Bus interface circuit | |
| CN1715956A (en) | Double collecting machine system and it double collecting method for double machine hot back-up | |
| CN209433225U (en) | Processing unit for train network input-output system | |
| CN202661873U (en) | Intelligent phone-based automobile diagnosing system | |
| CN103176435A (en) | Device and method of interface for achieving connection of distributed control system and measuring device | |
| CN213987495U (en) | Welding robot and data analysis processing device thereof | |
| CN1821989A (en) | Single bus two-way communication protocol revolving analyzer | |
| CN209627394U (en) | A kind of digital signal acquiring device and system | |
| CN203086503U (en) | FlexRay bus communication daughter card based on PCI interface | |
| CN216959896U (en) | Big data bus transmission device of track traffic roadbed thing networking | |
| CN2627744Y (en) | Data-transmission interface and serial bus interface equipment | |
| CN100401330C (en) | Synchronous signal telecommunication controlling system of vehicle bus | |
| CN201569170U (en) | Communication system of gas water heater with function of stagger joint and remedy | |
| CN205485457U (en) | Intelligent data acquisition system and device | |
| CN206096827U (en) | Industrial data collection system | |
| CN220292038U (en) | USB changes on-vehicle ethernet equipment | |
| CN219018837U (en) | Photoelectric port automatic identification device and Ethernet equipment | |
| CN2874646Y (en) | Digital bus interface device for warning system | |
| CN215119304U (en) | Multi-interface gateway based on DTU | |
| CN218159296U (en) | Ad-hoc network type communication optimization circuit capable of rapidly identifying addresses by RS485 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |