CN2613023Y - Image zooming facotr generating circuit of display with error compensation - Google Patents

Image zooming facotr generating circuit of display with error compensation Download PDF

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Publication number
CN2613023Y
CN2613023Y CN 03216941 CN03216941U CN2613023Y CN 2613023 Y CN2613023 Y CN 2613023Y CN 03216941 CN03216941 CN 03216941 CN 03216941 U CN03216941 U CN 03216941U CN 2613023 Y CN2613023 Y CN 2613023Y
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China
Prior art keywords
output
display
circuit
comparer
error compensation
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Expired - Fee Related
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CN 03216941
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Chinese (zh)
Inventor
何云鹏
战嘉瑾
丁勇
刘志恒
陈永强
缪建兵
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Hisense Group Co Ltd
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Hisense Group Co Ltd
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Priority to CN 03216941 priority Critical patent/CN2613023Y/en
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Publication of CN2613023Y publication Critical patent/CN2613023Y/en
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Abstract

An image zooming coefficient generating circuit with an error compensation for a display belongs to the display art, comprising a field zooming coefficient generating and a row zooming coefficient generating circuit, wherein two circuit both comprise a 1 add counter taking 64 as a period, a comparer which is compared with a constant 32 is connected with an output end of the counter, if equal, 1 is output, otherwise 0 is output, the output end of the comparer is connected with a controlling end of a selector, two input signals of the selector are two zooming step 1 and step2, wherein step2 has error compensation to the step 1, when the comparer outputs 1, the selector outputs step 2, at other time step 1 is output. The connection on the output end of the selector acts as a 8 bitter adder of an addend, which connects a starter of a compensated image zooming efficient with the output end of the adder. The circuit has simple structure and low error, can make the image quality of the display apparently improved, which can be widely used in an image zooming coefficient generating of each kind of display.

Description

The image zoom coefficient of the band error compensation of display produces circuit
Technical field
The utility model belongs to the display technology field, produces the improvement of circuit more specifically to the band error compensation image zoom coefficient of display.
Background technology
In display image convergent-divergent circuit,, bring error owing to round to zoom factor is approximate.At this moment as not adding compensation, accumulated error can be very big, so that display can't correctly show.Again because the computing of mixed decimal is difficult in circuit realize that circuit in the past is very complicated that expense is big, and error is also bigger, makes the image quality decrease of display.
The purpose of this utility model just is to overcome above-mentioned shortcoming and defect, provide a kind of simple in structure, and error is less, the picture quality of display be improved significantly the image zoom coefficient of band error compensation of display produce circuit.
Summary of the invention
The utility model comprises that a zoom factor produces circuit and the row zoom factor produces circuit.It is 1 counter that adds in cycle with 64 that above-mentioned two kinds of circuit include one.What be connected with the output terminal of counter is the comparer of comparing with a constant 32, equates output 1, otherwise exports 0.The output terminal of comparer is connected to the control end of a selector switch, and two input signals of this selector switch are two convergent-divergent step-length step1 and step2, and wherein step2 carries out error compensation to step1.When comparer exports 1, selector switch output step2, all the other the time output step1.The output terminal of selector switch connects 8 totalizers as summand, is connected the trigger of output through the image zoom coefficient of compensation with the output terminal of totalizer.
The utility model adopts the fixed cycle (64 clock period) to compensate.With the input picture display format is that 800 * 600 to be transformed into 1024 * 768 be example.If distance is 64 between the figure neighbor of source.Then the step-length when convergent-divergent is: horizontal direction is 799/1023*64=49.9863, and vertical direction is: 599/767*64=49.9817. is because the computing of mixed decimal is difficult to realization in circuit, and the expense of circuit is big.So getting its approximate value 50, we are step1.The error part every 64 clock period compensation once.This compensation is extremely important, especially some form is transformed into 1024 * 768 as 640 * 400, and the step-length of field direction is: 399/767*64=33.293. is at this moment as uncompensation, and accumulated error can be very big, so that can't correctly show.Step2 by way of compensation can be drawn by following formula:
hxtep 2 = hstep 1 + ( ori _ actoux - 1 ) * 64 - ( des _ actpix - 1 ) * hstep 1 des _ actpix
vstep 2 = vstep 1 + ( ori _ actlin - 1 ) * 64 - ( des _ actlin - 1 ) * vstep 1 des _ actlin . . . . ( 1 )
Wherein, hstep1, hstep2 are the convergent-divergent step-lengths of horizontal direction, and vstep1, vstep2 are the convergent-divergent step-lengths of vertical direction.Ori_actpix, ori_actlin are respectively the valid pixel number and the line numbers of source images.Des_actpix, des_actlin are the valid pixel number and the line numbers of target image.Step1 and step2 are calculated by following formula by MCU.
Task of the present utility model comes to this and finishes.
It is a kind of simple in structure that the utility model provides, and error is little, the picture quality of display be improved significantly the image zoom coefficient of band error compensation of display produce circuit.It can be widely used in the image zoom coefficient generation of various displays.
Description of drawings
Fig. 1 produces the block scheme of circuit for the field zoom factor of band error compensation.
Fig. 2 produces the block scheme of circuit for the capable zoom factor of band error compensation.
Fig. 3 is the circuit theory diagrams of Fig. 1.
Embodiment
The image zoom coefficient of the band error compensation of 1. 1 kinds of displays of embodiment produces circuit, shown in Fig. 1~3.Fig. 1 is the zoom factor generation circuit of field direction, comprises that one is 1 counter that adds in cycle with 64, one 8 coefficient totalizer, a comparer, two MUX and trigger.The vstep1 of input, vstep2 is calculated by MCU.D_vde_l1 signal first clock period when the output map image field effectively begins is 1, and all the other times are 0.D_de_l1 is 1 in first clock period that the output image each row of data effectively begins, and all the other times are zero.Promptly when beginning, every row adds 1, zero clearing when every beginning.When counter was added to 64, upset was 0 automatically.Counter is added to 32 o'clock output high level, selects vstep2, is then to select the summand of vstep1 as the coefficient totalizer at 0 o'clock.The 0th to the 5th of the coefficient v_coef of output is as another summand of next cycle.And first clock period that effectively begins on the scene is to the zero clearing of coefficient totalizer.After the coefficient vcoef[7:0 of 8 of trigger outputs].
Fig. 2 is that the zoom factor of line direction produces circuit, produces identical with the field zoom factor.With 64 is that the counter in cycle adds 1 at each rising edge clock, zero clearing when D_de_l1 is 1.Is that the counter result selected hstep2 at 32 o'clock in the centre in cycle, all the other the time select the summand of hstep1 as the coefficient totalizer.The row coefficient totalizer low six as another summand.Its result zero clearing when every when beginning row (D_de_l1 equals 1).Export 8 hcoef[7:0 at last].
Embodiment 1 circuit structure is simple, and error is little, can make display picture quality be improved significantly.It can be widely used in the image zoom coefficient generation of various displays.

Claims (1)

1. the image zoom coefficient of the band error compensation of a display produces circuit, it comprises that a zoom factor produces circuit and the row zoom factor produces circuit, it is characterized in that it is 1 counter that adds in cycle with 64 that above-mentioned two kinds of circuit include one, what be connected with the output terminal of counter is the comparer of comparing with a constant 32, equate output 1, otherwise export 0, the output terminal of comparer is connected to the control end of a selector switch, two input signals of this selector switch are two convergent-divergent step-length step1 and step2, wherein step2 carries out error compensation to step1, when comparer exports 1, selector switch output step2, all the other time output step1, the output terminal of selector switch connects 8 totalizers as summand, is connected the trigger of the image zoom coefficient of output through compensating with the output terminal of totalizer.
CN 03216941 2003-04-29 2003-04-29 Image zooming facotr generating circuit of display with error compensation Expired - Fee Related CN2613023Y (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 03216941 CN2613023Y (en) 2003-04-29 2003-04-29 Image zooming facotr generating circuit of display with error compensation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 03216941 CN2613023Y (en) 2003-04-29 2003-04-29 Image zooming facotr generating circuit of display with error compensation

Publications (1)

Publication Number Publication Date
CN2613023Y true CN2613023Y (en) 2004-04-21

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CN 03216941 Expired - Fee Related CN2613023Y (en) 2003-04-29 2003-04-29 Image zooming facotr generating circuit of display with error compensation

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CN (1) CN2613023Y (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103607195A (en) * 2013-10-17 2014-02-26 陕西万达信息工程有限公司 Two-number-adding timing sequence unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103607195A (en) * 2013-10-17 2014-02-26 陕西万达信息工程有限公司 Two-number-adding timing sequence unit

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Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
EE01 Entry into force of recordation of patent licensing contract

Assignee: Qingdao Hisense Xinxin Technology Co., Ltd.

Assignor: Hisense Group Co., Ltd.

Contract fulfillment period: 2008.10.12 to 2013.10.11

Contract record no.: 2008370000073

Denomination of utility model: Image zooming facotr generating circuit of display with error compensation

Granted publication date: 20040421

License type: Exclusive license

Record date: 20081030

LIC Patent licence contract for exploitation submitted for record

Free format text: EXCLUSIVE LICENSE; TIME LIMIT OF IMPLEMENTING CONTACT: 2008.10.12 TO 2013.10.11; CHANGE OF CONTRACT

Name of requester: QINGDAO HAIXIN XINXIN SCIENCE CO., LTD.

Effective date: 20081030

C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20040421