CN103607195A - Two-number-adding timing sequence unit - Google Patents
Two-number-adding timing sequence unit Download PDFInfo
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- CN103607195A CN103607195A CN201310488790.8A CN201310488790A CN103607195A CN 103607195 A CN103607195 A CN 103607195A CN 201310488790 A CN201310488790 A CN 201310488790A CN 103607195 A CN103607195 A CN 103607195A
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Abstract
The invention discloses a two-number-adding timing sequence unit which is applicable to the realization of the adding of two numbers and the accumulation of partial products of a multiplier. The two-number-adding timing sequence unit includes a full adder, a D flip-flop and two multiplexers. The full-adder is provided with two internal input ends and one internal output end, and one input end c-1 and an output end c are led out from the full-adder; the D flip-flop is provided with a data input end, a clock input end (Clock), a reset end Reset and an output end (Q); a first multiplexer is provided with one internal output end, and two input ends (a and b), and one selection end Sab are led out from the first multiplexer; a second multiplexer is provided with one internal input end and one internal output end, and one input end SI and one selection end SE are led out from the second multiplexer; the two internal input ends of the full-adder are respectively connected with the internal output end of the first multiplexer and the output end of the D flip-flop; and the internal input end of the second multiplexer is connected with the internal output end of the full-adder, and the internal output end of the second multiplexer is connected with the data input end of the D flip-flop.
Description
Technical field
The invention belongs to integrated circuit (IC) design field, be specifically related to a kind of two addend timing units.
Background technology
Conventionally in integrated circuit (IC) design, multiplier and adder are two modules that work alone, and they have respectively hardware spending separately.Hardware spending is in circuit design, to need one of key factor of considering, but in existing document, the scheme that main flow design adopts is respectively multiplier and adder to be optimized, and this reduction for hardware circuit expense is limited.Thereby how multiplier and adder are combined to design, effectively reducing hardware spending, is a popular direction of integrated circuit (IC) design.
Summary of the invention
The object of the invention is to address the above problem, a kind of two addend timing units that two numbers are added and multiplier partial product is cumulative that are applicable to are provided, this timing unit can reduce the hardware spending of integrated circuit.
In order to achieve the above object, the present invention is achieved by the following technical solutions: comprise full adder, d type flip flop, two MUX; Full adder has two inner inputs and an internal output terminal, leads to an input c
-1with an output c; D type flip flop has data input pin, input end of clock Clock, reset terminal Reset, output Q; The first MUX has an internal output terminal, leads to two input a, b and a selecting side S
ab; The second MUX has an inner input and an internal output terminal, leads to an input SI and a selecting side SE.
Two inner inputs of described full adder are connected with the internal output terminal of the first MUX and the output Q of d type flip flop respectively; The inside input of the second MUX and the internal output terminal of full adder are connected, and the internal output terminal of the second MUX is connected with the data input pin of d type flip flop.
Two described MUX are No. two selectors.
Compared with prior art, the present invention has following beneficial effect:
When the first any road of MUX gating, during second its external input terminals of MUX gating SI, this unit is for realizing the accumulation function of multiplier partial product; When the first MUX is not being distinguished gating two input a, b in the same time, during second its inner input of MUX gating, the function that this unit is added for realizing two numbers.The present invention is by increasing some logical circuits, logic element carried out multiplexing, can realize that two numbers are added and the cumulative function of partial product of multiplier, thereby reduce the hardware spending of integrated circuit.
Accompanying drawing explanation
Fig. 1 is logic circuit structure figure of the present invention;
Fig. 2 is the logic circuit structure figure of the compound full adder timing unit of the present invention;
Fig. 3 is the circuit structure diagram of the compound full adder timing unit of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the present invention is further detailed explanation:
Referring to Fig. 1, the present invention includes full adder FA, d type flip flop, two MUX; Full adder has two inner inputs and an internal output terminal, leads to an input c
-1with an output c; D type flip flop has data input pin, input end of clock Clock, reset terminal Reset, output Q; The first MUX has an internal output terminal, leads to two input a, b and a selecting side S
ab; The second MUX has an inner input and an internal output terminal, leads to an input SI and a selecting side SE.Two inner inputs of full adder are connected with the internal output terminal of the first MUX and the output Q of d type flip flop respectively; The inside input of the second MUX and the internal output terminal of full adder are connected, and the internal output terminal of the second MUX is connected with the data input pin of d type flip flop.
Principle of the present invention and the course of work:
Work as S
ab=0 or during 1, SE=1, the first any road of MUX gating, second its external input terminals of MUX gating SI, this unit is for realizing the accumulation function of multiplier partial product.Work as S
abduring=1, SE=0, the first MUX is at this moment Strobe input a, its inner input of the second MUX gating; Work as S
abduring=0, SE=0, the first MUX is in this moment Strobe input b, its inner input of the second MUX gating, the function that this unit is added for realizing two numbers.
Referring to Fig. 2, the first MUX and full adder have formed a compound full adder timing unit, realize the addition function of two numbers.Work as S
ab=1 o'clock, this recombiner unit can be realized the addition of Q and a; Work as S
ab=0 o'clock, this recombiner unit can be realized the addition of Q and b.C
-1for the carry output signals of previous stage, c is carry output signals at the corresponding levels, and s is at the corresponding levels and signal.
With reference to Fig. 3, compound full adder timing unit is comprised of basic logical gate, realization be the logic function of recombiner unit in Fig. 2.
Claims (2)
1. two addend timing units, is characterized in that: comprise full adder (FA), d type flip flop, two MUX; Full adder has two inner inputs and an internal output terminal, leads to an input c
-1with an output c; D type flip flop has data input pin, input end of clock Clock, reset terminal Reset, output Q; The first MUX has an internal output terminal, leads to two input a, b and a selecting side S
ab; The second MUX has an inner input and an internal output terminal, leads to an input SI and a selecting side SE;
Two inner inputs of described full adder are connected with the internal output terminal of the first MUX and the output Q of d type flip flop respectively; The inside input of the second MUX and the internal output terminal of full adder are connected, and the internal output terminal of the second MUX is connected with the data input pin of d type flip flop.
2. a kind of two addend timing units according to claim 1, is characterized in that: two described MUX are No. two selectors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310488790.8A CN103607195A (en) | 2013-10-17 | 2013-10-17 | Two-number-adding timing sequence unit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310488790.8A CN103607195A (en) | 2013-10-17 | 2013-10-17 | Two-number-adding timing sequence unit |
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| CN103607195A true CN103607195A (en) | 2014-02-26 |
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| CN201310488790.8A Pending CN103607195A (en) | 2013-10-17 | 2013-10-17 | Two-number-adding timing sequence unit |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2613023Y (en) * | 2003-04-29 | 2004-04-21 | 海信集团有限公司 | Image zooming facotr generating circuit of display with error compensation |
| US7146487B2 (en) * | 1998-01-28 | 2006-12-05 | Altera Corporation | Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution |
| US7196648B1 (en) * | 2005-12-23 | 2007-03-27 | Cirrus Logic, Inc. | Non-integer decimation using cascaded intergrator-comb filter |
| CN101807913A (en) * | 2010-03-26 | 2010-08-18 | 华为技术有限公司 | Enabling signal generating method, device and equipment of low-speed clock |
-
2013
- 2013-10-17 CN CN201310488790.8A patent/CN103607195A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7146487B2 (en) * | 1998-01-28 | 2006-12-05 | Altera Corporation | Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution |
| CN2613023Y (en) * | 2003-04-29 | 2004-04-21 | 海信集团有限公司 | Image zooming facotr generating circuit of display with error compensation |
| US7196648B1 (en) * | 2005-12-23 | 2007-03-27 | Cirrus Logic, Inc. | Non-integer decimation using cascaded intergrator-comb filter |
| CN101807913A (en) * | 2010-03-26 | 2010-08-18 | 华为技术有限公司 | Enabling signal generating method, device and equipment of low-speed clock |
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Application publication date: 20140226 |