CN2570981Y - Upside-down mounting type chip packaging arrangement - Google Patents
Upside-down mounting type chip packaging arrangement Download PDFInfo
- Publication number
- CN2570981Y CN2570981Y CN 02254295 CN02254295U CN2570981Y CN 2570981 Y CN2570981 Y CN 2570981Y CN 02254295 CN02254295 CN 02254295 CN 02254295 U CN02254295 U CN 02254295U CN 2570981 Y CN2570981 Y CN 2570981Y
- Authority
- CN
- China
- Prior art keywords
- chip
- pellicle
- packaging structure
- flip
- carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Wire Bonding (AREA)
Abstract
The utility model relates to an upside-down sheet type chip packaging structure, which is at least provided with a load bearing device, a chip, a plurality of convex blocks and a protective rubber film, wherein, the load bearing device is provided with a top surface and a plurality of convex block pads, and the convex block pads are matched on the top surface of the load bearing device. The chip is provided with a working surface and a corresponding back surface and a plurality of welding pads matched on the working surface of the chip. In addition, the convex blocks are respectively matched with one of the welding pads and one of the convex blocks corresponding to the welding pads, and the protective rubber film is matched on the back surface of the chip to avoid the outside damage to the chip.
Description
Technical field
The utility model relates to a kind of flip-chip type chip-packaging structure, and be particularly related to a kind of flip-chip type chip-packaging structure with pellicle, wherein pellicle is disposed at the back side of chip, the back side in order to the prevention chip is subjected to damage of external force, provides preferable heat-conducting effect to chip simultaneously.
Background technology
Flip-chip joining technique (Flip Chip Interconnect Technology, be called for short FC) mainly utilize the mode of face array (area array), a plurality of weld pads (die pad) are disposed at the first type surface (active surface) of chip (die), and on each weld pad, form projection (bump), again chip is turned over (flip) afterwards, utilize on the chip projection respectively correspondence be connected to contact (contact) on the carrier (carrier), make chip can be electrically connected to carrier, be electrically connected to extraneous electronic installation again via the internal wiring of carrier via projection.It should be noted that, because the flip-chip joining technique is applicable to the chip-packaging structure of high pin number (High Pin Count), and have the Chip Packaging of dwindling area simultaneously and shorten advantages such as signal transmission path, make the flip-chip joining technique be widely used in the Chip Packaging field at present, the chip-packaging structure of common application flip-chip joining technique for example has flip-chip sphere grid array type (Flip Chip/Ball Grid Array, FC/BGA) and flip-chip Pga type (Flip Chip/Pin Grid Array, the chip-packaging structure of kenel such as FC/PGA).
Please refer to Fig. 1, it illustrates the generalized section of first kind of common flip-chip sphere grid array cake core encapsulating structure.Chip-packaging structure 100 mainly comprises a chip 110, a plurality of projection 120 and a carrier 130 etc.Wherein, chip 110 has a working surface (active surface) 112 and a corresponding back side 114, the one side with work package (activedevice) of the working surface 112 general reference chips 110 of its chips 110, and chip 110 also has a plurality of weld pads 116, it is disposed at the working surface 112 of chip 110, in order to export as the signal of chip 110 into media.In addition, carrier 130 for example is one to have the substrate (substrate) of built-in circuit, and has an end face 132 and a corresponding bottom surface 134, and carrier 130 also has a plurality of bump pads (bump pad) 136, and its position corresponds respectively to the position of these weld pads 116.In addition, 120 of these projections dispose respectively between one of one of these weld pads 116 and pairing these bump pads 136 thereof, in order to electrically connect one of one of these weld pads 116 and pairing these bump pads 136 thereof respectively.
Please equally with reference to figure 1; primer (underfill) 140 is filled in the space that the end face 132 of the working surface 112 of chip 110 and carrier 130 is constituted; in order to the part that exposes of protection weld pad 116, projection 120 and bump pads 136, and produce simultaneously the difference of thermal strain (thermal strain) between buffer chip 110 and the carrier 130 because of being heated.In addition, carrier 130 also has a plurality of solder ball pads (ball pad) 138, and it is disposed at the bottom surface 134 of carrier 130 equally in the mode of face array, and soldered ball (ball) 150 is disposed at respectively on each solder ball pad 138.Therefore, the weld pad 116 of chip 110 can be via projection 120, and electrically reach the bump pads 136 that mechanicalness is connected to carrier 130, (routing) solder ball pad 138 to the bottom surface 134 of carrier 130 again winds the line downwards via the internal wiring of carrier 130, utilize the soldered ball 150 on the solder ball pad 138 at last, and electrically reach the electronic installation that mechanicalness is connected to next level (next level), for example a printed circuit board (PCB) (PCB).
Please also refer to Fig. 1, Fig. 2, wherein Fig. 2 illustrates the generalized section of second kind of common flip-chip sphere grid array cake core encapsulating structure.At first as shown in Figure 1, chip-packaging structure 100 is that primer 140 is filled in the space that the end face 132 of the working surface 112 of chip 110 and carrier 130 is constituted, in order to the part that exposes of protection weld pad 116, projection 120 and bump pads 136.In addition; though the primer 140 of the chip-packaging structure 100 of Fig. 1 can be protected the part that exposes of weld pad 116, projection 120 and bump pads 136; but but can't protect the back side 114 of chip 110 effectively; make the back side 114 of chip 110 be subjected to external force easily and destroy, thereby stay trickle slight crack (not illustrating) at the back side 114 of chip 110.It should be noted that applying high heat repeatedly circularly after chip 110, the size of slight crack and the degree of depth are inevitable little by little to be increased, and causes the internal circuit of chip 110 will be subjected to the influence of slight crack at last and lose its original function.
Then as shown in Figure 2,102 of chip-packaging structures are that the mode with model (molding) forms in sealing (molding compound) 142 on chip 110 and the carrier 130, and sealing 142 is filled in the space that the end face 132 of the working surface 112 of chip 110 and carrier 130 is constituted, and coat the lateral margin and the back side 114 to chip 110.Therefore, the surface of chip 110 all can be subjected to (comprising the back side 114) protection of sealing 142.It should be noted that because the coefficient of heat conduction of the material of sealing 142 (Coefficient of Thermal Expansion, CTE) relatively poor, so the heat energy that chip 110 is produced when running is not easy to dissipate to via sealing 142 external world.
Summary of the invention
In view of this, the purpose of this utility model is to provide a kind of flip-chip type chip-packaging structure, the back side in order to the prevention chip is subjected to damage of external force, provide preferable heat-conducting effect to chip simultaneously, so can promote the electric usefulness of this chip-packaging structure, and the useful life that can improve this chip-packaging structure.
Based on above-mentioned purpose, the utility model proposes a kind of flip-chip type chip-packaging structure, it has a carrier, a chip, a plurality of projection, a pellicle (protection film) and a primer at least.Wherein, carrier has an end face and a plurality of bump pads, and these bump pads are disposed at the end face of carrier.In addition, chip then has a working surface and a corresponding back side, and chip also has a plurality of weld pads, and it is disposed at the working surface of chip.In addition, these projections then dispose respectively between one of one of these weld pads and pairing these bump pads thereof.And pellicle is disposed at the back side of chip, and primer then is filled in the space that end face constituted of the working surface and the carrier of chip.Material that it should be noted that pellicle is the material that elasticity is good, thermal endurance is good and thermal diffusivity is good.In addition, pellicle also can have a plurality of heat radiation particles, and it is doped within the pellicle.
Based on above-mentioned purpose of the present utility model, the utility model also proposes a kind of flip-chip type chip-packaging structure equally, and it has a carrier, a chip, a plurality of projection, a pellicle and a sealing at least.Wherein, carrier has an end face and a plurality of bump pads, and these bump pads are disposed at the end face of carrier.In addition, chip then has a working surface and a corresponding back side, and chip also has a plurality of weld pads, and it is disposed at the working surface of chip.In addition, these projections then dispose respectively between one of one of these weld pads and pairing these bump pads thereof.And pellicle is disposed at the back side of chip, and sealing then is filled in the space that end face constituted of the working surface and the carrier of chip, and the lateral margin of coating chip and pellicle, and exposes the one side away from chip of pellicle.Similarly, the material of pellicle is the material that elasticity is good, thermal endurance is good and thermal diffusivity is good.In addition, pellicle also can have a plurality of heat radiation particles, and it is doped within the pellicle.
For above-mentioned purpose of the present utility model, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Fig. 1 illustrates the generalized section of first kind of common flip-chip sphere grid array cake core encapsulating structure;
Fig. 2 illustrates the generalized section of second kind of common flip-chip sphere grid array cake core encapsulating structure;
Fig. 3 illustrates the generalized section of first kind of flip-chip type chip-packaging structure of preferred embodiment of the present utility model;
Fig. 4 illustrates the generalized section of second kind of flip-chip type chip-packaging structure of preferred embodiment of the present utility model; And
Fig. 5 A--5C illustrates a kind of manufacturing process flow chart with chip of pellicle of preferred embodiment of the present utility model.Label declaration
100,102: chip-packaging structure 110: chip
112: working surface 114: the back side
116: weld pad 120: projection
130: carrier 132: end face
134: bottom surface 136: bump pads
138: solder ball pad 140: primer
142: sealing 150: soldered ball
200,202: chip-packaging structure 210: chip
212: working surface 214: the back side
216: weld pad 218: pellicle
220: projection 230: carrier
232: end face 234: bottom surface
236: bump pads 238: solder ball pad
240: primer 242: sealing
250: soldered ball 300: wafer
300a: chip 301: flip-chip chip structure
302: working surface 304: the back side
306: weld pad 310: pellicle
320: projection
Embodiment
Please refer to Fig. 3, it illustrates the generalized section of first kind of flip-chip type chip-packaging structure of preferred embodiment of the present utility model.Chip-packaging structure 200 mainly comprises a chip 210, a plurality of projection 220 and a carrier 230 etc.Chip 210 has a working surface 212 and a corresponding back side 214, it should be noted that, the one side with work package of the working surface 212 general reference chips 210 of chip 210, and chip 210 also has a plurality of weld pads 216, its mode with the face array is disposed at the working surface 212 of chip 210, in order to export as the signal of chip 210 into media.In addition, carrier 230 for example is one to have the substrate of built-in circuit, and carrier 230 has an end face 232 and a corresponding bottom surface 234, and carrier 230 also has a plurality of bump pads 236, and its position corresponds respectively to the position of these weld pads 216.In addition, 220 of these projections dispose respectively between one of one of these weld pads 216 and pairing these bump pads 236 thereof, in order to electrically connect one of one of these weld pads 216 and pairing these bump pads 236 thereof respectively.
Please equally with reference to figure 3; primer 240 is filled in the space that the end face 232 of the working surface 212 of chip 210 and carrier 230 is constituted; in order to the part that exposes of protection weld pad 216, projection 220 and bump pads 236, and produce the difference of thermal strain between while buffer chip 210 and the carrier 230 because of being heated.In addition, when chip-packaging structure 200 is applied to the chip-packaging structure of flip-chip sphere grid array type (FC/BGA), carrier 230 can have a plurality of solder ball pads 238, it is disposed at the bottom surface 234 of carrier 230 equally in the mode of face array, and soldered ball 250 is disposed at respectively on each solder ball pad 238.Therefore, the weld pad 216 of chip 210 can be via projection 220, and electrically reach the bump pads 236 that mechanicalness is connected to carrier 230, wind the line downwards via the internal wiring of carrier 230 again to the solder ball pad 238 of the bottom surface 234 of carrier 230, utilize the soldered ball 250 on the solder ball pad 238 at last, and electrically reach the electronic installation that mechanicalness is connected to next level (next level), for example a printed circuit board (PCB) (PCB).In addition, chip-packaging structure 200 also can be applicable to the chip-packaging structure of flip-chip Pga type (FC/PGA), or other flip-chip type chip-packaging structure.Carrier 230 that it should be noted that chip-packaging structure 200 also can be the bearing structure of other kenel except being one to have the substrate of built-in circuit, but for example lead frame of a carries chips 210 (lead-frame) or flexible circuit board etc.
Please equally with reference to figure 3, do not destroy for the back side 214 that will prevent chip 210 can not be subjected to external force, provide preferable heat-conducting effect to chip 210 simultaneously, chip-packaging structure 200 will also have a pellicle 218, and it is disposed at the back side 214 of chip 210.It should be noted that, the material of pellicle 218 must have elasticity and toughness, so when extraneous pressure puts on the pellicle 218, pellicle 218 with elasticity and toughness can correspondingly immediately produce deformation, and the pressure in the external world is dispersed on the back side 214 of chip 210, stay slight crack in order to prevent extraneous excessive pressure at the back side 214 of chip 210.Therefore, the back side 214 of chip 210 will not be subject to extraneous pressure and produce slight crack, applying high heat repeatedly circularly after chip 210, the back side 214 of chip 210 will no longer have slight crack in order to increase its size and the degree of depth, so the internal circuit of chip 210 will can not be subjected to the influence of slight crack and lose its original function, so can improve the useful life of chip-packaging structure 200.
Please equally with reference to figure 3, during the manufacturing process of chip-packaging structure 200 and subsequent group process of assembling, pellicle 218 very likely needs to be warming up to more than 200 degree Celsius, so the material of pellicle 218 must correspondence have resistant to elevated temperatures characteristic, in order to avoid pellicle 218, make itself structure that phenomenons such as aging (oxidation) or embrittlement take place after too high heat treatment.In addition, for good heat-conducting effect and chip 210 is provided, the material of pellicle 218 then can have good heat dissipation characteristics, make the partial heat energy that chip 210 time is produced in running, can dissipate to the external world via pellicle 218, thereby effectively promote the electric usefulness of chip-packaging structure 200.
Please equally with reference to figure 3, (Poly-Imide PI) has better elastic, toughness, thermal endurance and thermal diffusivity, so can select the material of polyimide resin as pellicle 218 owing to polyimide resin.In addition, except the material of selecting to have preferable heat dissipation characteristics is used as the material of pellicle 218, in preferred embodiment of the present utility model, also can be within pellicle 218 with many heat radiation particles (particle) dopant profiles, in order to the heat dissipation characteristics of this body structure of promoting pellicle 218, and materials of these heat radiation particles for example have silicon dioxide (SiO2), aluminium oxide (Al2O3), copper and the good material of other thermal diffusivity.
Please also refer to Fig. 3, Fig. 4, wherein Fig. 4 illustrates the generalized section of second kind of flip-chip type chip-packaging structure of preferred embodiment of the present utility model.Chip-packaging structure 200 and chip-packaging structure 202 structurally are close to identical, so please refer to chip-packaging structure 200 and the related description thereof of Fig. 3, in this no longer giving unnecessary details, hereinafter only are illustrated at both not existing together more.At first, the primer 240 of the chip-packaging structure 200 of Fig. 3 is filled in the space that the end face 232 of the working surface 212 of chip 210 and carrier 230 is constituted, in addition, the sealing 242 of the chip-packaging structure 202 of Fig. 4 is except the space that the end face 232 of the working surface 212 that is filled in chip 210 and carrier 230 is constituted, the lateral margin of coating chip 210 and pellicle 218 also, and expose the one side away from chip 210 of pellicle 218, in order to increase the area of dissipation of pellicle 218, this is maximum not existing together between chip-packaging structure 200 and the chip-packaging structure 202.In addition, also can utilize the one side away from chip 210 of pellicle 218 directly to contact extraneous radiator (not illustrating), and then promote pellicle 218 its radiating efficiencys for chip 210.
Preferred embodiment of the present utility model also proposes a kind of manufacturing process with chip of pellicle, and please in regular turn with reference to figure 5A--5C, it illustrates a kind of manufacturing process flow chart with chip of pellicle of preferred embodiment of the present utility model.At first shown in Fig. 5 A, one wafer (wafer) 300 is provided, it has a working surface 302 and a corresponding back side 304, wherein the working surface 302 of wafer 300 has many group integrated circuit (Integration Circuit, IC) (do not illustrate), then shown in Fig. 5 B, form the back side 304 of a pellicle 310 in wafer 300, the method that wherein forms pellicle 310 can adopt rubbing method (coating) of winding applying method (film taping), roll extrusion rubbing method (roller coating), method of spin coating (spin coating) or other kind etc.Moreover shown in Fig. 5 C, distributed areas according to each group integrated circuit (IC) come cut crystal 300 to become a plurality of chip 300a, make pellicle 310 also correspondence cut into several parts, and keep somewhere respectively, so can make the back side 304 of every chips 300a all have pellicle 310 in the back side 304 of these chips 300a.
Please be equally with reference to figure 5A--5C, shown in Fig. 5 C, in order to make projection 320 on the weld pad 306 of the working surface 302 of chip 300a, can be shown in Fig. 5 A, make projection 320 in advance on weld pad 306 at the working surface 302 of wafer 300, or shown in Fig. 5 B, forming pellicle 310 after the back side 304 of wafer 300, the beginning is made projection 320 on the weld pad 306 at the working surface 302 of wafer 300.In any case it is right, all can obtain same flip-chip chip structure 301 at last, it comprises chip 300a, protection glue-line 310 and projection 306 etc. at least, wherein pellicle 310 is disposed at the back side 304 of chip 300a, and projection 320 then is disposed at the weld pad 306 on the working surface 302 of chip 300a respectively.
In sum, flip-chip type chip-packaging structure of the present utility model is additionally to set up one deck pellicle at the back side of its chip, wherein this pellicle can have better elastic and toughness, the back side in order to the prevention chip is subjected to damage of external force, and this pellicle also can have good thermal endurance, in order to tolerating the high hot of the extraneous pellicle that puts on, and this pellicle still can have good thermal diffusivity, in order to provide preferable heat-conducting effect to chip.Therefore, flip-chip type chip-packaging structure of the present utility model can additionally be set up a pellicle by the back side at chip, the back side in order to the prevention chip is subjected to damage of external force, provide preferable heat-conducting effect to chip simultaneously, so can promote the electric usefulness of this chip-packaging structure, the useful life that also can improve this chip-packaging structure.
Though the utility model with preferred embodiment openly as above; so it is not to be used to limit the utility model; any those of ordinary skill in the art; in not breaking away from spirit and scope of the present utility model; can do some equivalences and change and change, therefore protection range of the present utility model is as the criterion with claim.
Claims (10)
1, a kind of flip-chip type chip-packaging structure is characterized in that, comprises at least:
One carrier has an end face and several bump pads, and wherein these bump pads are disposed at this end face;
One chip has a working surface and a corresponding back side, and this chip also has several weld pads, and wherein these weld pads are disposed at this working surface;
Several projections dispose respectively between one of one of these weld pads and pairing these bump pads thereof; And
One pellicle is disposed at this back side of this chip.
2, flip-chip type chip-packaging structure as claimed in claim 1 is characterized in that, also comprises a primer, and it is filled in this working surface of this chip and the space that this end face constituted of this carrier.
3, flip-chip type chip-packaging structure as claimed in claim 1, it is characterized in that, also comprise a sealing, it is filled in this working surface of this chip and the space that this end face constituted of this carrier, and coat the lateral margin of this chip and this pellicle, and expose the one side away from this chip of this pellicle.
4, flip-chip type chip-packaging structure as claimed in claim 1 is characterized in that, this carrier comprises a substrate.
5, flip-chip type chip-packaging structure as claimed in claim 1 is characterized in that, the material of this pellicle comprises the rubber-like material.
6, flip-chip type chip-packaging structure as claimed in claim 1 is characterized in that, the material of this pellicle comprises having stable on heating material.
7, flip-chip type chip-packaging structure as claimed in claim 1 is characterized in that, the material of this pellicle comprises the material with thermal diffusivity.
8, flip-chip type chip-packaging structure as claimed in claim 1 is characterized in that, the material of this pellicle comprises polyimide resin.
9, flip-chip type chip-packaging structure as claimed in claim 1 is characterized in that, this pellicle also has several heat radiation particles, and it is doped within this pellicle.
10, flip-chip type chip-packaging structure as claimed in claim 9 is characterized in that, materials of these heat radiation particles are selected from by silicon dioxide, aluminium oxide and copper is formed a kind of material in the group.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02254295 CN2570981Y (en) | 2002-09-19 | 2002-09-19 | Upside-down mounting type chip packaging arrangement |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02254295 CN2570981Y (en) | 2002-09-19 | 2002-09-19 | Upside-down mounting type chip packaging arrangement |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2570981Y true CN2570981Y (en) | 2003-09-03 |
Family
ID=33723179
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02254295 Expired - Lifetime CN2570981Y (en) | 2002-09-19 | 2002-09-19 | Upside-down mounting type chip packaging arrangement |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2570981Y (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100390983C (en) * | 2006-03-30 | 2008-05-28 | 威盛电子股份有限公司 | Chip packing-body |
| CN100463130C (en) * | 2004-05-20 | 2009-02-18 | 威盛电子股份有限公司 | Crystal-cladded package preparing process |
| CN103594387A (en) * | 2012-08-16 | 2014-02-19 | 英飞凌科技股份有限公司 | Pad sidewall spacer and method of making pad sidewall spacer |
| CN104835745A (en) * | 2014-02-07 | 2015-08-12 | 阿尔特拉公司 | Methods for packaging integrated circuits |
-
2002
- 2002-09-19 CN CN 02254295 patent/CN2570981Y/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100463130C (en) * | 2004-05-20 | 2009-02-18 | 威盛电子股份有限公司 | Crystal-cladded package preparing process |
| CN100390983C (en) * | 2006-03-30 | 2008-05-28 | 威盛电子股份有限公司 | Chip packing-body |
| CN103594387A (en) * | 2012-08-16 | 2014-02-19 | 英飞凌科技股份有限公司 | Pad sidewall spacer and method of making pad sidewall spacer |
| CN104835745A (en) * | 2014-02-07 | 2015-08-12 | 阿尔特拉公司 | Methods for packaging integrated circuits |
| US9748197B2 (en) | 2014-02-07 | 2017-08-29 | Altera Corporation | Methods for packaging integrated circuits |
| CN104835745B (en) * | 2014-02-07 | 2019-08-30 | 阿尔特拉公司 | The method for encapsulating integrated circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2815324B2 (en) | Chip carrier having a single encapsulant and method of forming | |
| CN1163962C (en) | Electronic package with compressible heat sink structure | |
| US7300822B2 (en) | Low warpage flip chip package solution-channel heat spreader | |
| US6661103B2 (en) | Apparatus for packaging flip chip bare die on printed circuit boards | |
| CN1160782C (en) | Semiconductor integrated circuit device | |
| CN1172368C (en) | Semiconductor device | |
| US8072057B2 (en) | Semiconductor device and method of fabrication | |
| US20100084761A1 (en) | Semiconductor device and fabrication method of the same | |
| US20050189646A1 (en) | Packaged die on PCB with heat sink encapsulant and methods | |
| KR20010031110A (en) | Method and construction for thermally enhancing a microelectronic pakage | |
| CN100539091C (en) | Chip package structure | |
| CN1870256A (en) | Automatic tab package connecting host device element | |
| US20080135990A1 (en) | Stress-improved flip-chip semiconductor device having half-etched leadframe | |
| TW200423337A (en) | Chip package structure | |
| CN1157790C (en) | Chip stack package structure | |
| KR19990006450A (en) | Chip package | |
| US7190082B2 (en) | Low stress flip-chip package for low-K silicon technology | |
| CN2570981Y (en) | Upside-down mounting type chip packaging arrangement | |
| JP3628058B2 (en) | Resin-sealed semiconductor device | |
| JPS63239826A (en) | Semiconductor device | |
| JP3688801B2 (en) | Semiconductor device, manufacturing method thereof and mounting method thereof | |
| US7601561B2 (en) | Heat-radiating tape carrier package and method for manufacturing the same | |
| CN1574343A (en) | Semiconductor module | |
| CN101308827A (en) | Cooling type semiconductor package | |
| KR20040034313A (en) | Semiconductor device and method of manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CX01 | Expiry of patent term |
Expiration termination date: 20120919 Granted publication date: 20030903 |