CN2540066Y - High frequency clock pulse generator - Google Patents
High frequency clock pulse generator Download PDFInfo
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- CN2540066Y CN2540066Y CN 02204400 CN02204400U CN2540066Y CN 2540066 Y CN2540066 Y CN 2540066Y CN 02204400 CN02204400 CN 02204400 CN 02204400 U CN02204400 U CN 02204400U CN 2540066 Y CN2540066 Y CN 2540066Y
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Abstract
The utility model relates to a high frequency clock pulse generator that comprises a same frequency clock pulse source for providing a plurality of base frequency signals of various phases; wherein, partial base frequency signals are used for choosing signals; a multiplied frequency circuit is also included and is coupled with the same frequency clock pulse source; the multiplied frequency circuit comprises at least a frequency multiplier level; wherein, each frequency multiplier level includes at least one frequency multiplier unit, and each frequency multiplier unit of the first level receives two base frequency signals as the input signal and a base single as a choosing signal; and the phase difference of the choosing signal is the average value of the phase difference of two input signals; the choosing signal is used for carrying out samplings of the two input signals to produce a clock pulse signal that is two times of the input signal which are output to the frequency units of frequency multiplier in the next level to as an input signal or a choosing signal of the frequency units, so as to produce an output signal which is 2n times of the first frequency, and n is the level number of the sampler.
Description
(1) technical field
The relevant a kind of high frequency time pulse generator of the utility model, the high frequency time pulse generator of especially relevant a kind of low power consumption.
(2) background technology
Clock pulse generator is applied in the circuit arrangement in various fields, needs in the circuit application of high frequency time pulse at some, and high frequency time pulse generator need provide the high frequency time pulse signal, works down in high frequency with drive circuit.
See also Fig. 1, it is the circuit block diagram of the high frequency time pulse generator of the utility model prior art, and (phase-locked loop) formed by a phase-locked loop.Allow the voltage controlled oscillator in the loop directly vibrate, to produce the output clock signal of high frequency in high frequency.This phase-locked loop is made up of phase detectors (phasedetector) 12, a charge pump (charge pump) 13, one loop filter 14, a voltage controlled oscillator (voltagecontrolled oscillator) 15 and one frequency eliminator 16.Voltage controlled oscillator 15 is set at and produces the N output clock signal 17 doubly that a frequency is an incoming frequency 11, and it is synchronous to be somebody's turn to do the phase place and the incoming frequency fi that export clock signal 17.Yet when the phase-locked loop directly vibrated in high frequency, voltage controlled oscillator 15 will consume great power, and the power of its consumption and its operating frequency square almost is the relation that is directly proportional.Therefore, when the operating frequency of voltage controlled oscillator 15 improved, the power that the phase-locked loop consumed almost presented the growth of square type.Therefore, this kind design is a kind of way of suitable consumed power.
See also Fig. 2, it is the circuit block diagram of the high frequency time pulse generator of the another kind of prior art of the utility model, is made up of a phase-locked loop (phase-locked loop) 25, one delay-locked loop (delayed lock loop) 26 and one logical circuit 27.It is the low frequency output clock signal 21 that utilizes phase-locked loop 25 to produce, and carries out phase delay through 26 pairs of this low frequency output of delay-locked loop clock signal 21 again, and produces the low frequency clock signal 23 of a plurality of tool outs of phase.The low frequency clock signal 23 of these a plurality of tool outs of phase is as the input of logical circuit 27, and clock signal 22 outputs of controlled clock signal 24 controls to produce high frequency.Compare with Fig. 1,, but have more a delay-locked loop 26, and need to produce again in addition a control clock signal 24 though the high frequency time pulse generator of Fig. 2 need not allow phase-locked loop 25 in high frequency work down.In addition, the relation of the low frequency clock signal 23 of this control clock signal 24 and these a plurality of tool outs of phase also quite is difficult to control as the relation between flexibility (skew), duty cycle (duty cycle), setting-up time (setup time), the retention time parameters such as (hold time).Therefore, it is comparatively complicated that the high frequency time pulse generator of Fig. 2 can become on circuit design, the also difficult control of the relativeness between each clock signal in the delay-locked loop 26 simultaneously.
(3) utility model content
Main purpose of the present utility model provides the little and simple high frequency time pulse generator of circuit design of a kind of power consumption.
For achieving the above object, high frequency time pulse generator of the present utility model is characterized in, comprising: time clock source frequently together, be used to provide several fundamental frequency signals of out of phase, and wherein partly these several fundamental frequency signals are with the signal that elects; An and frequency multiplier circuit, be coupled to this with the frequency time clock source, it is made up of the frequency multiplier of one-level at least, wherein each grade frequency multiplier comprises a frequency multiplication unit at least, and respectively this frequency multiplication unit of the first order receives two fundamental frequency signals and selects signal as input signal and a fundamental frequency signal as this, and wherein should select the phase difference of signal is the mean value of these two input signal phase differences; And this selection signal is taken a sample to these two input signals, to produce a clock pulse signal with two times of this input signals, and signal is selected as an input signal or of this frequency multiplication unit in the frequency multiplication unit that exports the next stage frequency multiplier to, has so as to generation to be this first frequency 2
nOne output signal of multiple frequency, and n is the progression of this frequency multiplier.
According to above-mentioned conception, when n more than or equal to 2 the time, respectively the input signal of this frequency multiplication unit is this fundamental frequency signal or this output signal.
According to above-mentioned conception, wherein these several fundamental frequency signals were evenly distributed in the cycle of one 360 degree.
According to above-mentioned conception, should be a phase-locked loop wherein with the frequency time clock source.
According to above-mentioned conception, wherein this phase-locked loop comprises a voltage-controlled oscillator, is used to provide these fundamental frequency signals.
According to above-mentioned conception, wherein this voltage-controlled oscillator is that configuration and setting serves as reasons that several postpone the multipole differential ring-type oscillator that single unit born of the same parents are formed.
According to above-mentioned conception, wherein this frequency multiplier circuit is made up of the frequency multiplier of n level, and it comprises m frequency multiplication unit, and m is (3
n-1)/2.
According to above-mentioned conception, wherein this frequency multiplication unit is 2 pairs of 1 multiplexers.
According to above-mentioned conception, wherein this frequency multiplication unit be according to the high low level of this selection signal choose these two input signals one of them with output, and produce this two frequency-doubled signal.
For further specifying the purpose of this utility model, design feature and effect, the utility model is described in detail below with reference to accompanying drawing.
(4) description of drawings
Fig. 1 is a kind of circuit block diagram of high frequency time pulse generator of prior art.
Fig. 2 is the circuit block diagram of the high frequency time pulse generator of another kind of prior art.
Fig. 3 is a circuit block diagram of the present utility model.
Fig. 4 is the circuit configurations schematic diagram of the utility model with the voltage controlled oscillator in the frequency time clock source.
Fig. 5 is the multiplexer logical schematic that the utility model is used to produce the multistage frequency multiplier circuit of quadruple clock signal.
Fig. 6 is the clock pulse figure of each clock signal of each multiplexer among the utility model Fig. 5.
(5) embodiment
See also Fig. 3, it is the circuit block diagram of high frequency time pulse generator of the present utility model.It comprises together a time clock source 33 and a frequency multiplier circuit 34 frequently.Should be a phase-locked loop with time clock source 33 frequently wherein, and this frequency multiplier circuit 34 is made up of the frequency multiplier of one-level at least, the frequency multiplier of each grade comprises a frequency multiplication unit at least.Because the phase-locked loop is one to comprise the analog circuit of voltage controlled oscillator, wherein the output phase of voltage controlled oscillator and frequency are synchronous with the input reference signal that is received, so the utility model utilizes this phase-locked loop to produce the VCO clock signal (low frequency signal) of out of phase, this VCO clock signal is imported in this frequency multiplier circuit 34 again.To have same frequency but two VCO clock signals of out of phase input to the frequency multiplication unit, and with another VCO clock signal as selecting signal, this selects two VCO clock signal frequencies of frequency and this of signal identical, but phase difference is the mean value of these two VCO clock signal phase differences.By utilizing two kinds of accurate positions of height of selecting signal, respectively these two voltage-controlled concussion clock signals are taken a sample, can obtain the clock signal of a frequency for two times of this voltage-controlled concussion clock signals, it can directly export or input to the next stage frequency multiplier of this frequency multiplier circuit 34, to produce the clock signal of higher multiple frequency.
See also Fig. 4, it is the circuit configurations schematic diagram of the utility model with the voltage controlled oscillator in the frequency time clock source.Should be a phase-locked loop wherein with the frequency time clock source.The voltage controlled oscillator that is included in this phase-locked loop is served as reasons and is postponed the differential ring-type oscillator of a level Four that single unit born of the same parents (Unit Delay Cell) 41,42,43,44 are formed, the control of its phase delay is to finish by the bias voltage that changes each grade, so as to determining each to postpone single unit born of the same parents' phase delay, and each postpones single unit born of the same parents and provides two anti-phase phase delay clock signals to postpone single unit born of the same parents' input clock signal as next stage.In preferred embodiment of the present utility model, the voltage controlled oscillator in the phase-locked loop is to be designed to the differential ring-type oscillator of level Four shown in Figure 4, and its configuration can provide the voltage-controlled concussion clock signal of various phase phasic differences 45 degree be evenly distributed in one-period in.
See also Fig. 5 and Fig. 6, they are respectively the clock pulse figure of each clock signal of the multiplexer logical schematic of the utility model multistage frequency multiplier circuit of being used to produce the quadruple clock signal and each multiplexer.In preferred embodiment of the present utility model, this frequency multiplier circuit is to be made up of 51,52,53,54 of four two pairs one multiplexers, and it is set the clock signal that is used for producing a quadruple.Multiplexer 51,52,53 forms a first order frequency multiplier, and multiplexer 54 forms a second level frequency multiplier.
If need the clock signal output of higher frequency multiplication, only need to increase the progression of voltage controlled oscillator to produce the VCO clock signal of more outs of phase, and behind two couples, one multiplexer of Fig. 5, be connected in series the Multistage Frequency Multiplexer of forming by two pairs one multiplexers again, just can obtain the clock signal output of higher frequency multiplication.
As from the foregoing, suppose that m is two couples, the one multiplexer sum of frequency multiplier circuit, and the frequency of being wanted is 2
nFrequency multiplication, a simple formula can be derived by following checking computations:
When n=1, the one-level frequency multiplier that frequency multiplier circuit is made up of one or two pairs one multiplexers, then m=1; When n=2, frequency multiplier circuit is made up of the secondary frequency multiplier, and two couples, the one multiplexer number of first order frequency multiplier is 3, and two couples, the one multiplexer number of second level frequency multiplier is 1, then m=3 * 1+1=31+30=4; When n=3, frequency multiplier circuit is made up of three grades of frequency multipliers, and two couples, the one multiplexer number of first order frequency multiplier is 3 * 3, two couples, the one multiplexer number of second level frequency multiplier is 3 * 1, two couple of the third level, one multiplexer number is 1, then m=3 * 3+3 * 1+1=32+31+30=13; When n=4, frequency multiplier circuit is made up of the level Four frequency multiplier, and two couples, the one multiplexer number of first order frequency multiplier is 3 * 3 * 3, two couples, the one multiplexer number of second level frequency multiplier is 3 * 3, two couple of the third level, one multiplexer number is 3 * 1, two couple of the fourth stage, one multiplexer number is 1, then m=3 * 3 * 3+3 * 3+3 * 1+1=33+32+31+30=40.When frequency multiplier circuit was made up of n level frequency multiplier, wherein two couples, the one multiplexer number of first order frequency multiplier was 3
n-1, two couples, the one multiplexer number of second level frequency multiplier is 3
n=2, two couples, the one multiplexer number of third level frequency multiplier is 3
n-3 ..., two couples, the one multiplexer number of n level frequency multiplier is 30, then m=3
n-1+3
n-2+3
n-3+ ... + 30=(3
n-1)/2.
In sum, the utility model only need use a phase-locked loop to produce the low frequency clock signal, again couple the multistage frequency multiplier circuit formed by multiplexer to produce the high frequency time pulse signal thereafter, the utility model need not use delay-locked loop to produce the clock signal of various phase places, also need not allow the phase-locked loop be operated under the high frequency, can save many power consumptions, in addition, because the clock signal of various outs of phase all is from the voltage controlled oscillator in the phase-locked loop, therefore without any need for the control clock signal source that adds.In preferred embodiment of the present utility model, only need a voltage controlled oscillator to be operated in 1/4th of required output clock pulse frequency and get final product, so quite power saving.In addition, because the utility model is to utilize the mode of the high low level sampling of selecting signal that two VCO clock signals are chosen, to produce the high frequency time pulse signal, its duty cycle to the output clock signal of voltage controlled oscillator is very inresponsive, and each selects signal all is from voltage controlled oscillator, as long as the control of circuit layout is suitable, it is very little that the shake of voltage (jitter) can be controlled, and also can become very stable through the average frequency that gets off for a long time.The utility model is not only simplified the complex circuit designs degree of high frequency time pulse generator, saves many power consumptions simultaneously, effectively improves the disappearance of prior art, therefore has industrial value.
Certainly, those of ordinary skill in the art will be appreciated that, above embodiment is used for illustrating the utility model, and be not to be used as qualification of the present utility model, as long as in connotation scope of the present utility model, all will drop in the scope of the utility model claims variation, the modification of the above embodiment.
Claims (6)
1. a high frequency time pulse generator is characterized in that, comprising:
Time clock source frequently together is used to provide several fundamental frequency signals of out of phase, and wherein partly these several fundamental frequency signals are with the signal that elects; And
One frequency multiplier circuit, be coupled to this with time clock source frequently, it is made up of the frequency multiplier of one-level at least, and wherein each grade frequency multiplier comprises a frequency multiplication unit at least, and respectively this frequency multiplication unit of the first order receives two fundamental frequency signals and selects signal as input signal and a fundamental frequency signal as this, wherein
This selects the phase difference of signal is the mean value of these two input signal phase differences; And
This selection signal is taken a sample to these two input signals, to produce a clock pulse signal with two times of this input signals, and signal is selected as an input signal or of this frequency multiplication unit in the frequency multiplication unit that exports the next stage frequency multiplier to, has so as to generation to be this first frequency 2
nOne output signal of multiple frequency, and n is the progression of this frequency multiplier.
2. high frequency time pulse generator as claimed in claim 1 is characterized in that, this is a phase-locked loop with the frequency time clock source.
3. high frequency time pulse generator as claimed in claim 2 is characterized in that this phase-locked loop comprises a voltage-controlled oscillator, is used to provide these fundamental frequency signals.
4. high frequency time pulse generator as claimed in claim 3 is characterized in that, this voltage-controlled oscillator is that configuration and setting serves as reasons that several postpone the multipole differential ring-type oscillator that single unit born of the same parents are formed.
5. high frequency time pulse generator as claimed in claim 1 is characterized in that this frequency multiplier circuit is made up of the frequency multiplier of n level, and it comprises m frequency multiplication unit, and m is (3
n-1)/2.
6. high frequency time pulse generator as claimed in claim 1 is characterized in that, this frequency multiplication unit is 2 pairs of 1 multiplexers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02204400 CN2540066Y (en) | 2002-01-30 | 2002-01-30 | High frequency clock pulse generator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02204400 CN2540066Y (en) | 2002-01-30 | 2002-01-30 | High frequency clock pulse generator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2540066Y true CN2540066Y (en) | 2003-03-12 |
Family
ID=33686353
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02204400 Expired - Fee Related CN2540066Y (en) | 2002-01-30 | 2002-01-30 | High frequency clock pulse generator |
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| Country | Link |
|---|---|
| CN (1) | CN2540066Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111245430A (en) * | 2020-03-20 | 2020-06-05 | 深圳芯行科技有限公司 | Circuit and method capable of reducing power consumption of ring oscillator |
-
2002
- 2002-01-30 CN CN 02204400 patent/CN2540066Y/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111245430A (en) * | 2020-03-20 | 2020-06-05 | 深圳芯行科技有限公司 | Circuit and method capable of reducing power consumption of ring oscillator |
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| CF01 | Termination of patent right due to non-payment of annual fee |