CN2531577Y

CN2531577Y - Multi-frequency output clock-pulse signal synthesizer

Info

Publication number: CN2531577Y
Application number: CN 02208135
Authority: CN
Inventors: 李娟祯; 戴嘉良; 黄逸杰
Original assignee: Via Technologies Inc
Current assignee: Via Technologies Inc
Priority date: 2002-03-22
Filing date: 2002-03-22
Publication date: 2003-01-15
Anticipated expiration: 2012-03-22

Abstract

The utility model relates to a multiple frequency output clock pulse signal synthesizer which is used in a converter for converting progressive scanning image data into interlaced scanning image data. The converter is provided with a first reference clock pulse signal with the frequency of F1, and the clock pulse signal synthesizer comprises a phase locked loop oscillator which generates and outputs a clock pulse signal with the frequency of F1* N according to the first reference clock pulse signal received by the input end, a frequency eliminating feedback circuit which feeds back a feedback clock pulse signal with the frequency of F1 as the reference to the phase locked loop oscillator, a first frequency eliminating output circuit which outputs a first output clock pulse signal with the frequency of F1* N /P1, and a second frequency eliminating output circuit which outputs a second output clock pulse signal with the frequency of F1* N /P2. The values of P2/P1 are adjusted according to the ratio variation between the picture dots of the horizontal scanning lines of the progressive scanning image data and the interlaced scanning image data.

Description

The clock signal synthesizer of multi-frequency output

Technical field

The utility model relates to a kind of clock signal synthesizer of multi-frequency output, refers to be applied to the clock signal synthesizer of the multi-frequency output in the television signal encoder especially.

Background technology

Along with the rapid progress of manufacturing technology, PC has become people's necessary product of living, and it has powerful operation capacity, and the user can utilize it to finish the function of many other electronic products.Utilizing PC to play videodiscs such as VCD, DVD is an example, but it is too small because of the PC screen size usually, cause actual inconvenience of viewing and admiring, therefore provide a TV signal output end to utilize general domestic TV to show, become the critical function of display card in the PC.

Fig. 1 (a) is the partial function block schematic diagram of a display card (display adapter), wherein graph processing chips (graphic chip) 10 is exported pixel datas digital signal to a random access storage device arranged side by side digital to analog converter (Random Access Memory Digital-to-Analog Converter, be called for short RAM DAC) 11 and one television signal encoder 12 (TV encoder), and this pixel data digital signal arranged side by side is the analog signal that can supply computer display 13 to show after these random access storage device digital to analog converter 11 conversions.After the processing of this television signal encoder 12, can produce power supply as for this pixel data digital signal arranged side by side and look 14 anolog TV signals that show, and these anolog TV signals generally can be divided into NTSC and two kinds of specifications of PAL.

Fig. 1 (b) is the inner part function block schematic diagram of above-mentioned television signal encoder 12 (TV encoder), and wherein this pixel data digital signal arranged side by side is through data acquisition device (Data Capturedevice) 121, color space converter (Color Space Converter) 122, picture dimension adjustment and anti-scintillator (Scaler and Deflicker) 123, first-in first-out buffer (First-In First-Outbuffer) 124,14 NTSC specifications that show or PAL specification TV signal are looked in the power supply that the conversion of NTSC/PAL encoder (NTSC/PAL encoder) 125 and one digital to analog converter (Digital-to-Analog Converter) 126 produces.

Wherein this picture dimension adjustment and 123 processing one of anti-scintillator export it in first-in first-out buffer 124 to behind the image data line by line, and NTSC/PAL encoder 125 takes out described data processing again from first-in first-out buffer 124, and then the interlacing image data that is separated into Qi Tuchang (odd field) and bigraph field (evenfield) is to show on TV.Therefore, picture dimension adjustment and 123 processing required times of two horizontal scanning lines of anti-scintillator equal NTSC/PAL encoder 125 and handle the required times of a horizontal scanning line, so just relation as the following equation of the frequency Fe of the frequency Fsd of picture dimension adjustment and anti-scintillator 123 required clock signals and NTSC/PAL encoder 125 required clock signals are represented:

Fsd/Fe=2 * H_sd/H_e ... (formula 1)

Wherein H_sd is the pixel number of picture dimension adjustment and anti-scintillator 123 handled horizontal scanning lines, and H_e then is the pixel number of NTSC/PAL encoder 125 handled horizontal scanning lines.

But because television signal encoder 12 (TV encoder) inside only has a phase-locked loop clock pulse generator 127 to produce clock signal to offer picture dimension adjustment and anti-scintillator 123 and NTSC/PAL encoder 125 simultaneously, make Fsd=Fe, therefore when more and more (1024 points for example of the horizontal scanning line pixel quantity of picture dimension adjustment and anti-scintillator 123 handled image datas line by line, 1152 points, 1365 in addition to 1600 points) time, the image width that is presented at after treatment on the television image (needs to increase because of Fsd increases with horizontal scanning line pixel quantity with more and more narrow, Fe=Fsd again, and excessive Fe will cause the pixel output frequency of horizontal scanning line on the video screen too fast, and then cause the image narrowed width), the effective width that can't fully use TV to have originally.And how to improve the shortcoming of these existing means, be development main purpose of the present utility model.

Summary of the invention

The utility model is a kind of clock signal synthesizer of multi-frequency output, be applied to the image data displaying of lining by line scan is converted in the transducer of an interlacing scan image data displaying, provide in this transducer a frequency be F1 first with reference to clock signal, and this clock signal synthesizer comprises: a phase-locked loop oscillator produces clock signal that a frequency is F1 * N with reference to clock signal and by its output output according to received this of its input first; One frequency elimination feedback circuit is electrically connected on the input of this phase-locked loop oscillator, and it receives this frequency is that the clock signal of F1 * N carries out a frequency elimination operation divided by N, so feed back a frequency be F1 the feedback clock signal to this phase-locked loop oscillator for its reference; One first frequency elimination output circuit is electrically connected on this phase-locked loop oscillator, and it receives this frequency is that the clock signal of F1 * N carries out a frequency elimination operation divided by P1, and then exports the first output clock signal that a frequency is F1 * N/P1; And one second frequency elimination output circuit, be electrically connected on this phase-locked loop oscillator, it receives this frequency is that the clock signal of F1 * N carries out a frequency elimination operation divided by P2, and then export the second output clock signal that a frequency is F1 * N/P2, wherein the value of this P2/P1 is adjusted according to the variation of ratio between the horizontal scanning line pixel number of the horizontal scanning line pixel number of this image data displaying of lining by line scan and this interlacing scan image data displaying.

According to above-mentioned conception, this frequency is exported by a preposition frequency eliminating circuit with reference to clock signal by first of F1 in the clock signal synthesizer of multi-frequency described in the utility model output, it is that the original reference clock signal of D * F1 carries out a frequency elimination operation divided by D with frequency, and then exports the first output clock signal that this frequency is F1.

According to above-mentioned conception, this transducer is arranged on the television signal encoder in the display card in the clock signal synthesizer of multi-frequency output described in the utility model.

According to above-mentioned conception, this frequency is that the first output clock signal of F1 * N/P1 and the second output clock signal of this F1 * N/P2 are an adjusted size and an anti-scintillator and NTSC/PAL encoders that offers respectively in this television signal encoder in the clock signal synthesizer of multi-frequency output described in the utility model.

According to above-mentioned conception, this first frequency elimination output circuit and this second frequency elimination output circuit are finished divided by the P2 counter divided by P1 counter and by one respectively in the clock signal synthesizer of multi-frequency output described in the utility model.

Description of drawings

Fig. 1 (a) is the partial function block schematic diagram of a display card;

Fig. 1 (b) is the part function block schematic diagram of television signal encoder inside;

Fig. 2 is the preferred embodiment schematic diagram of the clock signal synthesizer of multi-frequency output of the present utility model.

Embodiment

Fig. 2 is the preferred embodiment schematic diagram that improves the clock signal synthesizer that a multi-frequency that above-mentioned existing means shortcoming develops out exports, and it mainly is made of preposition frequency eliminating circuit 20, phase-locked loop oscillator 21, frequency elimination feedback circuit 22, the first frequency elimination output circuit 23 and the second frequency elimination output circuit 24.

Its medium frequency is that to be undertaken one by preposition frequency eliminating circuit 20 be that the first output clock signal of F1 is to phase-locked loop oscillator 21 divided by the frequency elimination of D operation back output one frequency to the original reference clock signal of D * F1, to produce a frequency be the clock signal of F1 * N and export frequency elimination feedback circuit 22 to reference to clock signal and phase-locked loop oscillator 21 is according to received this first, it is that the clock signal of F1 * N carries out a frequency elimination operation divided by N that frequency elimination feedback circuit 22 receives these frequencies, so feed back a frequency be F1 the feedback clock signal to this phase-locked loop oscillator for its reference.As for can be respectively with divided by P1 counter and the first frequency elimination output circuit 23 and the second frequency elimination output circuit 24 finished divided by the P2 counter, be that to receive this frequency be the clock signal of F1 * N and carry out a frequency elimination operation and the frequency elimination operation divided by P2 divided by P1 respectively, and then export the second output clock signal that the first output clock signal that a frequency is F1 * N/P1 and a frequency are F1 * N/P2 respectively.

And the frequency that said apparatus produced to be the second output clock signal of first output clock signal and this F1 * N/P2 of F1 * N/P1 just can offer the adjusted size in this television signal encoder 12 respectively and prevent scintillator 123 and NTSC/PAL encoder 125.And can obtain equation as follows in the substitution formula 1:

Fsd/Fe=P2/P1=2 * H_sd/H_e ... (formula 2)

Therefore the ratio of Fsd and Fe can change by the value of adjusting P2/P1, so, just, can come P2/P1 is finely tuned according to the variation of ratio between the horizontal scanning line pixel number of the horizontal scanning line pixel number of this image data displaying of lining by line scan and this interlacing scan image data displaying.For example, under situation about P1 being adjusted to, will make Fe less than Fsd, and then the television image image width that originally narrows down can be relaxed to meeting the effective width that TV has originally less than P2, effectively improve the shortcoming of existing means, and then realize main purpose of the present utility model.

The present utility model can be made various obvious variations and modification by those of ordinary skill in the industry, but the protection range that neither disengaging claims are defined.

Claims

1. the clock signal synthesizer of multi-frequency output, be applied to the image data displaying of lining by line scan is converted in the transducer of an interlacing scan image data displaying, provide in this transducer a frequency be F1 first with reference to clock signal, it is characterized in that this clock signal synthesizer comprises:

One phase-locked loop oscillator produces clock signal that a frequency is F1 * N with reference to clock signal and by its output output according to received this of its input first;

One frequency elimination feedback circuit is electrically connected on the input of this phase-locked loop oscillator, and it receives this frequency is that the clock signal of F1 * N carries out a frequency elimination operation divided by N, so feed back a frequency be F1 the feedback clock signal to this phase-locked loop oscillator for its reference;

One first frequency elimination output circuit is electrically connected on this phase-locked loop oscillator, and it receives this frequency is that the clock signal of F1 * N carries out a frequency elimination operation divided by P1, and then exports the first output clock signal that a frequency is F1 * N/P1; And

One second frequency elimination output circuit, be electrically connected on this phase-locked loop oscillator, it receives this frequency is that the clock signal of F1 * N carries out a frequency elimination operation divided by P2, and then export the second output clock signal that a frequency is F1 * N/P2, wherein the value of this P2/P1 is to adjust according to the variation of ratio between the horizontal scanning line pixel number of the horizontal scanning line pixel number of this image data displaying of lining by line scan and this interlacing scan image data displaying.

2. the clock signal synthesizer of multi-frequency output as claimed in claim 1, it is characterized in that described frequency is exported by a preposition frequency eliminating circuit with reference to clock signal by first of F1, it is to be that the original reference clock signal of D * F1 carries out a frequency elimination operation divided by D with frequency, and then exports the first output clock signal that this frequency is F1.

3. the clock signal synthesizer of multi-frequency output as claimed in claim 1 is characterized in that described transducer is a television signal encoder that is arranged in the display card.

4. the clock signal synthesizer of multi-frequency output as claimed in claim 3 is characterized in that described frequency is that the first output clock signal of F1 * N/P1 and the second output clock signal of this F1 * N/P2 are an adjusted size and an anti-scintillator and NTSC/PAL encoders that offers respectively in this television signal encoder.

5. the clock signal synthesizer of multi-frequency output as claimed in claim 1 is characterized in that the described first frequency elimination output circuit and this second frequency elimination output circuit are finished divided by the P2 counter divided by P1 counter and by one respectively.