CN2518223Y - Wafer packing body structure - Google Patents
Wafer packing body structure Download PDFInfo
- Publication number
- CN2518223Y CN2518223Y CN 02204360 CN02204360U CN2518223Y CN 2518223 Y CN2518223 Y CN 2518223Y CN 02204360 CN02204360 CN 02204360 CN 02204360 U CN02204360 U CN 02204360U CN 2518223 Y CN2518223 Y CN 2518223Y
- Authority
- CN
- China
- Prior art keywords
- wafer
- insulating barrier
- package body
- conducting resinl
- body structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
A wafer package body structure at least comprises a wafer, an insulation layer, electricity-conducting glue, a plurality of ball pads, a welding shield layer and a plurality of welding balls; wherein, the wafer is provided with an initiative surface; the insulation layer is arranged on the initiative surface of the wafer; the insulation layer is provided with a plurality of ports which penetrate the insulation layer. The electricity-conducting glue is filled in the ports; the ball pads are arranged on the insulation layer and can be electrically connected with the electricity-conducting glue. The welding shield layer is coated on the insulation layer and the ball pads are exposed from the welding shield layer; in addition, the welding balls are separately arranged on the ball pads.
Description
Technical field
The utility model relates to a kind of wafer-level packaging, and particularly relevant for a kind of wafer-level packaging that can solve thermal expansion coefficient difference problem between wafer and motherboard.
Background technology
In the society of information explosion now, electronic product is dispersed throughout in the daily life, no matter aspect the clothing, food, lodging and transportion--basic necessities of life amusement, all can use the product that integrated circuit package is formed.Along with electronics technology evolution constantly, functional more complicated, more humane product is weeded out the old and bring forth the new, with regard to the electronic product outward appearance, also towards light, thin, short, little trend design, therefore technical at semi-conductor packaging, develop the form of many high-density semiconductor encapsulation.And can reach above-mentioned purpose by wafer size structure dress (Chip Scale Package) technology, the sectional dimension of the packaging body that its made is finished and the sectional dimension of wafer are roughly the same, so the volume of wafer size structure dress is very little, therefore be widely used in the technical of semiconductor packages.Wherein, the technology of reaching wafer size structure dress has a variety of, and wherein a kind of is the means of utilizing wafer-level packaging, reaches the purpose of wafer size structure dress.As its name suggests, wafer-level packaging is exactly that the encapsulation of wafer is just finished when the wafer cutting is finished.
With regard to its technology, at first to provide a wafer, wafer is made up of a plurality of wafer, and Cutting Road (scribe-line) is surrounded between the adjacent wafer.Make reconfiguration line structure body (redistribution layer) then to the active surface of wafer, then form projection to the reconfiguration line structure body, carry out the technology of wafer cutting afterwards, the reconfiguration line structure body on wafer and the wafer and the same structure body of adjacency are separated from each other, and form independently flip chip packaging body 100, as shown in Figure 1, so when the wafer cutting is finished, overlay crystal chip and packaging body thereof just complete, and wherein Fig. 1 is the section enlarged diagram of known wafer scale chip package.Wherein each flip chip packaging body 100 comprises a wafer 110, a reconfiguration line structure body 120 and a plurality of projection 130, wherein wafer 110 has a plurality of weld pads 114, be positioned on the active surface 112 of wafer 110, and reconfiguration line structure body 120 is positioned on the active surface 112 of wafer 110, reconfiguration line structure body 120 has insulating structure 122 and metallic circuit structure 124, and metallic circuit structure 124 can crisscross in the insulating structure 122, and metallic circuit structure 124 can electrically connect with weld pad 114.In addition, projection 130 is positioned on the reconfiguration line structure body 120, and can electrically connect with metallic circuit structure 124.
And flip chip packaging body 100 generally can be connected on the substrate 140, and substrate 140 has a plurality of bump pads 144 and a plurality of solder ball pad 148, lays respectively on the upper surface 142 of substrate 140 and on the lower surface 146.At this moment, can carry out reflow process, spill following scaling powder (not drawing) afterwards, by the mode of heating, the projection 130 of flip chip packaging body 100 can join on the bump pads 144 of substrate 140.Insert a packing material 150 then between flip chip packaging body 100 and the substrate 140, make packing material 150 can coat projection 130.Afterwards, also will plant a plurality of soldered balls 160 to solder ball pad 148, by soldered ball 160, substrate 140 can electrically connect with a printed circuit board (PCB) (not drawing).
Because therefore 140 thermal coefficient of expansions of wafer 110 and substrate different must fill in packing material 150 between wafer 110 and the substrate 140 in above-mentioned technology, with the thermal stress that prevents to be produced when the thermal cycle, the situation generation that causes projection 130 to break.Yet, because the gap between wafer 110 and the substrate 140 is very little, when inserting packing material 150, it is mode with capillarity, packing material 150 could flow between flip chip packaging body 100 and the substrate 140 lentamente, and is so very consuming time on technology, and cost is also higher, and packing material 150 is difficult for complete filling between flip chip packaging body 100 and the substrate 140, exists and leave the space.Moreover, since the two ends of projection 130 respectively with wafer 110 on reconfiguration line structure body 120 and the bump pads 144 of substrate 140 engage, so easily because wafer 110 and 140 thermal stress that caused of substrate, to the effect that projection 130 produces shearing, make projection 130 direction transversely to have the situation of breaking to produce.
The utility model content
Therefore one of the purpose of this utility model is exactly in that a kind of wafer level packaging structure and technology thereof are provided, and can reduce cost.
Two of the purpose of this utility model is providing a kind of wafer level packaging structure and technology thereof exactly, can solve because the different problems that cause of thermal coefficient of expansion between wafer and substrate.
For reaching above-mentioned and other purpose of the present utility model, a kind of wafer package body structure is proposed, comprise at least: a wafer, an insulating barrier, a conducting resinl, a plurality of ball pad, a welding cover layer and a plurality of soldered ball.Wherein wafer has an active surface, and insulating barrier is configured on the active surface of wafer, and insulating barrier has a plurality of openings, and opening runs through insulating barrier.Conducting resinl is filled in the opening, and a plurality of ball pad is configured on the insulating barrier, and can electrically connect with conducting resinl.And welding cover layer covers on the insulating barrier, and welding cover layer can expose the ball pad, and in addition, soldered ball is configured in respectively on the ball pad.
In addition, with regard on the structure, according to a preferred embodiment of the present utility model, one reconfiguration line structure body can be configured between insulating barrier and the wafer, and the reconfiguration line structure body has an insulating structure and a metallic circuit structure, the metallic circuit structure crisscrosses in the insulating structure, and the metallic circuit structure is electrically connected at conducting resinl and wafer.In addition, also can have projection in the opening, and conducting resinl can electrically connect with projection.
For reaching above-mentioned and other purpose of the present utility model, a kind of wafer-level packaging technology is proposed, a wafer at first is provided, this wafer has an active surface, then forms an insulating barrier on the active surface of wafer.Then form a plurality of being opened in the insulating barrier, and opening runs through insulating barrier.Then insert conducting resinl in opening, and form a metal level on surface of insulating layer, again metal level is defined a plurality of ball pads, and the ball pad can electrically connect with conducting resinl.Then form a welding cover layer on surface of insulating layer, this welding cover layer can expose the ball pad, and plants and connect a plurality of soldered balls on the ball pad.Last cutting crystal wafer and insulating barrier.
According to a preferred embodiment of the present utility model, wherein form insulating barrier to the active surface of wafer before, comprise that also carrying out one makes the reconfiguration line structure body technology, and a reconfiguration line structure body is formed on the active surface of wafer, then just form insulating barrier to the reconfiguration line structure body.In addition, wafer also has a plurality of projections, be configured on the active surface of wafer, and projection is arranged in the opening of insulating barrier.
In above-mentioned wafer level packaging structure, since conducting resinl be coated on projection around, and projection can electrically conduct on the soldered ball by conducting resinl, and because the ductility of conducting resinl is excellent, during the deformation that therefore produces when having Yin Re between wafer and printed circuit board (PCB), configuration by conducting resinl can significantly reduce the thermal stress that is caused between wafer and printed circuit board (PCB), and the situation that known projection like this breaks just can not take place.In addition, the volume of the individual packages body that the utility model cut down is very little, and independently the sectional area of packaging body is consistent with the sectional area of wafer for it, and because projection is arranged in the opening of insulating barrier, therefore more can reduce the height of individual packages body.In addition, wafer-level packaging technology of the present utility model is separated the mode made from known wafer and substrate and is integrated into one, so its production cost is more cheap.
Description of drawings
Fig. 1 is the section enlarged diagram of known wafer-level packaging;
Fig. 2 to Fig. 9 is the enlarged diagram according to a kind of wafer-level packaging technology of the utility model first preferred embodiment;
Figure 10 is the schematic diagram according to the wafer level packaging structure of the utility model second preferred embodiment;
Figure 11 is the schematic diagram according to the wafer level packaging structure of the utility model the 3rd preferred embodiment;
Figure 12 is the schematic diagram according to the wafer level packaging structure of the utility model the 4th preferred embodiment;
Figure 13 is the schematic diagram according to the wafer level packaging structure of the utility model the 5th preferred embodiment.
100: the crystal covered package body
110,211,510: wafer
112,212,312; 512: active surface
114,214,314,514: weld pad
120,220,420: the reconfiguration line structure body
122,222: insulating structure
124,224: the metallic circuit structure
130,230,330,430: projection
140: substrate
142,228: upper surface
144: bump pads
146: lower surface
148: solder ball pad
150: packing material
160,280,580: soldered ball
200,300: packaging body
210,310: wafer
213: the master end
226: contact
240,340,440,540: insulating barrier
242,342,442,542: opening
244: surface of insulating layer
250,450,550: conducting resinl
260,460: metal level
262,272,462,562: the ball pad
270: welding cover layer
290: printed circuit board (PCB)
464: circuit
Embodiment
Please refer to Fig. 2 to Fig. 9, it is the enlarged diagram according to a kind of wafer-level packaging technology of the utility model first preferred embodiment.Please earlier with reference to Fig. 2, one wafer 210 at first is provided, wafer 210 by a plurality of wafers 211 form (in Fig. 2, only drawing one of them), wafer 210 has an active surface 212, and wafer 210 also has a plurality of weld pads 214, is configured on the active surface 212 of wafer 210.In addition, definition wafer 210 has a master end 213, and semiconductor subassembly of wafer 210 (not drawing) and weld pad 214 are positioned at master end 213, and are active surface 212 on the 213 outermost surfaces, master end of wafer 210.
Make a reconfiguration line structure body 220 then and on the active surface 212 of wafer 210, (just be configured in the master end of wafer 210), and reconfiguration line structure body 220 has an insulating structure 222, a metallic circuit structure 224 and a plurality of contact 226, contact 226 exposes the upper surface 228 of reconfiguration line structure body 220, and metallic circuit structure 224 crisscrosses in the insulating structure 222, and the weld pad 214 of wafer 210 and contact 226 are electrically connected.Can utilize the mode of screen printing or the mode that little shadow is electroplated then, form a plurality of projections 230 to contact 226, wherein the material of projection 230 can be SAC alloy, sn-bi alloy, leypewter, nickel billon or gold.
Please refer to Fig. 3, next with the mode of hot pressing or the mode of spin coating, form an insulating barrier 240 and on the upper surface 228 of reconfiguration line structure body 220, (just be configured in the master end 213 of wafer 210), and insulating barrier 240 can coat projection 230, wherein the material of insulating barrier 240 can be a high molecular polymer, such as be epoxy resin (Epoxy), (polyimide, PI), and insulating barrier 240 has a surface of insulating layer 244 to polyimides.
Please refer to Fig. 4, can utilize the mode of lithography or the mode of laser drill then, form a plurality of openings 242 in insulating barrier 240, the position of the corresponding projection 230 in the position of opening 242, and opening 242 runs through insulating barrier 240, and can make projection 230 expose insulating barrier 240 by opening 242.Then insert a conducting resinl 250 in the opening 242 of insulating barrier 240, and conducting resinl 250 can electrically connect projection 230, wherein conducting resinl 250 is the resin of materials such as argentiferous or copper.
Please refer to Fig. 5, utilize modes such as pressing, sputter or plating then, a metal level 260 is made on the surface of insulating layer 244, wherein the material of metal level 260 can be a copper.
Please refer to Fig. 5 and Fig. 6, utilize the mode of lithography then, metal level 260 is defined a plurality of ball pads 262, and ball pad 262 is positioned on the conducting resinl 250.
Please refer to Fig. 7,, form a welding cover layer 270 on surface of insulating layer 244, and welding cover layer 270 has a plurality of openings 272, to expose ball pad 262 next in the mode of screen printing.
Please refer to Fig. 8, plant a plurality of soldered balls 280 then on ball pad 262.Cutting crystal wafer 210, reconfiguration line structure body 220 and insulating barrier 240 more at last, and form a plurality of independently packaging bodies 200 respectively.The independently packaging body 200 that so cuts down can make wafer 211 engage with the contact 292 of printed circuit board (PCB) 290 by soldered ball 280, forms structure as shown in Figure 9.
Please refer to Fig. 2 to Fig. 9, in above-mentioned wafer level packaging structure, since conducting resinl 250 be electrically connected at projection 230 around, and projection 230 can electrically conduct on the soldered ball 280 by conducting resinl 250, and because the ductility of conducting resinl 250 is excellent, therefore when wafer 211 and 290 deformation that have Yin Re and produce of printed circuit board (PCB), configuration by conducting resinl 250 can significantly reduce wafer 211 and 290 thermal stress that caused of printed circuit board (PCB), and the situation that known projection like this breaks just can not take place.
In addition, the volume of the independently packaging body 200 that cuts down is very little, independently the sectional area of packaging body 200 is consistent with the sectional area of wafer 211 for it, and because projection 230 is arranged in the opening 242 of insulating barrier 240, therefore more can reduce the height of individual packages body 200.In addition, wafer-level packaging technology of the present utility model is separated the mode made from known wafer and substrate and is integrated into one, so its production cost is more cheap.
With regard to technology now, because the soldered ball that engages with printed circuit board (PCB), its minimum spacing is between 300 microns to 500 microns, yet may diminish to, the spacing of weld pad only has only 50 microns, so it must utilize the design of reshuffling circuit, it is connected outer contact layout again, make the spacing of producing soldered ball can reach the purpose that engages with printed circuit board (PCB).Wherein, reshuffle the design of circuit, except the described mode of above-mentioned first preferred embodiment, also can be other mode, as described below.
Please refer to Figure 10, it is the schematic diagram according to the wafer level packaging structure of the utility model second preferred embodiment, and wherein insulating barrier 340 directly is formed on the active surface 312 of wafer 310, and can expose weld pad 314 by the opening 342 of insulating barrier 340.And the mode by lithography can define metal level 360 a plurality of circuits 364 and a plurality of ball pad 362, carrying out the action that circuit is reshuffled, and ball pad 362 is configured to the position that is suitable for planting soldered ball 380.In addition, can be designed to not have the form of projection in the opening 342 of insulating barrier 340, and whole opening 342 is inserted conducting resinl 350 fully.So do not need projection, just can carry out wafer-level packaging technology, therefore can save the step of making projection, can reduce production costs simultaneously yet.Yet, as shown in figure 11, it is the schematic diagram according to the wafer level packaging structure of the utility model the 3rd preferred embodiment, also can make projection 330 in the opening 342 of insulating barrier 340, because projection 330 is a metal, therefore its electric conductivity can promote the electric conductivity of packaging body 300 greater than conducting resinl 350 by the configuration of projection 330.And the configuration of remaining component is all identical with second preferred embodiment, just repeats no more at this.
In addition, please refer to Figure 12, it is the schematic diagram according to the wafer level packaging structure of the utility model the 4th preferred embodiment.After upstream manufacturer is making reconfiguration line structure body 420, when if the position of its formation projection 430 is not corresponding with the contact of printed circuit board (PCB) (not drawing), also can be when making metal level 460, reshuffle the action of circuit again, make the position of ball pad 462 to match, and ball pad 462 can electrically connect by circuit 464 and conducting resinl 450 with the position of the contact of printed circuit board (PCB).In addition, also can be designed to not have the form of projection in the opening 442 of insulating barrier 440, and whole opening 442 is inserted conducting resinl 450.
In the above-described embodiment, reshuffle the action of circuit, make that the position of ball pad can be corresponding with the position of the contact of printed circuit board (PCB), and can make and have enough spacings between adjacent solder balls by reconfiguration line structure body or metal level.Yet the utility model is not limited only to aforesaid application, it is corresponding also can being designed to weld pad 514 configurations of wafer 510 and the joint configuration of printed circuit board (PCB) (not drawing), as shown in figure 13, it is the schematic diagram according to the wafer level packaging structure of the utility model the 5th preferred embodiment.So do not need on the active surface 512 of wafer 510, to make the reconfiguration line structure body, and ball pad 562 is formulated on the conducting resinl 550 in the opening 542 of insulating barrier 540, and the configuration of soldered ball 580 is corresponding with the configuration of weld pad 514.In addition, also can make projection in the opening 542 of insulating barrier 540, and can promote the electric conductivity of packaging body by the configuration of projection.
Therefore,, all can use wafer-level packaging method of the present utility model, make wafer after encapsulation is finished, just can directly engage by soldered ball with printed circuit board (PCB) no matter whether upstream manufacturer has made projection.So with regard on the structure of packaging body, can have projection in the opening of insulating barrier, also can not have projection.
In addition, having the structure of conducting resinl in the opening of insulating barrier of the present utility model, is not only to use in the above-described embodiment, can be applied in other aspect yet, such as being that to be applied in the making of substrate first-class.
In sum, the utility model has following advantages at least:
1. wafer level packaging structure of the present utility model and technology thereof are because conducting resinl is coated on Around the projection, and projection can electrically conduct on the soldered ball by conducting resinl, and because Therefore the ductility of conducting resinl is excellent, has Yin Re when between wafer and printed circuit board (PCB) and produces Deformation the time, the configuration by conducting resinl can significantly reduce institute between wafer and printed circuit board (PCB) The thermal stress that causes, the situation that known projection like this breaks just can not take place.
2. wafer level packaging structure of the present utility model and technology thereof, its last institute cuts down The volume of individual packages body very little, and the sectional area of individual packages body can with the cross section of wafer Long-pending consistent, and because projection is arranged in the opening of insulating barrier, therefore more can reduce independence The height of packaging body.
3. wafer level packaging structure of the present utility model and technology thereof can make production cost more For cheap.
Claims (10)
1, a kind of wafer package body structure is characterized in that, this structure comprises at least:
One wafer, this wafer has a master end;
One insulating barrier is configured in this master end of this wafer, and this insulating barrier has a plurality of openings, and those openings run through this insulating barrier;
One conducting resinl, this conducting resinl are filled in those openings;
A plurality of ball pads are configured on this insulating barrier, and electrically connect with this conducting resinl;
One welding cover layer, this welding cover layer covers this insulating barrier, and this welding cover layer can expose those ball pads; And
A plurality of soldered balls are configured in respectively on those ball pads.
2, wafer package body structure as claimed in claim 1, it is characterized in that, this structure more comprises a reconfiguration line structure body (Redistribution Layer), between this insulating barrier and this wafer, this reconfiguration line structure body has an insulating structure and a metallic circuit structure, this metallic circuit structure crisscrosses in this insulating structure, and this metallic circuit structure is electrically connected at this conducting resinl and this wafer.
3, wafer package body structure as claimed in claim 1 is characterized in that, this structure more comprises a plurality of projections, be configured in respectively in those openings, and this conducting resinl and those projections electrically connects.
4, wafer package body structure as claimed in claim 3 is characterized in that, the material of those projections is a leypewter.
5, wafer package body structure as claimed in claim 3 is characterized in that, the material of those projections is the nickel billon.
6, wafer package body structure as claimed in claim 3 is characterized in that, the material of those projections is a gold.
7, wafer package body structure as claimed in claim 3 is characterized in that, the material of those projections is the SAC alloy.
8, wafer package body structure as claimed in claim 3 is characterized in that, the material of those projections is a sn-bi alloy.
9, wafer package body structure as claimed in claim 1 is characterized in that, this insulating barrier is a polyimides.
10, wafer package body structure as claimed in claim 1 is characterized in that, this insulating barrier is an epoxy resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02204360 CN2518223Y (en) | 2002-01-29 | 2002-01-29 | Wafer packing body structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02204360 CN2518223Y (en) | 2002-01-29 | 2002-01-29 | Wafer packing body structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2518223Y true CN2518223Y (en) | 2002-10-23 |
Family
ID=33686321
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02204360 Expired - Lifetime CN2518223Y (en) | 2002-01-29 | 2002-01-29 | Wafer packing body structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2518223Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103400816A (en) * | 2013-06-26 | 2013-11-20 | 三星半导体(中国)研究开发有限公司 | Packaging part and manufacturing method thereof |
-
2002
- 2002-01-29 CN CN 02204360 patent/CN2518223Y/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103400816A (en) * | 2013-06-26 | 2013-11-20 | 三星半导体(中国)研究开发有限公司 | Packaging part and manufacturing method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Effective date of abandoning: 20020129 |
|
| C25 | Abandonment of patent right or utility model to avoid double patenting |