CN2507208Y

CN2507208Y - Television standard time code demodulator

Info

Publication number: CN2507208Y
Application number: CN01273712U
Authority: CN
Inventors: 梁双有; 任燕
Original assignee: National Time Service Center of CAS
Current assignee: National Time Service Center of CAS
Priority date: 2001-12-17
Filing date: 2001-12-17
Publication date: 2002-08-21
Anticipated expiration: 2011-12-17

Abstract

The utility model relates to a television standard time code demodulator which is used in precise time comparison. The circuit of the television standard time code demodulator is provided with eleven units. The television standard time code demodulator is characterized in that the video signal of CCTV is processed through synchronous separation to obtain composite synchronizing pulse, and is processed through a line-field separation circuit to obtain field pulse. Synchronizing pulse is selected from the field pulse after digital delay, and then identification pulse, second pulse and time code pulse are selected from a time code signal. Finally, BCD time is put out. The utility model has simple circuit, low code error rate, strong practicability, low cost and high precision. The television standard time code demodulator can be used in precise time comparison of satellite television. The television standard time code demodulator can also be widely used in the field of national defence, scientific research, traffic and communications.

Description

Television standard timing code demodulator

Technical field

The utility model belongs to standard time frequency measurement technical field, relates to a kind of television standard timing code demodulator when carrying out the chronometer time comparison.

Background technology

At present in China, standard time and standard frequency all are to serve as the comparison standard with giving the correct time of the Chinese Central Television (CCTV), and giving the correct time of the Chinese Central Television (CCTV) is that standard time and standard frequency by a cesium-beam atomic clock produces is as the criterion.This cesium-beam atomic clock is through the frequency reference of frequency synthesizer output 4.43361875MHz frequency signal as Chinese Central Television's system synchronization signal.The accuracy of second and standard frequency (comprising subcarrier) is better than 1 * 10 ^-12The moment accuracy of standard time is better than 3 μ s.The second of various places and the accuracy of standard frequency are better than 5 * 10 beyond Beijing ^-12But it is former, the standard time demodulator that is used for timing and calibrating frequency that China uses is but all developed in the eighties mostly voluntarily, because it comprises time and frequency demodulation two cover circuit, the circuit complexity, backward in technique, the error rate is high, time showing is often glimmered, influence its performance, and the cost height, inconvenience with apply.

Summary of the invention

At above-mentioned prior art situation, the purpose of this utility model is, gives users, especially needs the user of standard time, and reliable, a cheap timing and frequency calibration set apparatus are provided.

According to the regulation of the GB7402-87 of State Standard Bureau (UDC621.391.8.08) standard " utilizing TV signal to transmit the standard time frequency ", China is inserted in standard time, standard frequency and platform sign indicating number information in the 16th row and the 329th row of TV signal flyback.Be benchmark with the synchronous forward position of row in the 16th row, be arranged in order and be: identification pulse, standard frequency, pulse per second (PPS) and sign indicating number constantly.Be arranged in order in the 329th row and be identification pulse, standard frequency and platform sign indicating number.According to this regulation, the utility model has designed and has a kind ofly received only time code signal in the demodulation CCTV signal, had only time-code demodulation circuit kit, only select timing code, the pulse per second (PPS) of 16 row for use, do not select the television standard timing code demodulator of the 1MHz frequency signal in 329 row and 16 row for use, this demodulator has saved circuit such as the clamp in the former demodulator, the maintenance of sampling, phase demodulation, the empty vibration of pressure, loop filtering, its cost has only 1/8th of former demodulator, and from physically having solved the error code problem of time-code demodulation.The operation principle of the utility model television standard timing code demodulator circuit is such: (Phase Alternation Line system) that receives, two, arbitrary composite video signal is given synchronous separating unit (1) and digital shaping unit (5) simultaneously in the quadruplet program, synchronous separating unit (1) is isolated composite synchronizing signal, composite synchronizing signal is isolated field system chronizing impulse through a row separative element (2), through digital delay unit I (3), form the strobe pulse of one 32 μ s, the clock of digital delay I unit (3) is the 1MHz signal that is come by crystal oscillator unit (11), select horizontal pulse from composite synchronizing signal, to select 16 horizontal synchronizing pulses output through 16 row gating units (4), identification pulse gating unit (6) is given in 16 horizontal synchronizing pulses simultaneously, selects identification pulse from time code signal.The clock of identification pulse gating unit (6) is the 1MHz signal of crystal oscillator, and time code signal comes from digital shaping unit (5).Numeral shaping unit (5) directly amplifies TV signal, shaping, and the output time code signal is given identification pulse gating unit (6), pulse per second (PPS) gating unit (8), string and converting unit (10) simultaneously.Identification pulse from identification pulse gating unit (6) is selected through digital delay II (7), successively forms two pulses, and one is the second strobe pulse that forms 4 μ s after 25 μ s postpone, and one is the trigger impulse that postpones 0.1 μ s of formation through 29.6 μ s.The clock of digital delay II unit (7) is the 10MHz signal that comes from crystal oscillator.The second strobe pulse of 4 μ s is selected a second signal through pulse per second (PPS) gating unit (8) from time code signal, and output after broadening, buffering.Identification pulse removes to trigger shift pulse and forms unit (9) after 29.6 μ s postpone, and forms the clock pulse of the 1MHz of one 20 μ s.The clock signal that shift pulse forms unit (9) is the 10MHz signal of crystal oscillator.String and converting unit (10) are given in the shift clock pulse of 20 μ s, convert the serial timing code in the time code signal to parallel BCD (two/decimal system) timing code and export, content sometimes, minute, second.

Its concrete technical solution is as described below:

The utility model television standard timing code demodulator circuit, have synchronous separating unit, digital delay unit, 16 horizontal synchronizing pulse gatings, dfisplacement pulse extraction unit, the serial parallel converting unit is characterized in that: also have a row separative element (2), digital shaping unit (5), the earlier logical unit (6) of identification pulse, pulse per second (PPS) gating unit (8), unit, crystal oscillator unit (11); The CCTV vision signal is through the compound time code signal of digital shaping unit (5) output; Time relationship based on time code signal and field pulse, the synchronous arteries and veins strictnesses of 16 row behind the I (3) to synchronous separating unit (1) output, produces strobe pulse, selects 16 horizontal synchronizing pulses; With 16 behavior reference points, select the identification pulse in the time code signal; Identification pulse produces strobe pulse behind digital delay unit II (7), select pulse per second (PPS); Strobe pulse is given shift pulse simultaneously and is formed unit (9), forms shift pulse, gives serial parallel converting unit (10) time code signal is changed; Identification pulse, pulse per second (PPS), time code signal are all directly selected from the complex digital signal of digital shaping unit (5) output; Clock signal selected in each unit produces by digital crystal oscillator unit (11); Timing circuit among the digital delay unit I (3) adopts binary counter chip MC4040 of a 4K position, with direct acquisition forward position 928 μ s, the back strobe pulse along one the 32 μ s of 960 μ s; Adopting the clock pulse from crystal oscillator unit (11) among the digital delay unit II (7) is 10MHz, postpones with the decimal that obtains 29.6 μ s; 10MHz is adopted in the counter clock pulse that shift pulse forms in the unit (9), so that the middle mistake displacement of time-code and the phase drift that is caused by frequency difference of can not causing of the time-code code element of 1 μ s just in time dropped in the triggering forward position of 20 shift pulses.

Description of drawings

Fig. 1: the utility model television standard timing code demodulator operation principle block diagram

Fig. 2: the utility model television standard timing code demodulator circuit schematic diagram

Wherein: digital corresponding among the numeral in each square frame of Fig. 1 and Fig. 2 in each frame of broken lines.

Below in conjunction with Fig. 1, Fig. 2 present design is elaborated:

(1) synchronous separating unit: give synchronous separating unit and shaping digital units the CCTV composite video signal that receives simultaneously.Synchronous separating unit is made up of the emitter follower of T1 pipe, the sync separator of T2 pipe and the amplifier of T3 pipe, and T3 selected scenes effect pipe is to have buffer action.Signal after field effect transistor T3 amplifies is exported composite synchronizing signal through the U2:F paraphase by 12 pin.Composite synchronizing signal is divided two-way, and one the tunnel gives row, a separative element, and one the tunnel gives 16 row gating units.

(2) row, a separative element: composite synchronizing pulse is sent into by R15, C1, R16, C2 and is formed the second order integrating circuit, and has utilized the switching characteristic of transistor T 4.When integrated value during greater than 0.7V, switch transistor T 4 conductings, output low level; When integrated value during less than 0.7V, T4 ends, the output high level.Form a field pulse signal thus.After exempting from paraphase, exports U2 by 10 pin.

(3) digital delay unit I: the field system chronizing impulse rising edge triggers d type flip flop, makes that the 8 pin great changes of U3:B are low level, the 1MHz clock count that counter U4 (MC4040) comes with crystal oscillator.When counter meter during to 928 μ s, the positive pulse of 11 pin output at U8:D triggers U6:B; When counter meter during to 960 μ s, the negative pulse of 3 pin output at U5:A makes trigger U3:B, U6:B return-to-zero.8 pin of U3:B become high level, and counter MC4040 return-to-zero stops counting, so just the strobe pulse of criticizing at one 3 μ s of the Q of U6:B end output.

(4) 16 row gating units: the 32 μ s strobe pulses that come by digital delay unit I and composite synchronizing signal through U8:C with, select 16 every trade lock-out pulses, drive through buffering and export.

(5) digital shaping unit: the CCTV vision signal is through comparison circuit LM311, and from digital time code signal of 7 pin output, potentiometer W1 is in order to adjust sampled level.Identification pulse gating unit, pulse per second (PPS) gating unit, serial parallel conversion unit are given in this signal output simultaneously.

(6) identification pulse gating unit: U6:A is triggered on the back edge with 16 horizontal pulses, the identification pulse of forming via U6:A, U5:B, U9:A forms circuit, at one 10 little strobe pulse of the disconnected output of U6:A ground Q, with time code signal through U8:A with, gating goes out identification pulse.

(7) digital delay unit II: trigger U9:B by identification pulse, make counting circuit U9:B, U11 count, during counting output 25 μ s, trigger U10:A, count down to 29 μ s, 8 ends output return-to-zero pulse at U2:D, make trigger U10zA return-to-zero, rolling counters forward goes to trigger the shift pulse unit during to 29.6 μ s, make the U10:B return-to-zero after the paraphase simultaneously, counter stops counting.One 4 wide strobe pulse of μ s of Q end output of U10zA.The clock pulse of used here digital delay counter is 10MHz, chooses the strobe pulse of 4 μ s, can make the strobe pulse of second select pulse per second (PPS) to greatest extent, is unlikely to falsely drop front portion, other signals of rear portion of pulse per second (PPS) again.

(8) pulse per second (PPS) gating unit: by the strobe pulse of 4 next μ s of digital delay unit II, select pulse per second (PPS) in the time code signal through U8:B, pass through the U17:A monostable circuit again, with the pulse per second (PPS) broadening is 1pps (one of the per second) pulse of 100ms (millisecond), drives output through U2:D, U1:A buffering again.

(9) shift pulse forms the unit: by digital delay! The trigger impulse that I comes removes to trigger U3:A, and the Q end of U3:A becomes low level, makes U1 hundred million U15:B counting, and 20 is little after after the U2:C return-to-zero, counting stops.So just at 20 shift pulses that frequency is 1MHz of the Q3 of U15:B output.The decimal that counter adopts the clock pulse of 10MHz 1. can make digital delaying circuit II obtain 29.6 μ s postpones, and makes 20! The MHz shift pulse triggers the forward position and just in time is in the middle of the 1 μ s code element of time-code.2. can guarantee crystal oscillator frequency and the time frequency difference between the symbol frequency cause and the phase drift of shift pulse can not cause time-code displacement error code.Because it is 0.1 μ s that the drift of the maximum phase of 10MHz clock pulse can not surpass 1 cycle, and the time-code code-element period is 1 μ s.

(10) serial parallel conversion: 20 shift pulses by the output of U15:B9 pin, carry out shift LD to time code signal via U12, U13, U14 circuit, at parallel binary coded decimal time code of output output of shift LD, when content is, minute, second.

(11) crystal oscillation: the crystal oscillation unit is a common digital crystal-oscillator circuit.10MHz gives digital delaying circuit I and identification pulse gating circuit as counting clock pulse through U15:A frequency division output 1MHz clock signal,! 0MHz gives digital delaying circuit II and shift pulse forms circuit.

Embodiment

The binary coded decimal time code of the utility model output is connected with clock display circuit in any device that needs the standard time demonstration through decoder, display, in the time of just can demonstrating Beijing time of standard, minute, second.The 1pps of output can be used as high-precision timing signal, after the utility model adds decoding, demonstration, power supply, just can become one independently telechron and satellite receiver combine, just can constitute the satellite television clock.The utility model also can be used as parts and is installed in other equipment, for example is contained in the television set, and television set has had the standard time function.Be contained in the computer, can be used as the computer network synchronization criterion.Can also provide a unified standard time for station, harbour, office building.The utility model can be widely used in many fields such as national defence, scientific research, traffic, communication.

Claims

1, a kind of television standard timing code demodulator, have synchronous separating unit, digital delay unit, 16 horizontal synchronizing pulse gatings, dfisplacement pulse extraction unit, the serial parallel converting unit is characterized in that: also have a row separative element, digital shaping unit, the earlier logical unit of identification pulse, pulse per second (PPS) gating unit, unit, crystal oscillator unit; The CCTV vision signal is through the compound time code signal of digital shaping unit output; Based on the time relationship of time code signal and field pulse, 16 horizontal synchronizing pulse strictnesses, the composite synchronizing signal of synchronous separating unit output is carried out separated in synchronization; With the field pulse is reference point, behind digital delay unit I, produces strobe pulse, selects 16 horizontal synchronizing pulses; With 16 behavior reference points, select the identification pulse in the time code signal; Identification pulse produces strobe pulse behind digital delay unit II, select pulse per second (PPS); Strobe pulse is given shift pulse simultaneously and is formed the unit, forms shift pulse, gives the serial parallel converting unit time code signal is changed.

2, a kind of television standard timing code demodulator according to claim 1 is characterized in that: identification pulse, pulse per second (PPS), time code signal are all directly selected from the complex digital signal of digital shaping unit output; Clock signal selected in each unit produces by digital crystal oscillator unit.

3, a kind of television standard timing code demodulator according to claim 1 is characterized in that: the timing circuit among the digital delay unit I adopts binary counter chip MC4040 of a 4K position; Adopting the clock pulse from the crystal oscillator unit among the digital delay unit II is 10MHz; 10MHz is adopted in the counter clock pulse that shift pulse forms in the unit.