CN2435790Y - External-set on-line IC card read/write device - Google Patents
External-set on-line IC card read/write device Download PDFInfo
- Publication number
- CN2435790Y CN2435790Y CN 00224989 CN00224989U CN2435790Y CN 2435790 Y CN2435790 Y CN 2435790Y CN 00224989 CN00224989 CN 00224989 CN 00224989 U CN00224989 U CN 00224989U CN 2435790 Y CN2435790 Y CN 2435790Y
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- Prior art keywords
- chip
- circuit
- card
- pin
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- Expired - Fee Related
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Abstract
The utility model relates to an external on-line IC card reader-writer, which is composed of a monolithic computer 1, a latching and data storage circuit 2, RS-232 interface circuit 3, IC card write-read circuit 4, a power-fail protecting control circuit 5, a special fake preventing chip 6 with encrypted logic, a spring clip circuit 7, and a buzzer circuit 8. The utility model which has the advantages of simple structure, easy fabrication, convenient operation, high read-write speed, small size, strong data encryption function, and large data storage quantity is suitable for the IC card distribution, fee charging, unmanned inquiry terminal, a universal reader-writer, etc.
Description
The utility model relates to a kind of IC-card read write line, and refering in particular to is a kind of external on-line IC-card read write line.
IC-card more and more is subject to people's attention as the high-tech product of the good security performance of a kind of tool, the IC-card read write line, as with the matching used a kind of imperative equipment of IC-card, also existing various types appear on the market, but because due to its structure, it is big to exist volume, unhandy shortcoming.
The purpose of this utility model is to overcome the deficiency of prior art and provides a kind of rational in infrastructure, and volume is small and exquisite, the external on-line IC-card read write line that can use with computer interconnection.
The utility model is to adopt following proposal to realize: it is by one-chip computer 1, latch and data-storing circuit 2, RS-232 interface circuit 3, IC-card read/write circuit 4, power down protection control circuit 5, the special anti-counterfeiting chip 6 of band encryption logic, bullet card circuit 7, buzzer circuit 8 is formed, described one-chip computer 1 is made up of ic chip 1, latch and data-storing circuit 2 by ic chip 2, IC3 forms, RS-232 interface circuit 3 is by ic chip 4, capacitor C 3-C6 forms, IC-card read/write circuit 4 is by triode T1, T2, IC socket S, resistance R 3, R7 forms, power down protection control circuit 5 is by ic chip 9, resistance R 5, diode D3, accumulator B1 forms, the special anti-counterfeiting chip 6 of band encryption logic is made up of ic chip 10, bullet card circuit 7 is by triode BD682, inductance POPD, diode IN4148 forms, and buzzer circuit 8 is by triode RING-N; Hummer RING forms, diode IN4148 forms, and 32 I/O mouth lines of the ic chip 1 of one-chip computer are divided into four ports of P0-P3, P0, P2 mouth connect respectively latch and data-storing circuit 2 in ic chip 2, IC3, P1 interface IC card read/write circuit 4 and band encrypt special anti-counterfeiting chip 6, the output that the P3 mouth connects RS-232 interface circuit 3, bullet card circuit 7, buzzer circuit 8, P2 mouth is simultaneously as the Data Control line of special anti-counterfeiting chip 6.
Concrete structure of the present utility model describes in detail below in conjunction with accompanying drawing:
Accompanying drawing 1 is the utility model outside drawing.
Accompanying drawing 2 is the utility model electricity theory diagram.
Accompanying drawing 3 is the electrical schematic diagram of single-chip microcomputer in the utility model.
Accompanying drawing 4 is data-storing and an address latch circuit schematic diagram in the utility model.
Accompanying drawing 5 is a RS-232 interface electrical schematic diagram in the utility model.
Accompanying drawing 6 is an IC-card read/write circuit schematic diagram in the utility model.
Accompanying drawing 7 is a band encryption logic special chip electrical schematic diagram in the utility model.
Accompanying drawing 8 is a power down protection electrical schematic diagram in the utility model.
Accompanying drawing 9 is the utility model card circuit theory diagrams of being hit by a bullet.
Accompanying drawing 10 is a buzzer circuit schematic diagram in the utility model.
See accompanying drawing 1-10, the surface of the utility model casing M is provided with IC-card socket S, operating key N, Y, in the casing M circuit board is housed, circuit board is by one-chip computer 1, latch and data-storing circuit 2, RS-232 interface circuit 3, IC-card read/write circuit 4, power down protection control circuit 5, the special anti-counterfeiting chip 6 of band encryption logic, bullet card circuit 7, buzzer circuit 8 is formed, described one-chip computer 1 is made up of ic chip 1, latch and data-storing circuit 2 by ic chip 2, IC3 forms, RS-232 interface circuit 3 is by ic chip 4, capacitor C 3-C6 forms, IC-card read/write circuit 4 is by triode T1, T2, IC socket S, resistance R 3, R7 forms, and power down protection control circuit 5 is by ic chip 9, resistance R 5, diode D3, accumulator B1 forms, the special anti-counterfeiting chip 6 of band encryption logic is made up of ic chip 10, and bullet card circuit 7 is by triode BD682, inductance POPD, diode IN4148 forms, and buzzer circuit 8 is by triode RING-N; Hummer RING forms, diode IN4148 forms, and 32 I/O mouth lines of the ic chip 1 of one-chip computer are divided into four ports of P0-P3, P0, P2 mouth connect respectively latch and data-storing circuit 2 in ic chip 2, IC3, P1 interface IC card read/write circuit 4 and band encrypt special anti-counterfeiting chip 6, the output that the P3 mouth connects RS-232 interface circuit 3, bullet card circuit 7, buzzer circuit 8, P2 mouth is simultaneously as the Data Control line of special anti-counterfeiting chip 6.The 3rd, 4,7,8,13,14,17,18 pin of described address latch IC3 are 39,38,37,36,35,34,33,32 pin of order sheet computing machine respectively, be used for least-significant byte address latch, thereby 8 bit address signals exported to memory ic chip 2 by its 8 bit address with single-chip microcomputer IC1; The 2nd, 5,6,9,12,15,16,19 of IC3 links to each other with the 10th, 9,8,7,6,5,4,3 pin of IC4 respectively, so that provide the least-significant byte address to IC4 behind the least-significant byte address signal process IC3 address latch of one-chip computer IC1 output; The 39th, 38,37,36,35,34,33,32 pin of IC1 connect the 11st, 12,13,14,15,16,17,18,19 pin of ic chip 2 respectively, with the exchanges data between realization and the single-chip microcomputer IC1; The 21st of single-chip microcomputer IC1 the, 22,23,24,25,26,27,28 pin connect the 24th, 21,23,2,26,1 pin of ic chip 2 respectively in addition, as the 9th, 10,11,12,13,14,15 bit address lines.
In the utility model, the integrated package model is:
IC1---8051 or 89C51,87C51
IC2——62256
IC3——74HC373
IC4——MXA232
IC9——MXD1210
IC10——ENCRUPTY
Principle of work of the present utility model is sketched in following:
When single-chip microcomputer IC1 desire is operated IC2, will hang down 8 address latches through IC3, and, can directly realize the 32K address space of IC2 is carried out read-write operation by the high 7 bit address control of IC1 to IC2.
The effect of ic chip 4 is that serial signal with single-chip microcomputer IC1 and external relation carries out level conversion in the RS-232 interface circuit; The IC-card read/write circuit is that six pins of P1 mouth, P1.0, P1.1, P1.2, P1.3, P1.4, P1.5 by single-chip microcomputer IC1 are controlled the IC-card read/write circuit, stably to read the information in the IC-card; Integrated package ENCRUPTY is that several pins of the P1 mouth by IC1 and several pins of P2 mouth are realized control to it in the false proof chip of dedicated encrypted, so that the utility model possesses the logical encrypt antiforge function; The power down protection circuit mainly is to carry out Energy Saving Control under power-down state; integrated package MXD1210 passes through the control of the 28th pin of single-chip microcomputer IC1 to its 5th pin/CEI; make high level of the 6th pin output of MXD1210; thereby the chip selection signal of control data storage ic chip 2 (62256); IC2 is not worked; realize the function of power down protection, buzzer circuit passes through the control of the 14th pin of single-chip microcomputer IC1 to the level of triode RIN-N, to realize cut-offfing of control hummer RING.In the utility model, the all operations order is exported by one-chip computer IC1, generally speaking, one-chip computer is in a kind of query State all the time to the state of IC-card read write line, when IC-card inserted card read head for ID, one-chip computer just began IC-card to be checked verification, if this IC-card can not be by verification, one-chip computer will be by sending the prompting of alternative sounds to the control of hummer; If IC-card can be by checking, verification, then single-chip microcomputer continues IC-card is carried out read-write operation, finish read-write operation after, single-chip microcomputer will be controlled IC-card bullet card circuit IC-card will be ejected card read head for ID.
In sum, the utility model is simple in structure, and processing and manufacturing is easy, and is easy to use, and read or write speed is fast, and volume is little, and data encryption feature is strong, and the data-storing amount is big, is applicable to the IC-card hair fastener, charge, and unmanned inquiry terminal, general read write line etc. are located to use.
Claims (1)
1, external on-line IC-card read write line, the surface of casing M is provided with IC-card socket S, operating key N, Y, in the casing M circuit board is housed, circuit board is by one-chip computer (1), latch and data-storing circuit (2), RS-232 interface circuit (3), IC-card read/write circuit (4), power down protection control circuit (5), the special anti-counterfeiting chip (6) of band encryption logic, bullet card circuit (7), buzzer circuit (8) is formed, described one-chip computer (1) is made up of ic chip 1, latch and data-storing circuit (2) by ic chip 2, IC3 forms, RS-232 interface circuit (3) is by ic chip 4, capacitor C 3-C6 forms, IC-card read/write circuit (4) is by triode T1, T2, IC socket S, resistance R 3, R7 forms, power down protection control circuit (5) is by ic chip 9, resistance R 5, diode D3, accumulator B1 forms, the special anti-counterfeiting chip (6) of band encryption logic is made up of ic chip 10, bullet card circuit (7) is by triode BD682, inductance POPD, diode IN4148 forms, and buzzer circuit (8) is by triode RING-N; Hummer RING forms, diode IN4148 forms, it is characterized in that: 32 I/O mouth lines of the ic chip 1 of one-chip computer are divided into four ports of P0-P3, P0, P2 mouth connect respectively latch and data-storing circuit (2) in ic chip 2, IC3, P1 interface IC card read/write circuit (4) and band encrypt special anti-counterfeiting chip (6), the output that the P3 mouth connects RS-232 interface circuit (3), bullet card circuit (7), buzzer circuit (8), P2 mouth is simultaneously as the Data Control line of special anti-counterfeiting chip (6).The 3rd, 4,7,8,13,14,17,18 pin of described address latch IC3 are 39,38,37,36,35,34,33,32 pin of order sheet computing machine respectively, be used for least-significant byte address latch, thereby 8 bit address signals exported to memory ic chip 2 by its 8 bit address with single-chip microcomputer IC1; The 2nd, 5,6,9,12,15,16,19 of IC3 links to each other with the 10th, 9,8,7,6,5,4,3 pin of IC4 respectively, so that provide the least-significant byte address to IC4 behind the least-significant byte address signal process IC3 address latch of one-chip computer IC1 output; The 39th, 38,37,36,35,34,33,32 pin of IC1 connect the 11st, 12,13,14,15,16,17,18,19 pin of ic chip 2 respectively, with the exchanges data between realization and the single-chip microcomputer IC1; The 21st of single-chip microcomputer IC1 the, 22,23,24,25,26,27,28 pin connect the 24th, 21,23,2,26,1 pin of ic chip 2 respectively in addition, as the 9th, 10,11,12,13,14,15 bit address lines.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN 00224989 CN2435790Y (en) | 2000-06-13 | 2000-06-13 | External-set on-line IC card read/write device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN 00224989 CN2435790Y (en) | 2000-06-13 | 2000-06-13 | External-set on-line IC card read/write device |
Publications (1)
Publication Number | Publication Date |
---|---|
CN2435790Y true CN2435790Y (en) | 2001-06-20 |
Family
ID=33589205
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN 00224989 Expired - Fee Related CN2435790Y (en) | 2000-06-13 | 2000-06-13 | External-set on-line IC card read/write device |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN2435790Y (en) |
-
2000
- 2000-06-13 CN CN 00224989 patent/CN2435790Y/en not_active Expired - Fee Related
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C19 | Lapse of patent right due to non-payment of the annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |