CN2449288Y - Online intelligent read/write device for traffic police - Google Patents

Abstract

The utility model relates to an online intelligent read / write device for traffic polices, which is composed of a single chip computer 1, a latch and data storing circuit 2, an RS-232 interface circuit 3, an IC card read/write circuit 4, a power-off protecting and controlling circuit 5, a special anti-forge encryption logic circuit 6, a spring fastener circuit 7, a buzzer circuit 8, a hardware reset circuit 9 and a power circuit 10 which are connected. The machine has the advantages of small volume, convenience, fast speed and high safety; the utility model is especially suitable for being used by the traffic polices in organ places connected with a computer; the utility model can read and store various traffic controlling information by inserting an IC card, receive superior terminal command and exchange corresponding data; the utility model can raise traffic control work efficiency.

Description

The special-purpose inline process type intelligent card read/write device of traffic police

The utility model relates to a kind of Digital Data Processing Equipment, specifically is meant a kind of inline process type intelligent card read/write device that is particularly suitable for the traffic police of vehicle supervision department special use.

Along with the arrival in global economic integration epoch, the application that just effectively promotes smart card (being IC-card) of making rapid progress of infotech develops to more senior direction.Compare with traditional data transmission set, smart card has higher security, and is more convenient, and can bring bigger economic benefit, so smart card is as some function devices of financial payment, application system, network engineering or the like.As the bigger vehicle supervision department of information processing capacity, just progressively carry out using a kind of tree peony traffic control card smart card of (comprising tree peony policeman card and tree peony driver card) that is called now, but at present in the machine-operated place of traffic police's work, the smart card read-write facility that also do not match and use with tree peony traffic control card, therefore a large amount of indoor numerical data works of treatment of carrying out in machine-operated place, annual examination registration and inquiry such as driver's vehicle, the registration and the inquiry of the violating the regulations in violation of rules and regulations and punishment situation of driver, the login of driver personal overview and inquiry, the login of policeman's curriculum vitae overview and rewards and punishments situation and inquiry or the like, all still be to be undertaken by the loaded down with trivial details liber of manually registering and consult, so that work efficiency is very low, the requirement of incompatibility information age.

In view of this, the purpose of this utility model, be provide a kind of traffic police of being particularly suitable in machine-operated place with the storing and read various traffic management informations and improve the inline process type intelligent card read/write device of management work efficient greatly of the online use of upper strata computation layer.

Referring to Fig. 1 the utility model electricity functional-block diagram, solution of the present utility model is as follows.Its circuit part is by one-chip computer 1; latch and data-storing circuit (RAM) 2; RS-232 interface circuit 3; IC-card read/write circuit 4; power down protection control circuit 5; the special anti-counterfeiting circuit 6 of band encryption logic; bullet card circuit 7; buzzer circuit 8; hardware reset circuit 9; power circuit 10 connects to form; wherein one-chip computer 1 respectively with latch and data-storing circuit 2; RS-232 interface circuit 3; IC-card read/write circuit 4; power down protection control circuit 5; the special anti-counterfeiting circuit 6 of band encryption logic; bullet card circuit 7; buzzer circuit 8; the part interface of hardware reset circuit 9 joins; latch and the data-storing circuit of data-storing circuit 2 links to each other with the interface of the special anti-counterfeiting circuit 6 of band encryption logic; the interface of power down protection control circuit 5 with latch and the data-storing circuit of data-storing circuit 2 joins; the interface of RS-232 interface circuit 3 links to each other with hardware reset circuit 9, and the power end of the power output end of power circuit 10 and other circuit of complete machine joins so that dc supply to be provided.

The utility model with foregoing circuit structure, because its one-chip computer 1 joins with the part interface of aforementioned circuit 2 to 9 respectively, so can realize the exchanges data of machine intimate respectively, the exchanges data that realization and machine exterior top level computer carry out, realization is to the read-write control of IC-card, under power-down state, realize power down protection control, realization is to the control of the special anti-counterfeiting circuit of band encryption logic, realization is to the control of bullet card circuit bullet card, realization is to the control of buzzer circuit sounding, and the control that the realization machine hardware resets under the deadlock situation; Owing to latch and the data-storing circuit of data-storing circuit 2 links to each other with the interface of the special anti-counterfeiting circuit 6 of band encryption logic, thus can realize and the special anti-counterfeiting circuit 6 with encryption logic between carry out exchanges data; Since the interface of power down protection control circuit 5 with latch and the data-storing circuit of data-storing circuit 2 joins, so can be implemented under the power-down state the control that enables to the data storage circuit; Because the interface of RS-232 interface circuit 3 links to each other with hardware reset circuit 9, so can be by upper strata PC control machine hardware reset under situation about crashing.Groundwork principle of the present utility model is as follows: 1. realize the read-write operation to IC-card: this is the most important processing capacity of the utility model.Under normal circumstances, 1 pair of IC-card read/write circuit 4 part of one-chip computer are in a kind of query State all the time, when having IC-card to insert in the IC-card slot on casing surface, will be with the detector switch jack-up of this IC-card, one-chip computer 1 detects after this level variation, just begin this IC-card is carried out the puppet card, bad card, useless card, the card type of nonsystematic card is differentiated, carry out the authentication that password relatively waits a series of system cards then, differentiate, have only the legal tree peony traffic control card of traffic control system (to comprise tree peony policeman card, tree peony driver card) could pass through, other card type is refused without exception.If this card is legal tree peony traffic control card, one-chip computer 1 just sticks into capable reading and writing operation to the tree peony traffic control, can be in time and tree peony traffic control card swap data.2. the function of serial asynchronous communication: one-chip computer 1 communicates with the serial line interface of traffic control terminal in upper strata by RS-232 interface circuit 3, the data upload that will read from tree peony traffic control card is given terminal, make terminal can in time and exactly accept the relevant information of tree peony traffic control card, or one-chip computer 1 accepts the order of terminal by the RS-232 serial line interface, realizes the corresponding operating to tree peony traffic control card.

The utlity model has following advantage and technical characterstic: 1. manufacturing cost is no more than 500 yuan, just can realize IC-card function of reading with the PC interconnection, can all storage cards, logic encryption card, CPU stick into capable read-write operation in the ISO7816-3 standard to meeting, domestic consumer can both afford economically, being suitable for mass consumption, is a kind of general product; 2. can in time inquire about the insertion state of IC-card, in case after having IC-card to insert, more correct with regard to differentiation, authentication, the password contrast work of promptly carrying out a series of cards through password, carry out reading and writing data at once, simple and fast, safe; 3. communicate by RS-232 serial line interface and upper strata traffic police's computing machine, general computing machine all has the RS-232 serial line interface, connect simple and convenient, less demanding to top level computer, in addition because one-chip computer 1 is little with the exchanges data amount of top level computer, so just enough with the RS-232 serial line interface, there is no need with other complicated communication modes; 4. making that the traffic police is indoor in machine-operated place can store quickly and easily and read various traffic management informations, thereby has improved the efficient of traffic administration work greatly.

Below in conjunction with drawings and Examples the utility model is further described.

Fig. 1 is a circuit frame principle figure of the present utility model;

Fig. 2 is a kind of physical circuit embodiment of Fig. 1 frame principle figure.

Referring to Fig. 1 and Fig. 2.One-chip computer 1 is connected to form with C13 and crystal oscillator X1 by single-chip microcomputer U1, capacitor C 8; Latch and data-storing circuit 2 is connected to form by address latch U3, data memory U2 and switch S IP; RS-232 interface circuit 3 is connected to form by serial line interface integrated package U5, serial port joint sun seat U7 and U8 and capacitor C 10 to C12; IC-card read/write circuit 4 is by IC-card read-write seat U4, Sheffer stroke gate U9, triode S1 and S2, resistance R 4 and R7, exclusion R11, and resistance R 10, crystal oscillator X2 and capacitor C 15 connect to form with C16; Power down protection control circuit 5 is connected to form by voltage comparator U6, battery B1, resistance R 5 and diode D3; The anti-tseudo circuit 6 of band encryption logic is made of the special anti-counterfeiting integrated package U10 of band encryption logic; Bullet card circuit 7 is connected to form by triode S4, diode D4 and inductance L 1; Buzzer circuit 8 is connected to form by triode S5 and buzzer FM; Hardware reset circuit 9 is connected to form with R2, resistance R 8 and capacitor C 14 by triode S3, diode D1 and D2, resistance R 1; Power circuit 10 is connected to form with R15 and capacitor C 1 to C7 by supply socket P, bridge heap B, integrated package of pressure-stabilizing M1, light emitting diode D5 and D6, resistance R 6.

In annexation between each circuit described in Fig. 1 technical solution and circuit working principle, be to come specific implementation like this in Fig. 2 embodiment:

U3 the 3rd pin D0 connects the 39th pin D0 of U1, U3 the 4th pin D1 connects U1 the 38th pin D1, U3 the 7th pin D2 connects U1 the 37th pin D2, U3 the 8th pin D3 connects U1 the 36th pin D3, and U3 the 13rd pin D4 connects U1 the 35th pin D4, and U3 the 14th pin D5 connects U1 the 34th pin D5, U3 the 17th pin D6 connects U1 the 33rd pin D6, U3 the 18th pin D7 connects U1 the 32nd pin D7, and U3 is used for U1 least-significant byte address latch, thereby by its least-significant byte address the least-significant byte address signal is exported to U2; U3 the 2nd pin A0 links to each other with U2 the 10th pin A0, U3 the 5th pin A1 links to each other with U2 the 9th pin A1, U3 the 6th pin A2 links to each other with U2 the 8th pin A2, U3 the 9th pin A3 links to each other with U2 the 7th pin A3, U3 the 12nd pin A4 links to each other with U2 the 6th pin A4, and U3 the 15th pin A5 links to each other with U2 the 5th pin A5, and U3 the 16th pin A6 links to each other with U2 the 4th pin A6, U3 the 19th pin A7 links to each other with U2 the 3rd pin A7, and this part mainly is to U2 to provide least-significant byte address later with the least-significant byte address signal that U1 exports through the U3 address latch; U1 the 39th pin D0 meets U2 the 11st pin D0 and makes the 1st position datawire, U1 the 38th pin D1 meets U2 the 12nd pin D1 and makes the 2nd position datawire, U1 the 37th pin D2 meets U2 the 13rd pin D2 and makes the 3rd position datawire, U1 the 36th pin D3 meets U2 the 15th pin D3 and makes the 4th position datawire, U1 the 35th pin D4 meets U2 the 16th pin D4 and makes the 5th position datawire, U1 the 34th pin D5 meets U2 the 17th pin D5 and makes the 6th position datawire, U1 the 33rd pin D6 meets U2 the 18th pin D6 and makes the 7th position datawire, U1 the 32nd pin D7 meets U2 the 19th pin D7 and makes the 8th position datawire, like this, 8 position datawires of U2 have just coupled together with 8 position datawires of U1, can directly carry out exchanges data; In addition, U1 the 21st pin P20 meets U2 the 25th pin A8 and makes the 9th bit address line, U1 the 22nd pin P21 meets U2 the 24th pin A9 and makes the 10th bit address line, U1 the 23rd pin P22 meets U2 the 21st pin A10 and makes the 11st bit address line, U1 the 24th pin P23 meets U2 the 23rd pin A11 and makes the 12nd bit address line, U1 the 25th pin P24 meets U2 the 2nd pin A12 and makes the 13rd bit address line, U1 the 26th pin P25 meets U2 the 26th pin A13 and makes the 14th bit address line, U1 the 27th pin P26 meets U2 the 1st pin A14 and makes the 15th bit address line, when the U1 desire is operated U2, U3 is with the least-significant byte address latch for process, and passes through the control to high 7 bit address of U2, can directly realize the 32K address space of U2 is carried out read-write operation.

The 11st pin TXD of U1, the 10th pin RXD are as serial port input, carry-out bit, the 11st pin T1IN, the 12nd pin R1OUT that connect U5 respectively, be used for carrying out level conversion with the RS-232 serial signal of external relation, RS-232 serial joint U7 and U8 are the data transmission intermediary of U5.

P1.0, the P1.2 of the P1 mouth of U1, P1.3, P1.5 and/these five pins of INT1 connect C7, C2, C6 and C8, A1, the C4 pin of U4 respectively, the P1.4 pin of U1 connects the end of R4, wherein P1.5 is used to detect the on off operating mode of A1, A2 two pins, whether promptly be used for detecting U4 has IC-card to insert, if there is IC-card to insert, this switch opens then, the P1.5 pin is a high level, by other pin the state of U4 is controlled, carried out exchanges data by P1.0 and U4 simultaneously; Form sequential control circuit by U9, X2, R10, C15, C16, U9 is a kind of TTL Sheffer stroke gate integrated circuit, two pin T1 of U1 and P1.1 are connected the 5th pin and the 10th pin of U9 respectively, when U1 need carry out control operation to U4, can be by the pulse output of T1 and two pin control of P1.1 U9:D the 11st pin CLK, whether control provides the time sequential routine to U4, and then whether control is controlled the read-write of U4.

The 28th pin P27 of U1 links to each other with the 5th pin A15 of U6, and U1 is P27 output high level under the state of power down, makes U6 the 5th pin also be high level.

The 2nd pin P1.1 of U1, the 8th pin P1.7, the 24th pin A11, the 25th pin A12, the 26th pin A13, the 27th pin A14 link to each other with the 17th pin P1.1, the 32nd pin P1.7, the 28th pin A11, the 25th pin A12, the 1st pin A13, the 8th pin A14 of U10 respectively, U1 makes U10 can provide the band encryption logic false proof mode bit and data bit by the state that P1.1 and P1.7 and four address wire A11, A12, A13, A14 can control U10.

The base stage of U1 the 12nd pin/INT0 and S4 is joined, can control the bullet card of bullet card circuit, when system to the IC-card end of operation, can automatically IC-card be ejected, the base stage of U1 the 14th pin T0 and S5 is joined, U1 can make hummer FM sounding by the control to S5 base stage level height, to go up electroacoustic prompting and false alarm prompting.U1 the 9th pin RESET connects the common port of D1 negative pole and D2 negative pole, when the RESET of hardware reset circuit 9 brings out existing high level, gets final product control single chip computer U1 hardware reset.

The 23rd pin A11 of U2, the 2nd pin A12, the 26th pin A13, the 1st pin A14 link to each other with the 28th pin A11, the 25th pin A12, the 1st pin A13, the 8th pin A14 of U10 respectively, and U10 provides to U2 by A11～14 pin has false proof mode bit and the data bit of band encryption logic.The 6th pin TO256 of U6 and the 20th pin CE of U2 join; the 1st pin VTO256 of U6 links to each other with the end of switch S IP on being connected on U2 the 28th pin VCC; under power-down state; because U6 the 5th pin is a high level; so U6 the 1st, 6 pin are controlled the state of U2 the 28th, 20 pin respectively; the control chip selection signal is not worked U2, reaches the effect of power down protection.The 9th pin TORST of U5 links to each other with the end of R8 on being connected on the S3 base stage, when the utility model when fortuitous event occurring and crash, as long as outside (generally being by top level computer control) gives U7 by the 4th pin DTR of U7 and U8, U8 transmits a high level, make U5 the 9th pin TORST output high level, the base stage of the S3 of control hardware reset circuit, make the public connecting end RESET of D1 and D2 high level occur, that is make the 9th pin RESET of U1 bring out existing high level, thereby control the utility model resets, like this, utilize external devices that operation of the present utility model is controlled, can avoid the utility model the endless loop phenomenon to occur, because the utility model upper strata PC can be installed function software of the present utility model, so can reset by the upper strata PC control the utility model that outreaches.

The circuit of the power circuit 10 among earlier figures 2 embodiment is formed, be a kind of typical rectification and mu balanced circuit, power circuit 10 is from integrated package of pressure-stabilizing M1 the 3rd pin output positive supply VCC, from common out-put supply GND, to offer other circuit of this machine as dc supply.The negative pole of D5 links to each other with the 7th pin P1.6 of U1.When the utility model had DC power supply, light emitting diode D6 was luminous always, as powering on indication.When the IC-card that U4 is inserted as U1 of the present utility model was operated, whether the level state control D5 of the P1.6 pin by control U1 was luminous, as the indication of operation IC-card.

In Fig. 2 embodiment, U1 adopts AT89C52, and U2 adopts 62256, U3 adopts 74HC373, and U4 adopts universal I C card read-write deck SLOT AMP-IC, and R11 adopts 5K6 * 8, U5 adopts MAX232, U6 adopts MXD1210, and U7 and U8 adopt 9 pin serial port joints sun seat, and U9 adopts 74HC00, U10 adopts ENCRUPTY, hummer adopts RING, and B adopts BRIDGE, and M1 adopts MC7805T.Above product is all commercially available.

Claims (2)

1; the special-purpose inline process type intelligent card read/write device of a kind of traffic police; it is characterized in that; circuit part is by one-chip computer (1); latch and data-storing circuit (2); RS-232 interface circuit (3); IC-card read/write circuit (4); power down protection control circuit (5); the special anti-counterfeiting circuit (6) of band encryption logic; bullet card circuit (7); buzzer circuit (8); hardware reset circuit (9); power circuit (10) connects to form; wherein one-chip computer (1) respectively with latch and data-storing circuit (2); RS-232 interface circuit (3); IC-card read/write circuit (4); power down protection control circuit (5); the special anti-counterfeiting circuit (6) of band encryption logic; bullet card circuit (7); buzzer circuit (8); the part interface of hardware reset circuit (9) joins; latch and the data-storing circuit of data-storing circuit (2) links to each other with the interface of the special anti-counterfeiting circuit (6) of band encryption logic; the interface of power down protection control circuit (5) with latch and the data-storing circuit of data-storing circuit (2) joins; the interface of RS-232 interface circuit (3) links to each other with hardware reset circuit (9), and the power output end of power circuit (10) and the power end of other circuit of complete machine join so that dc supply to be provided.

2, the special-purpose inline process type intelligent card read/write device of traffic police according to claim 1 is characterized in that:

(A) one-chip computer (1) is connected to form with C13 and crystal oscillator X1 by single-chip microcomputer U1, capacitor C 8; Latch and data-storing circuit (2) by address latch U3, data memory U2 and switch S IP connect to form; RS-232 interface circuit (3) is connected to form by serial line interface integrated package U5, serial port joint sun seat U7 and U8 and capacitor C 10 to C12; IC-card read/write circuit (4) is by IC-card read-write seat U4, Sheffer stroke gate U9, triode S1 and S2, resistance R 4 and R7, exclusion R11, and resistance R 10, crystal oscillator X2 and capacitor C 15 connect to form with C16; Power down protection control circuit (5) is connected to form by voltage comparator U6, battery B1, resistance R 5 and diode D3; The special anti-counterfeiting circuit (6) of band encryption logic is made of the special anti-counterfeiting integrated package U10 of band encryption logic; Bullet card circuit (7) is connected to form by triode S4, diode D4 and inductance L 1; Buzzer circuit (8) is connected to form by triode S5 and buzzer FM; Hardware reset circuit (9) is connected to form with R2, resistance R 8 and capacitor C 14 by triode S3, diode D1 and D2, resistance R 1; Power circuit (10) is connected to form with R15 and capacitor C 1 to C7 by supply socket P, bridge heap B, integrated package of pressure-stabilizing M1, light emitting diode D5 and D6, resistance R 6.

(B) U3 the 3rd pin D0 connects the 39th pin D0 of U1, U3 the 4th pin D1 connects U1 the 38th pin D1, U3 the 7th pin D2 connects U1 the 37th pin D2, U3 the 8th pin D3 connects U1 the 36th pin D3, U3 the 13rd pin D4 connects U1 the 35th pin D4, U3 the 14th pin D5 connects U1 the 34th pin D5, and U3 the 17th pin D6 connects U1 the 33rd pin D6, and U3 the 18th pin D7 connects U1 the 32nd pin D7; U3 the 2nd pin A0 links to each other with U2 the 10th pin A0, U3 the 5th pin A1 links to each other with U2 the 9th pin A1, U3 the 6th pin A2 links to each other with U2 the 8th pin A2, U3 the 9th pin A3 links to each other with U2 the 7th pin A3, U3 the 12nd pin A4 links to each other with U2 the 6th pin A4, U3 the 15th pin A5 links to each other with U2 the 5th pin A5, and U3 the 16th pin A6 links to each other with U2 the 4th pin A6, and U3 the 19th pin A7 links to each other with U2 the 3rd pin A7; U1 the 39th pin D0 meets U2 the 11st pin D0, U1 the 38th pin D1 meets U2 the 12nd pin D1, U1 the 37th pin D2 meets U2 the 13rd pin D2, U1 the 36th pin D3 meets U2 the 15th pin D3, U1 the 35th pin D4 meets U2 the 16th pin D4, U1 the 34th pin D5 meets U2 the 17th pin D5, U1 the 33rd pin D6 meets U2 the 18th pin D6, and U1 the 32nd pin D7 meets U2 the 19th pin D7, and U1 the 21st pin P20 meets U2 the 25th pin A8, U1 the 22nd pin P21 meets U2 the 24th pin A9, U1 the 23rd pin P22 meets U2 the 21st pin A10, and U1 the 24th pin P23 meets U2 the 23rd pin A11, and U1 the 25th pin P24 meets U2 the 2nd pin A12, U1 the 26th pin P25 meets U2 the 26th pin A13, and U1 the 27th pin P26 meets U2 the 1st pin A14; U1 the 11st pin TXD, the 10th pin RXD connect U5 the 11st pin T1IN, the 12nd pin R1OUT respectively; The P1.0 of U1, P1.2, P1.3, P1.5 and/these five pins of INT1 connect C7, C2, C6 and C8, A1, the C4 pin of U4 respectively, the P1.4 pin of U1 connects the end of R4, two pin T1 of U1 are connected U9 the 5th pin and the 10th pin respectively with P1.1; U1 the 28th pin P27 links to each other with U6 the 5th pin A15; U1 the 2nd pin P1.1, the 8th pin P1.7, the 24th pin A11, the 25th pin A12, the 26th pin A13, the 27th pin A14 link to each other with U10 the 17th pin P1.1, the 32nd pin P1.7, the 28th pin A11, the 25th pin A12, the 1st pin A13, the 8th pin A14 respectively; The base stage of U1 the 12nd pin/INT0 and S4 is joined; The base stage of U1 the 14th pin T0 and S5 is joined; U1 the 9th pin RESET connects the common port of D1 negative pole and D2 negative pole.

(C) U2 the 23rd pin A11, the 2nd pin A12, the 26th pin A13, the 1st pin A14 link to each other with U10 the 28th pin A11, the 25th pin A12, the 1st pin A13, the 8th pin A14 respectively; U6 the 6th pin TO256 and U2 the 20th pin CE join, and U6 the 1st pin VTO256 links to each other with the end of switch S IP on being connected on U2 the 28th pin VCC; U5 the 9th pin TORST links to each other with the end of R8 on being connected on the S3 base stage; M1 the 3rd pin output positive supply VCC of power circuit (10), from common out-put supply GND, the negative pole of D5 links to each other with U1 the 7th pin P1.6.

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