CN2398802Y - One-board switching circuit - Google Patents
One-board switching circuit Download PDFInfo
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- CN2398802Y CN2398802Y CN 99245604 CN99245604U CN2398802Y CN 2398802 Y CN2398802 Y CN 2398802Y CN 99245604 CN99245604 CN 99245604 CN 99245604 U CN99245604 U CN 99245604U CN 2398802 Y CN2398802 Y CN 2398802Y
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Abstract
The utility model discloses a one-board switching circuit, which is respectively connected with a main board, a relative board and a switching actuating mechanism through connecting terminals. The utility model comprises a main board failure detecting circuit and a switching signals originating circuit. The connecting terminals comprise a main and standby state feedback output terminal, a low-frequency pulse input terminal, a main output connecting terminal and a standby input connecting terminal. The main board failure detecting circuit comprises a DC voltage-isolating capacitor, a rectification filter circuit and an electronic switch. The switching signals originating circuit comprises one or more than one gating circuits, a final stage NAND gate of the switching signals originating circuit and a corresponding NAND gate of the relative board form an interlocking circuit. When a one-board has a failure, the utility model can automatically realize switching, and has the advantages of simple circuit structure and high reliability.
Description
The utility model relates to a kind of board switchover circuit that possesses hardware from switch function.
In the reliability design of system, it is an important designing technique that veneer possesses reliable switch function.Conventional design is the state that utilizes plate, switches by the software control veneer, has following several mode usually: 1, the master is equipped with backstage full powers control mode; 2, the master is equipped with the board software control mode; 3, be equipped with to fall master, backstage full powers control mode; 4, be equipped with to fall master, board software control mode.Here so-called " veneer " is meant the unit of one or several circuit arrangement formation that can finish certain function in the equipment, it can be on a circuit board, also can be on a plurality of circuit boards but be referred to as one " veneer ", because its function outbalance, if important fault is arranged in the device on veneer, need replace with a standby board, promptly so-called " switching " arrives " to plate ", and so-called " to plate " promptly refers to main with the corresponding standby board of veneer herein.
The shortcoming that top several switchover modes are all had nothing in common with each other.For mode 1, initiate to switch by mainboard, swing to slave board (being that slave board is upgraded to mainboard), its process is detected to issue orders behind the main board failure by the backstage and switches, if mainboard is just undesired with communicating by letter of backstage, this order of switching just can't be carried out so, and it is invalid switching.For mode 2, detect the back by the CPU in the mainboard veneer and initiate to switch, make slave board be upgraded to mainboard, still, if CPU breaks down as crashing, race flies, the shortcoming that same existence can't be switched; For mode 3,4, be to initiate to switch by slave board, make and oneself be upgraded to mainboard, but have same problem.
Another shortcoming of top several switchover modes is to switch holding time long (may reach 1～2 second when switching as the backstage).Because above-mentioned several modes all need negater circuit is made in EPLD (Erasableprogrammable Logic Device Erasable Programmable Logic Device) or FPGA (the FieldProgrammable Gate Array field programmable gate array) device, be subject to other device influences like this.
The purpose of this utility model is exactly in order to overcome the above problems, and provides a kind of backstage or CPU of not needing to intervene, find the board switchover circuit that this single plate hardware is made mistakes or CPU just can switch when changeing dead immediately.
The utility model realizes that the scheme of above-mentioned purpose is: a kind of board switchover circuit, by binding post respectively with this plate, plate is linked to each other with switching action mechanism, it comprises that this plate failure detector circuit, changeover signal initiate circuit, and it is characterized in that: described binding post comprises: the sub-StatFeedBack of activestandby state feedback output end, low-frequency pulse input terminal PulseIn, main output splicing ear/M_out, import splicing ear/S_In fully; Wherein the sub-StatFeedBack of activestandby state feedback output end links to each other with switching action mechanism; Low-frequency pulse input terminal PulseIn links to each other with a low-frequency pulse lead-out terminal on this plate, this low-frequency pulse is successively through this terminal of input after one or more function element that are positioned on this plate, have any one to work when undesired in these function element, this low frequency signal can not be delivered to this terminal smoothly; Main output splicing ear/M_out and import fully splicing ear/S_In respectively with importing splicing ear/S_In fully and leading output splicing ear/M_out and link to each other plate; Described plate failure detector circuit comprises capacitance C1, current rectifying and wave filtering circuit and electronic switch; Capacitance C1 is connected between the input of low-frequency pulse input terminal PulseIn and current rectifying and wave filtering circuit, and electronic switch is connected in the output and the changeover signal of current rectifying and wave filtering circuit and initiates between the circuit; Described changeover signal is initiated circuit and is comprised one or more gate circuits, its output is connected to the sub-StatFeedBack of activestandby state feedback output end and main output splicing ear/M_out, its final stage has a NAND gate U1D, the input of this NAND gate U1D also with import splicing ear/S_In fully and link to each other; Because of this plate master exports splicing ear/M_out and imports splicing ear/S_In fully and link to each other with main output splicing ear/M_out with the splicing ear/S_In that imports fully to plate respectively, make this plate changeover signal initiate circuit final stage NAND gate U1D and the plate changeover signal is initiated circuit final stage NAND gate formation interlock circuit.
The beneficial effects of the utility model: the first,, used isolation capacitance, utilized the detection signal of pulse signal, fault message is provided, guaranteed the isolation of this negater circuit and other circuit, be independent of each other as device in the plate owing to adopted above scheme.During use, can select to make this low frequency pulse signal successively through this circuit of input after one or more function element that are positioned on this plate.When low frequency signal on the path of process during any one or more function element fault, this low frequency signal can't arrive this circuit, this moment, circuit promptly was identified as fault, and then initiated to switch.Veneer or plate broken down often because " function element " fault wherein or the communication failure between " function element " cause in fact just can be undertaken by the fault of surveying these function element so survey single board default.(so-called herein " function element " is meant that CPU on the veneer, I/O chip, EPLD, FPGA programming device etc. finish the element of circuit function.) second, sort circuit design makes it to adopt the external discrete components and parts to constitute negater circuit, this has just been avoided negater circuit is made in the shortcoming that influenced by other devices in EPLD or the FPGA device, outside simultaneously device, because technology is very ripe, reliability also is can be guaranteed.Three, its changeover signal is finished by the discrete component circuit in this circuit, and switching does not need backstage or CPU to intervene, and finds like this that this single plate hardware is made mistakes or CPU just can switch when changeing dead immediately.
Fig. 1 is the utility model embodiment negater circuit principle schematic.
Fig. 2 is the connection diagram of the utility model negater circuit when a kind of occupation mode.
Fig. 3 is the connection diagram of the utility model negater circuit when another kind of occupation mode.
Also in conjunction with the accompanying drawings the utility model is described in further detail below by specific embodiment.
See Fig. 1, shown in be this routine board switchover circuit, respectively with this plate, plate is linked to each other with switching action mechanism, it comprises that this plate failure detector circuit, changeover signal initiate circuit by binding post.
Described binding post comprises: the sub-StatFeedBack of activestandby state feedback output end, low-frequency pulse input terminal PulseIn, main output splicing ear/M_out, import splicing ear/S_In fully.Wherein the sub-StatFeedBack of activestandby state feedback output end links to each other (when switching action mechanism receives this signal with switching action mechanism, can cause switching the switch running), this terminal is exported the activestandby state of this plate, because signal is taken from 11 pin of U1D, when so this terminal is output as low level, represent that this plate is main usefulness, the output high level represents that then this plate is standby.This terminal is isolated (as below stating) through R5, so can not influence the carrying out of switching.
Low-frequency pulse input terminal PulseIn links to each other with a low-frequency pulse lead-out terminal on this plate, this low-frequency pulse is successively through this terminal of input after one or more function element that are positioned on this plate, there is any one to work when undesired in these function element, this low frequency signal can not be delivered to this terminal smoothly, and at this moment this negater circuit is interpreted as veneer with it fault.This pulse is the key that circuit carries out hardware detection and auto switching.
Main output splicing ear/M_out and import fully splicing ear/S_In respectively with importing splicing ear/S_In fully and leading output splicing ear/M_out and link to each other plate./ M_out output low level then is that this plate master uses.The S_in input high level is that this plate master uses.Therefore the main board level is combined as
/ M_out=0 ,/S_In=1; The level of standby plate (slave board) is combined as
/M_out＝1，/S_In＝0。
It should be noted that in this example to also have a binding post CPUcontrl---CPU carries out control input end of switching.This is to establish (also can be set to compatible backstage control mode certainly) for compatible software (CPU) controls the usual manner of switching, when this plate is in main when using state, this CPU control terminal is incited somebody to action effectively, and by input low level, can be claimed by CPU makes this plate from leading with becoming stand-by state.At this moment as conventional switchover mode.
Described plate failure detector circuit comprises capacitance C1, current rectifying and wave filtering circuit and electronic switch; Capacitance C1 is connected between the input of low-frequency pulse input terminal PulseIn and current rectifying and wave filtering circuit, and electronic switch is connected in the output and the changeover signal of current rectifying and wave filtering circuit and initiates between the circuit.Described current rectifying and wave filtering circuit comprises rectifier diode D1, filter capacitor C2 and resistance R 1, and described electronic switch mainly is made up of triode Q1; Described rectifier diode D1 is the tandem type double diode, and its serial connection point links to each other the plus earth after the series connection with capacitance C1, negative electrode is by filter capacitor C2 ground connection, connect the base stage of triode Q1 by resistance R 1, the grounded emitter of triode Q1, collector electrode connects power Vcc by resistance R 2.
Produce the impulse commutation smoothing circuit with C1, C2, D1, R1, R2, Q1, the pulse of the 50HZ of C1 coupling input behind the rectifying and wave-filtering of D1, R1, C2, offers the base current of Q1, makes the Q1 conducting.In order to make Q1 can enter saturation condition, the value of R2 should be bigger, generally should satisfy following relation:
Ib
*B＞＞Icm
Wherein B is the dc amplification factor of Q1
Ib is a base current, and Icm is a collector saturation current.
Here should be understood that the employing of C1, C1 isolates every straightforward this switch unit circuit and other circuit of also making, only allow passing through of low-frequency ac pulse, other circuit are if a kind of DC level mode is added in capacitor, will be interpreted as no pulse by this negater circuit, thereby by this negater circuit generation auto switching.
Described changeover signal is initiated circuit and is comprised one or more gate circuits, its output is connected to the sub-StatFeedBack of activestandby state feedback output end and main output splicing ear/M_out, its final stage has a NAND gate U1D, the input of this NAND gate U1D also with import splicing ear/S_In fully and link to each other.Because of this plate master exports splicing ear/M_out and imports splicing ear/S_In fully and link to each other with main output splicing ear/M_out with the splicing ear/S_In that imports fully to plate respectively, make this plate changeover signal initiate circuit final stage NAND gate U1D, the plate changeover signal is initiated circuit final stage NAND gate formation interlock circuit.Described changeover signal is initiated circuit output end and is connected to the sub-StatFeedBack of activestandby state feedback output end by resistance R 5, be connected to main output splicing ear/M_out by resistance R 3, its final stage is NAND gate U1D, the input of this NAND gate U1D also with import fully that splicing ear/S_In links to each other and by resistance R 4 ground connection.
Specific to this example, for matching with Q1, it is a NAND gate U1A that described changeover signal is initiated the circuit first order.Carry out the sub-CPUcontrol in control input end that switches in order to introduce CPU, the gate circuit that described changeover signal is initiated in the circuit also comprises two NAND gate U1B, U1C.From controlling grade, CPUcontrl belongs to rudimentary control end, that is to say, if the PulesIn of negater circuit does not have the low-frequency pulse input, the Primary Component of expression veneer has damage or CPU to go wrong, to seal CPUcontrl this moment, utilize negater circuit of the present utility model to carry out auto switching; If the input of pulse is normal, show the working properly of CPU so, this moment, CPUcontrl just had the right to determine to switch.
U1A, U1B, U1C, U1D cascade successively.They link to each other with power Vcc by diode D2, and diode D2 anode connects power Vcc, and negative electrode connects the power input of NAND gate U1A, U1B, U1C, U1D.
As previously mentioned, U1D forms the R-S trigger with the NAND gate to plate, produces interlocking signal.Wherein the R3 string can be eliminated the burr that produces when inserting veneer at the output of U1D.Only from the element circuit of Fig. 1, when this negater circuit individualism, because R4 ground connection, 11 pin of U1D will be high level always, and the level of such two lead-out terminals is combined as :/M_out=1, and/S_In=0, this is a kind of slave board state.This benefit is the primal problem of robbing when solving charged insertion veneer.For analysis circuit, need in conjunction with and motherboard between relation, see Fig. 2.Among the figure, veneer A, one of board B are mainboard, binding post label on it be respectively StatFeedBack-1, PulseIn-1 ,/M_out-1 ,/S_In-1, CPUcontrol-1, another is a slave board, the binding post label on it be respectively StatFeedBack-2, PulseIn-2 ,/M_out-2 ,/S_In-2, CPUcontrol-2.
Fig. 2 /M_out and S_in are that active and standby plate is cross-coupled mutually, promptly/M_out-2 connects/S_In-1, and/M_out-1 connects/S_In-2, and every cross spider all has pull-up resistor Rp1, a Rp2 (going up termination Vcc), is made on the motherboard.When slave board will insert motherboard, normally contact pin does not touch socket, veneer provides power supply by the warm swap post, but since this moment slave board S_in to be inserted R4 ground connection, so this slave board keeps/M_out=1 always, S_in=0, like this, when just guaranteeing that the firm contact pin of slave board contacts, the level of butt joint terminal is that the level state when being in stable state with active and standby plate is consistent, therefore, this negater circuit can overcome other effectively and switches warm swap moment and may rob main problem.
This negater circuit also allows to be used to have only the situation of a veneer job, has represented the occupation mode of this negater circuit in veneer as Fig. 3.
If have only a veneer job, because pull-up resistor Rp1, the Rp2 of motherboard and the dividing potential drop of switch unit circuit R4, the branch pressure voltage point is selected in about V=2.8v, belong to high level, so/M_out will be high level, this means and having only the situation of this plate, will be changed to main board automatically.Certainly, if having only a veneer job, run into CPU or other critical elements just again and damage, circuit will be equally can make and oneself become slave board so since but device is bad, the meaning that becomes mainboard is also little, equally, become slave board and also can not cause what unnecessary loss.
Owing to introduced low-frequency pulse, can utilize it to carry out the part quality of other circuit or chip is detected.For example, if the low-frequency pulse that sends from CPU is that the main program by the board software program produces, pass through first, second and third programmable chip then, and by first and second I/O chip, so following situation all can auto switching:
*Cpu chip damages;
*The board software program fleet of CPU enters endless loop;
*The arbitrary damage of first, second and third programmable chip or do not load;
*The arbitrary damage of first and second I/O chip.
Therefore, utilize the vacant pin of this low-frequency pulse and chip circuit, just can play the function of automatic detection, be not subjected to the influence of other circuit, as long as the path that arbitrary low-frequency pulse passes through is obstructed, just can't transmit pulse signal, Q1 can not get base bias, be in cut-off state, 1,2 pin that is U1A is a high level, causes and switches, make this plate become slave board, plate is upgraded to mainboard.
Chip that it should be noted that the introducing low-frequency pulse all will be classified the object that this negater circuit is monitored as, and promptly the chip of all introducing low-frequency pulses all will cause switching when fault.So the introducing chip of low-frequency pulse must be critical, for nonessential chip, suggestion needn't be introduced, to avoid too frequent switching and unnecessary switching.
For the trouble isolation serviceability of this switch unit circuit, guarantee by following several respects:
1, negater circuit final stage, i.e. R-S interlock circuit must be selected the door chip of 74F series for use, and it keeps tens kilohms resistance after power down is arranged, and its prerequisite is that the VCC of a chip should have resistance greatly with GND;
2, the use of D2 is given gate circuit U1 power supply by D2 separately, and the protective tube that veneer occurs burns, and when promptly veneer does not have power supply online again,, almost can ignore to the filling electric current of this circuit with draw the electric current will be very little plate.In fact, D2 is exactly any prerequisite above guaranteeing.
Another reason that adopts 74F series is to improve the time of switching moment, and actual test shows stable switching time of the Ts＜10us of this circuit equally.In addition, provide two terminal CPUcontrl and StatFeedback and CPU to get in touch, made the CPU can be, or the order on backstage judges whether to carry out negater circuit according to the detected various information of this plate.
Use 74F series on a small scale IC do the negater circuit final stage, and be the power supply of negater circuit final stage with the isolation diode, the problem to plate " is dragged extremely " in meeting when solving outage.
3, a resistance of gating circuit is moved on to motherboard, other negater circuits may bring and rob main phenomenon when solving warm swap.
In sum, among the embodiment described above, its negater circuit will have following advantage:
*Hardware fault appearance automatic on-line heat is reliably switched;
*Independently circuit structure guarantees not to be subjected to the influence of other circuit or device;
*The programmable logic device of perception key more all sidedly, CPU, Primary Component faults such as interface chip, thereby auto switching;
*Can have trouble isolation serviceability, when promptly active and standby plate has one not have electricity (burning as protective tube in the veneer), can not influence the operate as normal of another veneer;
*Main situation can not appear robbing when guaranteeing warm swap;
*Guarantee to stablize switch speed in the microsecond level;
*Switch on compatible backstage, this plate software (passing through CPU) is switched control mode;
*Circuit simple in structure, the reliability height.
Claims (9)
1, a kind of board switchover circuit, respectively with this plate, plate is linked to each other with switching action mechanism, it comprises that this plate failure detector circuit, changeover signal initiate circuit, it is characterized in that by binding post:
Described binding post comprises: the sub-StatFeedBack of activestandby state feedback output end, low-frequency pulse input terminal PulseIn, main output splicing ear/M_out, import splicing ear/S_In fully; Wherein the sub-StatFeedBack of activestandby state feedback output end links to each other with switching action mechanism; Low-frequency pulse input terminal PulseIn links to each other with a low-frequency pulse lead-out terminal on this plate, this low-frequency pulse is successively through this terminal of input after one or more function element that are positioned on this plate, have any one to work when undesired in these function element, this low frequency signal can not be delivered to this terminal smoothly; Main output splicing ear/M_out and import fully splicing ear/S_In respectively with importing splicing ear/S_In fully and leading output splicing ear/M_out and link to each other plate;
Described plate failure detector circuit comprises capacitance C1, current rectifying and wave filtering circuit and electronic switch; Capacitance C1 is connected between the input of low-frequency pulse input terminal PulseIn and current rectifying and wave filtering circuit, and electronic switch is connected in the output and the changeover signal of current rectifying and wave filtering circuit and initiates between the circuit;
Described changeover signal is initiated circuit and is comprised one or more gate circuits, its output is connected to the sub-StatFeedBack of activestandby state feedback output end and main output splicing ear/M_out, its final stage has a NAND gate U1D, the input of this NAND gate U1D also with import splicing ear/S_In fully and link to each other; Because of this plate master exports splicing ear/M_out and imports splicing ear/S_In fully and link to each other with main output splicing ear/M_out with the splicing ear/S_In that imports fully to plate respectively, make this plate changeover signal initiate circuit final stage NAND gate U1D and the plate changeover signal is initiated circuit final stage NAND gate formation interlock circuit.
2, board switchover circuit as claimed in claim 1 is characterized in that: described current rectifying and wave filtering circuit comprises rectifier diode D1, filter capacitor C2 and resistance R 1, and described electronic switch mainly is made up of triode Q1; Described rectifier diode D1 is the tandem type double diode, its serial connection point links to each other with capacitance C1, plus earth after the series connection (GND), negative electrode is by filter capacitor C2 ground connection, and connect the base stage of triode Q1 by resistance R 1, the grounded emitter of triode Q1, collector electrode connects power Vcc by resistance R 2.
3, board switchover circuit as claimed in claim 1 or 2, it is characterized in that: comprise also in the circuit that CPU carries out the sub-CPUcontrol in control input end that switches, the gate circuit that described changeover signal is initiated in the circuit comprises four NAND gate U1A, U1B, U1C, the U1D of cascade successively, and wherein the input of second level NAND gate U1B links to each other with the sub-CPUcontrol in control input end that the CPU execution is switched.
4, board switchover circuit as claimed in claim 1 or 2, it is characterized in that: described changeover signal is initiated circuit output end and is connected to the sub-StatFeedBack of activestandby state feedback output end by resistance R 5, and be connected to main output splicing ear/M_out by resistance R 3, its final stage is NAND gate U1D, the input of this NAND gate U1D also with import fully that splicing ear/S_In links to each other and by resistance R 4 ground connection; Main output splicing ear/M_out with to after the importing splicing ear/S_In fully and link to each other on the plate, its tie point links to each other with the motherboard power supply by the pull-up resistor Rp1 on the motherboard; Import fully splicing ear/S_In with the main output splicing ear/M_out on the plate is linked to each other after, its tie point links to each other with the motherboard power supply by the pull-up resistor Rp2 on the motherboard.
5, board switchover circuit as claimed in claim 3, it is characterized in that: described changeover signal is initiated circuit output end and is connected to the sub-StatFeedBack of activestandby state feedback output end by resistance R 5, be connected to main output splicing ear/M_out by resistance R 3, the input of its final stage NAND gate U1D also with import fully that splicing ear/S_In links to each other and pass through resistance R 4 ground connection; Main output splicing ear/M_out with to after the importing splicing ear/S_In fully and link to each other on the plate, its tie point links to each other with the motherboard power supply by the pull-up resistor Rp1 on the motherboard; Import fully splicing ear/S_In with the main output splicing ear/M_out on the plate is linked to each other after, its tie point links to each other with the motherboard power supply by the pull-up resistor Rp2 on the motherboard.
6, board switchover circuit as claimed in claim 1 or 2 is characterized in that: described NAND gate U1D links to each other with power Vcc by diode D2, and diode D2 anode connects power Vcc, and negative electrode connects the power input of NAND gate U1D.
7, board switchover circuit as claimed in claim 3, it is characterized in that: described NAND gate U1A, U1B, U1C, U1D link to each other with power Vcc by diode D2, diode D2 anode connects power Vcc, and negative electrode connects the power input of NAND gate U1A, U1B, U1C, U1D.
8, board switchover circuit as claimed in claim 4, it is characterized in that: described NAND gate U1A, U1B, U1C, U1D link to each other with power Vcc by diode D2, diode D2 anode connects power Vcc, and negative electrode connects the power input of NAND gate U1A, U1B, U1C, U1D.
9, board switchover circuit as claimed in claim 5, it is characterized in that: described NAND gate U1A, U1B, U1C, U1D link to each other with power Vcc by diode D2, diode D2 anode connects power Vcc, and negative electrode connects the power input of NAND gate U1A, U1B, U1C, U1D.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 99245604 CN2398802Y (en) | 1999-09-21 | 1999-09-21 | One-board switching circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 99245604 CN2398802Y (en) | 1999-09-21 | 1999-09-21 | One-board switching circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2398802Y true CN2398802Y (en) | 2000-09-27 |
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ID=34031457
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 99245604 Expired - Lifetime CN2398802Y (en) | 1999-09-21 | 1999-09-21 | One-board switching circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2398802Y (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1299438C (en) * | 2002-11-02 | 2007-02-07 | 华为技术有限公司 | Method of realizing single plate main and ready change over and its circuit |
| CN101552709B (en) * | 2008-04-02 | 2012-05-23 | 中兴通讯股份有限公司 | Master and slave test groove collision detection method and circuit |
-
1999
- 1999-09-21 CN CN 99245604 patent/CN2398802Y/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1299438C (en) * | 2002-11-02 | 2007-02-07 | 华为技术有限公司 | Method of realizing single plate main and ready change over and its circuit |
| CN101552709B (en) * | 2008-04-02 | 2012-05-23 | 中兴通讯股份有限公司 | Master and slave test groove collision detection method and circuit |
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Free format text: CORRECT: PATENTEE; FROM: SHENZHEN HUAWEI TECHNOLOGY CO., LTD TO: HUAWEI TECHNOLOGY CO., LTD. |
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| CP01 | Change in the name or title of a patent holder |
Patentee after: Huawei Technologies Co., Ltd. Patentee before: Huawei Technology Co., Ltd., Shenzhen City |
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