CN2334063Y

CN2334063Y - One-chip computer and microcomputer simulation experiment instrument

Info

Publication number: CN2334063Y
Application number: CN98227888U
Authority: CN
Inventors: 陈菊华
Original assignee: Individual
Current assignee: Individual
Priority date: 1998-09-21
Filing date: 1998-09-21
Publication date: 1999-08-18
Anticipated expiration: 2008-09-21

Abstract

The utility model relates to a teaching experiment instrument, comprising a host machine and a CPT chip. The host machine is connected with a universal programmable I/O interface circuit; the data, the address bus, the chip select end, the read end, the writing end, the address latch signal end, the input and output port, the memory select end of the utility model are all connected with a bus socket. The input and output port is connected with a keyboard; the input and output line is connected with an ordinary display. The CPU card is composed of a central processor, a crystal oscillation, an internal bus driver, an external bus driver, an address latch, a programmable logic controller set, and a program memory, whose connecting ends are connected with the corresponding end of the bus socket.

Description

Single-chip microcomputer, microcomputer simulation experiment instrument

The utility model relates to a kind of teaching and experiment equipment, particularly a kind of instrument that is used to carry out single-chip microcomputer or Principles of Microcomputers teaching.

At present, when the student learns single-chip microcomputer or Principles of Microcomputers, need usually to finish with singlechip experiment apparatus and Microcomputer Experiments instrument respectively, function singleness can not be exchanged, and equipment investment is big, the cost height, use also inconvenience, and existing singlechip experiment apparatus or Microcomputer Experiments instrument only has the function of study, there is not the simulating developer function, make the user can only carry out the basic experiment of single-chip microcomputer or microcomputer, and can not carry out the simulating developer of single-chip microcomputer or microcomputer, bring significant limitation to the user.

The purpose of this utility model is exactly in order to address the above problem, just provide a kind of multiple functional, small investment, cost is low, easy to use and can provide the single-chip microcomputer of condition, microcomputer simulation experiment instrument for the user gives full play to exploitation.

Technical solution of the present utility model:

A kind of single-chip microcomputer, the microcomputer simulation experiment instrument, by main frame, the CPU card is formed, wherein main frame includes Timer IC1, serial line interface IC2, interruptable controller IC3, D/A converter IC4, A/D converter IC5, parallel IO interface IC6, program/data memory IC7, code translator IC8, Timer IC1 wherein, serial line interface IC2, interruptable controller IC3, D/A converter IC4, A/D converter IC5, parallel IO interface IC6, the data of program/data memory IC7, address bus connects together and is connected to bus socket IC9, IC1, IC2, IC3, IC4, IC5, IC6 reads, write end RD, WR connects together respectively and is connected to bus socket IC9, the sheet choosing end CS of IC1, control end, output terminal is connected to experiment socket Z1, the sheet choosing end CS of IC2 meets bus socket IC9, its serial is received, RXD makes a start, TXD is connected to experiment socket Z2, the sheet choosing end CS of IC3 and interrupt source input end IR0-7 are connected to experiment socket Z3, the sheet choosing end CS of IC4 and output terminal are connected to experiment socket Z5, the sheet choosing end CS of IC5, clock end CLK and analog quantity input end IN0-7 are connected to experiment socket Z7, the input/output port line PA of IC6, PB, PC is connected to experiment socket Z8, the input end of code translator IC8 also is connected to bus socket IC9 and links to each other with the public address bus, its another incoming line EXCS is connected to bus socket IC9, the output terminal of code translator IC8 is connected to experiment socket Z4, the memory read-write of IC7 is connected to bus socket IC9, bus socket IC9 is provided with experiment socket Z10, it is characterized in that main frame also is connected to general programmable I/O interface circuit IC11, its data, address bus is connected to bus socket IC9 and public data, address bus links to each other, its sheet choosing end CS, read, write end RD, WR, address latch signal end ALE and input/output port all link to each other with bus socket IC9 with memory selecting side IO/M, its input/output port line PA, PC meets keyboard M, and its input-output line PB meets common LED display N; The CPU card is by central processor CPU, crystal oscillator X, internal bus driver IC 12, external bus driver IC 13, address latch IC14, programmable logic controller (PLC) group IC15, memory under program IC16 forms, the data bus of CPU is connected to the public data line with bus socket IC9 by internal bus driver IC 12, be connected to simulated socket IC17 by external bus driver IC 13 simultaneously, and link to each other with the data line of memory under program IC16, the input/output port line I/O of central processor CPU meets bus socket IC9 and links to each other with experiment socket Z10, the address bus of central processor CPU directly meets simulated socket IC17, be connected to the address simultaneously and deposit lock device IC14, the output of address latch IC14 meets bus socket IC9 and links to each other with the public address bus, be connected to the input end of programmable logic controller (PLC) group IC15 simultaneously, also the address wire with memory under program IC16 links to each other, reading of central processor CPU, write end RD, WR, program gating end PSEN, input and output link to each other with the input end of programmable logic controller (PLC) group IC15 with memory selecting side IO/M, the multichannel output of IC15 is connected to bus socket IC9, read and write line MEMR with the memory of main frame respectively, MEMW, input and output read-write line IOR, IOW, the sheet choosing end IO1CS of general programmable I/O interface circuit IC11, the sheet choosing end IO2CS of parallel IO interface IC6, the sheet choosing end IO3CS of serial line interface IC2, input and output and memory selection wire IO/M, the sheet choosing end RAMCS of program/data memory IC7, code translator IC8 incoming line EXCS, the address latch line ALE of IC11 links to each other, wherein address latch line ALE also links to each other with the corresponding end of simulated socket IC17 and central processor CPU, and another part output of IC15 is connected to the read-write end RD of simulated socket IC17, WR and memory under program gating end PSEN.

The utility model adopts the CPU card to link to each other with the main frame grafting, main frame can be furnished with dissimilar singlechip CPU cards and microcomputer CPU card, so the utility model can be used for the theory teaching of single-chip microcomputer, also can carry out the Principles of Microcomputers teaching, has simultaneously the simulating developer function of single-chip microcomputer and microcomputer again, make emulation and experiment be dissolved in one, can reduce investment outlay, reduce cost, easy to use flexible, can provide the condition of bringing into play own explorative speciality to the user again simultaneously, be convenient to the user and carry out simulating developer, create the new product that some use single-chip microcomputer or microcomputer, have very big social benefit and economic benefit.

Fig. 1 is the main frame electrical schematic diagram of the utility model experiment instrument.

Fig. 2 is the CPU card electrical schematic diagram of the utility model experiment instrument.

Fig. 3 is a programmable logic controller (PLC) group embodiment electrical schematic diagram in the utility model CPU card.

Fig. 4 is another embodiment electrical schematic diagram of programmable logic controller (PLC) group in the utility model CPU card.

Fig. 5 is the another embodiment electrical schematic diagram of programmable logic controller (PLC) group in the utility model CPU card.

As Fig. 1～2, the utility model emulation experiment instrument is by main frame, the CPU card is formed, wherein main frame includes Timer IC1 (model can be 8253), serial line interface IC2 (model can be 8251), interruptable controller IC3 (model can be 8259), D/A converter IC4 (model can be 0832), A/D converter IC5 (model can be 0809), parallel IO interface IC6 (model can be 8255), program/data memory IC7 (model can be 62256), code translator IC8 (model can be 74LS138), Timer IC1 wherein, serial line interface IC2, interruptable controller IC3, D/A converter IC4, A/D converter IC5, parallel IO interface IC6, the data of program/data memory IC7, address bus connects together and is connected to bus socket IC9, IC1, IC2, IC3, IC4, IC5, IC6 reads, write end RD, WR connects together respectively and is connected to bus socket IC9, the sheet choosing end CS of IC1, control end, output terminal is connected to experiment socket Z1, the sheet choosing end CS of IC2 meets bus socket IC9, its serial is received, RXD makes a start, TXD is connected to experiment socket Z2, the sheet choosing end CS of IC3 and interrupt source input end IR0-7 are connected to experiment socket Z3, the sheet choosing end CS of IC4 and output terminal (by amplifier IC10) are connected to experiment socket Z5, the sheet choosing end CS of IC5, clock end CLK and analog quantity input end IN0-7 are connected to experiment socket Z7, the input/output port line PA of IC6, PB, PC is connected to experiment socket Z8, the input end of code translator IC8 also is connected to bus socket IC9 and links to each other with the public address bus, its another incoming line EXCS is connected to bus socket IC9, the output terminal of code translator IC8 is connected to experiment socket Z4, the memory read-write of IC7 is connected to bus socket IC9, bus socket IC9 is provided with experiment socket Z10, characteristics of the present utility model are, main frame also is connected to general programmable I/O interface circuit IC11 (model can be 8155), its data, address bus is connected to bus socket IC9 and public data, address bus links to each other, its sheet choosing end CS, read, write end RD, WR, address latch signal end ALE and input/output port all link to each other with bus socket IC9 with memory selecting side IO/M, its input/output port line PA, PC meets keyboard M, its input-output line PB meets common LED display N, and it has overcome the defective that existing 8088 Microcomputer Experiments systems can only make keyboard display with integrated package 8279.CPU card of the present utility model is by central processor CPU, crystal oscillator X, internal bus driver IC 12 (model can be 74LS245), external bus driver IC 13 (model can be 74LS245), address latch IC14 (model can be 74LS373), programmable logic controller (PLC) group IC15 (model can be GAL22V10), memory under program IC16 (EPROM) forms, the data bus of CPU is connected to the public data line with bus socket IC9 by internal bus driver IC 12, be connected to simulated socket IC17 (simulated socket and custom system connect) by external bus driver IC 13 simultaneously, and link to each other with the data line of memory under program IC16, the input/output port line I/O of central processor CPU meets bus socket IC9 and links to each other with experiment socket Z10, the address bus of central processor CPU directly meets simulated socket IC17, be connected to the address simultaneously and deposit lock device IC14, the output of address latch IC14 meets bus socket IC9 and links to each other with the public address bus, be connected to the input end of programmable logic controller (PLC) group IC15 simultaneously, also the address wire with memory under program IC16 links to each other, reading of central processor CPU, write end RD, WR, program gating end PSEN, input and output link to each other with the input end of programmable logic controller (PLC) group IC15 with memory selecting side IO/M, the multichannel output of IC15 is connected to bus socket IC9, read and write line MEMR with the memory of main frame respectively, MEMW, input and output read-write line IOR, IOW, the sheet choosing end IO1CS of general programmable I/O interface circuit IC11, the sheet choosing end IO2CS of parallel IO interface IC6, the sheet choosing end IO3CS of serial line interface IC2, input and output and memory selection wire IO/M, the sheet choosing end RAMCS of program/data memory IC7, code translator IC8 incoming line EXCS, the address latch line ALE of IC11 links to each other, wherein address latch line ALE also links to each other with the corresponding end of simulated socket IC17 and central processor CPU, and another part output of IC15 is connected to the read-write end RD of simulated socket IC17, WR and memory under program gating end PSEN.

In the utility model, the CPU card has three kinds, and a kind of is 88 microcomputers series CPU card, a kind of is 51 series monolithic CPU cards, and also having a kind of is 196 series monolithic CPU cards, for different CPU cards, their line construction is identical, and just the combination of its programmable logic controller (PLC) group IC15 is different.As for 88 microcomputers series CPU card, programmable logic controller (PLC) group IC15 is made up of programmable logic controller (PLC) G1, G2, G3 (model all can be GAL22V10), as shown in Figure 3.For 51 series monolithic CPU cards, IC15 is made up of programmable logic controller (PLC) G4, G5, G6, G7 (model all can be GAL22V10), as shown in Figure 4.For 196 series monolithic CPU cards, IC15 is made up of programmable logic controller (PLC) G8, G9, G10, G11 (model all can be GAL22V10), as shown in Figure 5.

In the utility model, also can be provided with stepper motor driving circuit, electronic audio driving circuit, direct current motor drive circuit on the main frame, their input end is connected to experiment socket Z11, Z9, Z6 separately respectively, and their output is connected with stepper motor, electronic audio, direct current generator respectively.

Also can connect a signal picker on the main frame of the present utility model, this collector is made up of pressure transducer, temperature sensor, signal amplification circuit and standard signal output plughole, the output of pressure transducer, temperature sensor links to each other with signal amplification circuit, and the output of signal amplification circuit connects the standard signal output plughole.During experiment, only need the standard signal output plughole is linked to each other with the experiment socket Z7 of A/D converter IC5, can under system software controls, carry out the experiments of measuring of temperature and pressure.

Microcomputer embodiment:

With stepper motor rotating speed control experiment is example, central processor CPU in the CPU card can be selected 8088 sixteen bit microcomputers for use at this moment, with the corresponding end of the experiment socket Z8 of parallel IO interface IC6 with went on foot motor experiment socket Z11 and linked to each other, the output pulse frequency of the microcomputer 8088 of CPU card input/output port line I/O of control IC6 under the in house software management, by Z11 control step rotating speed of motor and rotation direction, can observe the rotation direction and the speed of each stepper motor again by the display panel on the stepper motor.As if doing other experiment, during as experiments such as interruptable controller IC3, A/D converter IC5, only need experiment socket Z3, Z7 and control line and corresponding continuous the getting final product of switching value input, output terminal with them.

Single-chip microcomputer embodiment:

Be developed as example with 196 system emulations, central processor CPU in the CPU card should be selected 196 single-chip microcomputers for use at this moment, the simulated socket IC17 of CPU card is linked to each other with user 196 systems with artificial head by dedicated emulated cable, the user is the management software in the memory under program IC16 in the available CPU card, and keyboard M by main frame and universal display device N can carry out the simulating developer to custom system.

Claims

1, a kind of single-chip microcomputer, the microcomputer simulation experiment instrument, by main frame, the CPU card is formed, wherein main frame includes Timer IC1, serial line interface IC2, interruptable controller IC3, D/A converter IC4, A/D converter IC5, parallel IO interface IC6, program/data memory IC7, code translator IC8, Timer IC1 wherein, serial line interface IC2, interruptable controller IC3, D/A converter IC4, A/D converter IC5, parallel IO interface IC6, the data of program/data memory IC7, address bus connects together and is connected to bus socket IC9, IC1, IC2, IC3, IC4, IC5, IC6 reads, write end RD, WR connects together respectively and is connected to bus socket IC9, the sheet choosing end CS of IC1, control end, output terminal is connected to experiment socket Z1, the sheet choosing end CS of IC2 meets bus socket IC9, its serial is received, RXD makes a start, TXD is connected to experiment socket Z2, the sheet choosing end CS of IC3 and interrupt source input end IR0-7 are connected to experiment socket Z3, the sheet choosing end CS of IC4 and output terminal are connected to experiment socket Z5, the sheet choosing end CS of IC5, clock end CLK and analog quantity input end IN0-7 are connected to experiment socket Z7, the input/output port line PA of IC6, PB, PC is connected to experiment socket Z8, the input end of code translator IC8 also is connected to bus socket IC9 and links to each other with the public address bus, its another incoming line EXCS is connected to bus socket IC9, the output terminal of code translator IC8 is connected to experiment socket Z4, the memory read-write of IC7 is connected to bus socket IC9, bus socket IC9 is provided with experiment socket Z10, it is characterized in that main frame also is connected to general programmable I/O interface circuit IC11, its data, address bus is connected to bus socket IC9 and public data, address bus links to each other, its sheet choosing end CS, read, write end RD, WR, address latch signal end ALE and input/output port all link to each other with bus socket IC9 with memory selecting side IO/M, its input/output port line PA, PC meets keyboard M, and its input-output line PB meets common LED display N; The CPU card is by central processor CPU, crystal oscillator X, internal bus driver IC 12, external bus driver IC 13, address latch IC14, programmable logic controller (PLC) group IC15, memory under program IC16 forms, the data bus of CPU is connected to the public data line with bus socket IC9 by internal bus driver IC 12, be connected to simulated socket IC17 by external bus driver IC 13 simultaneously, and link to each other with the data line of memory under program IC16, the input/output port line I/O of central processor CPU meets bus socket IC9 and links to each other with experiment socket Z10, the address bus of central processor CPU directly meets simulated socket IC17, be connected to the address simultaneously and deposit lock device IC14, the output of address latch IC14 meets bus socket IC9 and links to each other with the public address bus, be connected to the input end of programmable logic controller (PLC) group IC15 simultaneously, also the address wire with memory under program IC16 links to each other, reading of central processor CPU, write end RD, WR, program gating end PSEN, input and output link to each other with the input end of programmable logic controller (PLC) group IC15 with memory selecting side IO/M, the multichannel output of IC15 is connected to bus socket IC9, read and write line MEMR with the memory of main frame respectively, MEMW, input and output read-write line IOR, IOW, the sheet choosing end IO1CS of general programmable I/O interface circuit IC11, the sheet choosing end IO2CS of parallel IO interface IC6, the sheet choosing end IO3CS of serial line interface IC2, input and output and memory selection wire IO/M, the sheet choosing end RAMCS of program/data memory IC7, code translator IC8 incoming line EXCS, the address latch line ALE of IC11 links to each other, wherein address latch line ALE also links to each other with the corresponding end of simulated socket IC17 and central processor CPU, and another part output of IC15 is connected to the read-write end RD of simulated socket IC17, WR and memory under program gating end PSEN.

2, single-chip microcomputer according to claim 1, the microcomputer simulation experiment instrument, it is characterized in that described CPU card has three kinds, a kind of is 88 microcomputers series CPU card, a kind of is 51 series monolithic CPU cards, also having a kind of is 196 series monolithic CPU cards, for different CPU cards, their line construction is identical, just the combination of its programmable logic controller (PLC) group IC15 is different, for 88 microcomputers series CPU card, programmable logic controller (PLC) group IC15 is by programmable logic controller (PLC) G1, G2, G3 forms, for 51 series monolithic CPU cards, IC15 is by programmable logic controller (PLC) G4, G5, G6, G7 forms, and for 196 series monolithic CPU cards, IC15 is by programmable logic controller (PLC) G8, G9, G10, G11 forms.

3, single-chip microcomputer according to claim 1, microcomputer simulation experiment instrument, it is characterized in that also can being provided with on the described main frame stepper motor driving circuit, electronic audio driving circuit, direct current motor drive circuit, their input end is connected to experiment socket Z11, Z9, Z6 separately respectively, and their output is connected with stepper motor, electronic audio, direct current generator respectively.

4, single-chip microcomputer according to claim 1, microcomputer simulation experiment instrument, it is characterized in that also can connecting a signal picker on the described main frame, this collector is made up of pressure transducer, temperature sensor, signal amplification circuit and standard signal output plughole, the output of pressure transducer, temperature sensor links to each other with signal amplification circuit, and the output of signal amplification circuit connects the standard signal output plughole.