CN2258327Y - High-resolution and broadband linear frequency-scanning signal resource - Google Patents
High-resolution and broadband linear frequency-scanning signal resource Download PDFInfo
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- CN2258327Y CN2258327Y CN 96214122 CN96214122U CN2258327Y CN 2258327 Y CN2258327 Y CN 2258327Y CN 96214122 CN96214122 CN 96214122 CN 96214122 U CN96214122 U CN 96214122U CN 2258327 Y CN2258327 Y CN 2258327Y
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Abstract
The utility model discloses a high-resolution and broadband linear frequency-scanning signal resource which belongs to the field of digital analog circuit technology, comprising a direct digital frequency synthesizer DDS, the signal processing circuit of the direct digital frequency synthesizer DDS, a frequency scanning digital generator FPGA for field programmable gate array, a master clock phase-locked loop and a frequency mixing phase-locked loop unit. The utility model adopts novel modularized elements with high integral rate and integrally uses the circuit technologies of digital, analog circuit and high low frequency, which causes the utility model to satisfy the indicators with high performance of high resolution, wide frequency band, low phase noise linearity, etc.; the utility model has the advantages of stable and reliable performance, small size and low cost.
Description
The utility model belongs to numeral, Analogical Circuit Technique field, particularly the circuit structure design technology of swept signal source.
The linear frequency sweep signal source is widely used in the time delay of test transmission system, the application of frequency-modulation radar and demanding various linear frequency sweep signal sources.
At present the general resolution of swept signal source is low, and linear poor, and for being had＜resolution of 1Hz, its circuit realization is very complicated.It also is extremely difficult simultaneously requiring fabulous sweep linearity in very wide frequency range.
The purpose of this utility model is to overcoming the weak point of prior art, circuit, structure to swept signal source are carried out new design, adopt novel integrated level height, modular device, comprehensive utilization, numeral, analog circuit and high and low frequency circuit engineering, make it not only satisfy a high performance index such as high-resolution, bandwidth, the low linearity of making an uproar mutually simultaneously, but also having stable and reliable for performancely, volume is little, the characteristics that cost is low.
The utility model is designed a kind of high-resolution, is hanged down and make an uproar mutually, the wide-band linearity swept signal source, it is characterized in that comprising Direct Digital Frequency Synthesizers DDS and signal processing circuit thereof, field programmable gate array frequency sweep data generator FPGA, each unit of master clock phase-locked loop of linking to each other with said DDS respectively; The input of said FPGA is clock and the control signal that is provided by normative reference source and industrial computer, and the binary-coded decimal of its output and frequency sweep clock are sent into said DDS; Said master clock phase-locked loop is that the signal in said normative reference source is sent into said DDS after frequency multiplication.
The utility model comprises that also the low frequency signal with said DDS and treatment circuit output is mixed to the mixing phase-locked loop of required high-frequency signal.Application demand with the high frequency band that meets the demands.Said master clock phase-locked loop can be by VCXO VCXO, and amplification and rectification circuit, bimodulus give the phase lock circuitry of frequency divider, phase discriminator, loop filter composition.Said DDS signal processing circuit can be made up of level shifting circuit, D/A converter, low pass filter and amplifier, and its input is connected in the output of DDS, and its output is connected in the input of said mixing phase-locked loop.
Said mixing phase-locked loop can be by voltage controlled oscillator VCO, power splitter, amplifier, mixing, amplifier, surface acoustic wave bandpass filter, the phase lock circuitry that amplification/shaping circuit, dual-mode frequency divider, phase discriminator loop filter are formed; Said phase discriminator links to each other with said 10MHz canonical reference source; Said loop filter is connected with one the tuning circuit that gives that gives accent terminal voltage Loading Control signal is provided; Said frequency mixer links to each other with the treatment circuit of said DDS; The output signal of said mixing phase-locked loop is exported by low pass filter by the output of said power splitter.
Operation principle of the present utility model is described below in conjunction with Fig. 1-4:
FPGA frequency sweep data generator unit as shown in Figure 1, the core devices of this unit is a field programmable gate array frequency sweep data generator and eprom memory, industrial computer to FPGA rate selection be provided, reset, initial, control signal such as stop, the normative reference source provides reference clock signal to FPGA; The core of FPGA is one and adds/subtract reversible binary-coded decimal counter that it is counted the reference clock pulse signal of input, obtains the binary-coded decimal and the frequency sweep clock of linear change, and input DDS Direct Digital Frequency Synthesizers under the control of industrial computer.
DDS master clock phase-locked loop as shown in Figure 2.The function of this element provides high stability for DDS, master clock signal through frequency multiplication, its principle is the signal of VCXO VCXO output to be sent into bimodulus give frequency divider after amplification, shaping, signal and normative reference source signal that bimodulus gives frequency divider output carry out phase demodulation at phase discriminator, produce error signal, obtain error voltage through loop filter again, this error voltage is controlled the output signal frequency locking of VCXO again, and sends into DDS.
DDS Direct Digital Frequency Synthesizers and signal processing circuit unit thereof are as shown in Figure 3.Its principle has a phase accumulator for DDS inside, carries out phase-accumulatedly when each main clock pulse signal arrives, and the cycle of overflowing of phase accumulator is by the bit frequency data setting of binary-coded decimal.Remove to look into a high speed ROM table again with phase accumulator and obtain the amplitude sign indicating number, DDS exports this amplitude sign indicating number, after TTL-ECL level conversion, D/A conversion, obtain sine wave signal, and then output after low pass smothing filtering, amplification, this output signal is than the linear swept-frequency signal of the high-resolution of low-frequency range.If need the signal of high band, then need on the basis of above-mentioned each element circuit, to add again a mixing phase-locked loop.
The mixing phase locked-loop unit as shown in Figure 4.Its principle is: the hunting range of voltage controlled oscillator is arranged on the scope that places the required high band of shoe lid, and when just powering up, the frequency of DDS output is in the low side of its frequency band, gives the low side that tuning circuit is tuned at VCO its frequency of oscillation automatically this moment.The output of VCO obtains the square wave of this frequency through surface acoustic wave bandpass filter filtering, amplification, the shaping of corresponding frequencies, the normative reference signal of sending into phase discriminator and normative reference source through the bimodulus frequency division carries out phase demodulation again, the error signal of phase discriminator output obtains error voltage through loop filter, the output frequency of this error voltage control locking VCO, when the output signal of DDS changed in its low-frequency band wide region, VCO output also changed in the high-band frequency range that sets.
The utlity model has following characteristics:
The first, adopting the new technology-DDS Direct Digital Frequency Synthesizers in frequency synthesis field is that core component makes this device have the resolution height, and the frequency inverted time is short, be convenient to advantage such as control with microprocessor;
The second, adopt frequency control part-FPGA frequency sweep data generator, have external interface simple, can produce the frequency data of high speed variation, under the constant situation of sweep rate, improved resolution, improved scanning linearity, and reliability height, cost are low;
The 3rd, adopt the mixing PHASE-LOCKED LOOP PLL TECHNIQUE with the bringing up to high band than low-frequency range and make most of device of device all can adopt the low frequency device of DDS output, reduced cost and the requirement of device has been enlarged range of application;
The 4th, this device most devices all adopts modularization, and highly integrated parts have improved the unfailing performance of complete machine, and makes making easily, and volume is little, and is in light weight.
Brief Description Of Drawings:
Fig. 1 is the utility model FPGA frequency sweep data generator unit theory diagram.
Fig. 2 is the utility model DDS master clock phase locked-loop unit theory diagram.
Fig. 3 is the utility model DDS Direct Digital Frequency Synthesizers and signal processing unit theory diagram thereof.
Fig. 4 is the utility model mixing phase locked-loop unit theory diagram.
Fig. 5 is a kind of embodiment general structure of the utility model schematic diagram.
Fig. 6 is the FPGA and the DDS circuit connecting relation figure of present embodiment.
Fig. 7 is the DDS output signal processing circuit schematic diagram of present embodiment.
Fig. 8 is the master clock phase-locked loop circuit schematic diagram of present embodiment.
Fig. 9 is the mixing phase-locked loop circuit schematic diagram of present embodiment.
Figure 10 is the structural configuration schematic diagram of present embodiment.
The utility model is designed a kind of high-resolution, wide-band linearity swept signal generator embodiment
The leading indicator that the present embodiment designing requirement should reach is as follows:
Operating frequency: 42.2MHz-70.2MHz, 40.2MHz-56.2MHz;
Resolution :≤1Hz
The corresponding 42.2MHz-70.2MHz of sweep speed: 100KHz/S
The corresponding 40.2MHz-56.2MHz of 50KHz/S
Phase noise: from carrier frequency 10KHz＜-90dBC/Hz
For reaching above-mentioned technical indicator, present embodiment is made up of frequency sweep data generator, DDS Direct Digital Frequency Synthesizers and signal processing circuit thereof, master clock phase-locked loop and mixing phase-locked loop four major parts, as shown in Figure 5, the each several part circuit theory is described in detail as follows respectively in conjunction with Fig. 6～Fig. 9:
The annexation of the FPGA frequency sweep data generator of present embodiment and DDS immediate data synthesizer as shown in Figure 6, the FPGA of present embodiment selects 4000 field programmable gate array U of XC3042DC84 of Xilinx company for use
12And configuration AT﹠amp; The ATT1765F Serial E of T company
2Prom memory.DDS selects the STEL-1176DDS chip U of U.S. Stanford Telecom company for use
114 I/D mouths 76.77 of FPGA, 78.79 the rate selection that receives industrial computer respectively that links to each other with industrial computer resets (ReSet), initial (Start), stop (Stop), add/subtract counting and select control signal, the normative reference source U of the 10MHz that constitutes by 3 amplifier 74AC04
14From the input of the I/O mouth of FPGA, 35 parallel data mouths of FPGA link to each other with 35 parallel data mouths of DDS, send into another I/O mouth 57 of FPGA among the DDS and DDS 10 mouthfuls and are connected to DDS and send into the frequency sweep clock signal changing 35 bit frequency data at a high speed.From the 80MHz master clock pulse signal of master clock phase-locked loop through U
15Insert the CLK mouth of DDS; The 10 bit amplitudes sign indicating numbers that DDS produces export its treatment circuit to by its delivery outlet out11～out2.
The DDS output signal processing unit of present embodiment as shown in Figure 7.The TTL-ECL level shifting circuit U that this list is made up of 3 MC10124
21, U
22, U
23, CX20202A-1 D/A conversion U24 and PLP-30 low pass filter U
25Constitute.U
21Be input as DDS output out8～out11, U
22Be input as DDS output out4～out7, U
22Be input as DDS output out2～out3, corresponding U
21, U
22, U
23Output DA8～DA11, DA4～DA7, DA2～DA3 is added to U
241～10 leg.U
2420 legs output connect the PLP-30 low pass filter.
The DDS master clock phase locked-loop unit of present embodiment as shown in Figure 8.
This unit is 8 frequency multiplication phase-locked loops, and 10MHz normative reference signal source and MC12013 bimodulus give frequency divider U
32Output signal is added to MC145152 phase discriminator U jointly
31Carry out phase demodulation, it produces error signal, and through the loop filter low-pass filtering that MC1458 formed, VCXO controls to VCXO, and then through sinusoidal waveform being shaped as the MC10116 amplification/shaping circuit of ECL level, its output is the input that bimodulus gives frequency divider.This loop is the phase-locked loop circuit of 80MHz.
By another road output of MC10116, be added to MC10136 and remove 2 circuit U simultaneously
33, the band pass filter of the 40MHz that forms by LC again, the signal of output 40MHz is (by S after amplifying
3Port), the output of the Third Road of MC10116 is through MAR series amplifier, at S
1The signal of end output 80MHz.S
1The end output signal is to be added to the FPGA frequency sweep data generator of present embodiment and the master clock input of DDS immediate data synthesizer.
The mixing phase locked-loop unit of present embodiment as shown in Figure 9.This unit is by MC145152 phase discriminator U
41Loop low pass filter, voltage controlled oscillator MC1648, power splitter PSC-2-1, amplifier SA3 and frequency mixer SBL-1, Surface Acoustic Wave Filter SAW (being added with MAR-3 and MAR-6 isolated amplifier in these filter input and output), amplification/shaping circuit MC10116 and bimodulus give frequency divider MC12013 and form the mixing phase-locked loop.
Be input as 2.2～30.2MHz signal that DDS exports at frequency mixer SBL-1, after mixing is phase-locked,,, amplify the required frequency 42.2MHz～70.2MHz signal of back output again through low pass filter PLP-90 filtering from the PSC-2-1 power splitter.
Voltage controlled oscillator MC1648 is arranged between 38.5～90MHz.Incoming frequency is 2.2MHz when just powering up, give tuning circuit with voltage controlled oscillator tuning about 42.2MHz.This is to finish V with photoelectric coupled device 4N25 and relay DS2Y-S-DC1
1For giving tuning voltage, by potentiometer P
2Fine setting control.
The present embodiment assembly structure as shown in figure 10, this device profile is 20 * 35 * 4 (cm
3) flat case 90, each element circuit parts all is fixed on the circuit substrate, each unit is isolated by barricade, three independently screen unit interconnect with shielded type cable.Wherein 91 is FPGA and DDS unit, and 92 is the master clock phase-locked loop, and 93 are the mixing phase-locked loop.
The side panel of box is equipped with several sockets 94, is used for input of 10MHz standard source and industrial computer, the interface of power supply and output signal, and whole device, compact conformation, easy to operate.
Claims (5)
1, a kind of high-resolution, low make an uproar mutually, the wide-band linearity swept signal source, it is characterized in that comprising Direct Digital Frequency Synthesizers DDS and signal processing circuit thereof, field programmable gate array frequency sweep data generator FPGA, each unit of master clock phase-locked loop of linking to each other with said DDS respectively; The input of said FPGA is clock and the control signal that is provided by normative reference source and industrial computer, and the binary-coded decimal of its output and frequency sweep clock are sent into said DDS; Said master clock phase-locked loop is that the signal in said normative reference source is sent into said DDS after frequency multiplication.
2, swept signal source as claimed in claim 1 is characterized in that also comprising that the low frequency signal with said DDS and treatment circuit output is mixed to the mixing phase-locked loop of required high-frequency signal.
3, signal source as claimed in claim 1 or 2 is characterized in that said master clock phase-locked loop by the VCXO VCXO, and amplification and rectification circuit, bimodulus give the phase lock circuitry of frequency divider, phase discriminator, loop filter composition.
4, swept signal source as claimed in claim 1 or 2, it is characterized in that said DDS signal processing circuit is made up of level shifting circuit, D/A converter, low pass filter and amplifier, its input is connected in the output of DDS, and its output is connected in the input of said mixing phase-locked loop.
5, swept signal source as claimed in claim 2, it is characterized in that said mixing phase-locked loop by VCO voltage controlled oscillator, power splitter, amplifier, mixing, amplifier, surface acoustic wave bandpass filter, the phase-locked loop circuit that amplification/shaping circuit, dual-mode frequency divider, phase discriminator loop filter are formed; Said phase discriminator links to each other with said canonical reference source; Said loop filter is connected with one the tuning circuit that gives that gives accent terminal voltage Loading Control signal is provided; Said frequency mixer links to each other with the treatment circuit of said DDS; The output signal of said mixing phase-locked loop is exported by low pass filter by the output of said power splitter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 96214122 CN2258327Y (en) | 1996-06-28 | 1996-06-28 | High-resolution and broadband linear frequency-scanning signal resource |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 96214122 CN2258327Y (en) | 1996-06-28 | 1996-06-28 | High-resolution and broadband linear frequency-scanning signal resource |
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| CN2258327Y true CN2258327Y (en) | 1997-07-23 |
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| CN 96214122 Expired - Fee Related CN2258327Y (en) | 1996-06-28 | 1996-06-28 | High-resolution and broadband linear frequency-scanning signal resource |
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| CN101826880A (en) * | 2010-03-23 | 2010-09-08 | 成都九洲迪飞科技有限责任公司 | Signal source module of air traffic alert and collision avoidance system receiver |
| CN101975878A (en) * | 2010-09-26 | 2011-02-16 | 厦门出入境检验检疫局检验检疫技术中心 | Bistable radiation comb signal source |
| CN102608370A (en) * | 2012-04-17 | 2012-07-25 | 江苏科技大学 | Control panel and method of FPGA (Field Programmable Gate Array) based program control standard source |
| CN102710267A (en) * | 2012-05-22 | 2012-10-03 | 成都九华圆通科技发展有限公司 | First local oscillation circuit of ultrashort wave receiver |
| CN103066485A (en) * | 2012-12-13 | 2013-04-24 | 乐普（北京）医疗器械股份有限公司 | Filter drive circuit of swept source |
| CN103208406A (en) * | 2013-04-02 | 2013-07-17 | 四川大学 | Artificial intelligent phase modulation injection locking continuous wave magnetron microwave source |
| CN101442632B (en) * | 2008-12-19 | 2014-02-12 | 康佳集团股份有限公司 | Method and apparatus for implementing sound accompaniment spectrum display on television screen |
| CN104320087A (en) * | 2014-10-13 | 2015-01-28 | 中国电子科技集团公司第四十一研究所 | High-speed digital frequency scanning method |
| CN105245226A (en) * | 2015-11-13 | 2016-01-13 | 成都前锋电子仪器有限责任公司 | Dot frequency generation circuit for radio-frequency local oscillation circuit of radio integrated measurement instrument |
| CN105897298A (en) * | 2016-06-03 | 2016-08-24 | 北京航空航天大学 | Multi-stage modular wireless transceiver experimental platform |
| CN106027042A (en) * | 2016-05-24 | 2016-10-12 | 贵州航天电子科技有限公司 | Digital noise interference source system |
| CN107222172A (en) * | 2017-05-19 | 2017-09-29 | 四川莱源科技有限公司 | A kind of Sweep Source of high RST output |
| CN107222171A (en) * | 2017-05-19 | 2017-09-29 | 四川莱源科技有限公司 | One kind is used for two-way swept-frequency signal speedy carding process two-way Sweep Source |
| CN107942296A (en) * | 2017-11-29 | 2018-04-20 | 北方通用电子集团有限公司 | A kind of ultra wide band swept-frequency signal generating means |
| CN110455403A (en) * | 2019-08-19 | 2019-11-15 | 哈尔滨工业大学 | A kind of frequency characteristic of SAW device continuously adjusts detection method and its detection system and generator |
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1996
- 1996-06-28 CN CN 96214122 patent/CN2258327Y/en not_active Expired - Fee Related
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| CN101826880A (en) * | 2010-03-23 | 2010-09-08 | 成都九洲迪飞科技有限责任公司 | Signal source module of air traffic alert and collision avoidance system receiver |
| CN101975878A (en) * | 2010-09-26 | 2011-02-16 | 厦门出入境检验检疫局检验检疫技术中心 | Bistable radiation comb signal source |
| CN101975878B (en) * | 2010-09-26 | 2012-11-14 | 厦门出入境检验检疫局检验检疫技术中心 | Bistable radiation comb signal source |
| CN102608370A (en) * | 2012-04-17 | 2012-07-25 | 江苏科技大学 | Control panel and method of FPGA (Field Programmable Gate Array) based program control standard source |
| CN102710267A (en) * | 2012-05-22 | 2012-10-03 | 成都九华圆通科技发展有限公司 | First local oscillation circuit of ultrashort wave receiver |
| CN103066485B (en) * | 2012-12-13 | 2015-03-25 | 乐普（北京）医疗器械股份有限公司 | Filter drive circuit of swept source |
| CN103066485A (en) * | 2012-12-13 | 2013-04-24 | 乐普（北京）医疗器械股份有限公司 | Filter drive circuit of swept source |
| CN103208406B (en) * | 2013-04-02 | 2015-08-19 | 四川大学 | A kind of artificial intelligence phase modulation injection locking continuous wave magnetron microwave source |
| CN103208406A (en) * | 2013-04-02 | 2013-07-17 | 四川大学 | Artificial intelligent phase modulation injection locking continuous wave magnetron microwave source |
| CN104320087A (en) * | 2014-10-13 | 2015-01-28 | 中国电子科技集团公司第四十一研究所 | High-speed digital frequency scanning method |
| CN104320087B (en) * | 2014-10-13 | 2017-05-24 | 中国电子科技集团公司第四十一研究所 | High-speed digital frequency scanning method |
| CN105245226A (en) * | 2015-11-13 | 2016-01-13 | 成都前锋电子仪器有限责任公司 | Dot frequency generation circuit for radio-frequency local oscillation circuit of radio integrated measurement instrument |
| CN106027042A (en) * | 2016-05-24 | 2016-10-12 | 贵州航天电子科技有限公司 | Digital noise interference source system |
| CN106027042B (en) * | 2016-05-24 | 2019-03-26 | 贵州航天电子科技有限公司 | A kind of Digital Noise interference source system |
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| CN107222172A (en) * | 2017-05-19 | 2017-09-29 | 四川莱源科技有限公司 | A kind of Sweep Source of high RST output |
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| CF01 | Termination of patent right due to non-payment of annual fee |