CN2223537Y - Synchronous timing device for communication circuit terminal - Google Patents

Synchronous timing device for communication circuit terminal Download PDF

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Publication number
CN2223537Y
CN2223537Y CN 94214159 CN94214159U CN2223537Y CN 2223537 Y CN2223537 Y CN 2223537Y CN 94214159 CN94214159 CN 94214159 CN 94214159 U CN94214159 U CN 94214159U CN 2223537 Y CN2223537 Y CN 2223537Y
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CN
China
Prior art keywords
circuit
output
inputs
equipment
schmidt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN 94214159
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Chinese (zh)
Inventor
贾俊贤
鲍家元
金文雄
李平均
戴年华
姜晓宁
李长河
阚凤云
王彬
阎峥
才洪恩
薛宏伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute Of Management Information Systems Xi'an Jiao Tong University
WEIHUA COMMUNICATION TECHN INST WEINAN SHAANXI PROV
Telephone Exchange Public Telegraph Exchange Technical Maintenance Support Center
Original Assignee
Institute Of Management Information Systems Xi'an Jiao Tong University
WEIHUA COMMUNICATION TECHN INST WEINAN SHAANXI PROV
Telephone Exchange Public Telegraph Exchange Technical Maintenance Support Center
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Institute Of Management Information Systems Xi'an Jiao Tong University, WEIHUA COMMUNICATION TECHN INST WEINAN SHAANXI PROV, Telephone Exchange Public Telegraph Exchange Technical Maintenance Support Center filed Critical Institute Of Management Information Systems Xi'an Jiao Tong University
Priority to CN 94214159 priority Critical patent/CN2223537Y/en
Application granted granted Critical
Publication of CN2223537Y publication Critical patent/CN2223537Y/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

The utility model discloses a synchronous timing device for a communication line terminal, which is a synchronous timing device working for a communication line terminal. The utility model is composed of a synchronous counter, a selector, an NOR element circuit, and a Schmidt NAND element circuit. Base group velocity signals and U interface ST bus signals can realize synchronous timing work to achieve the function that base group digital channels can be tapped, multipled, and extended to users' terminal for a long distance. Because of a synchronous timer whose public known equipment is simplified, the defects of multiple transform of A / D (D / A) and the connection need of a simulation mode are avoided, and thus digital signal transmission speed increases up to 64Kbit/S above, achieving the goal of complete digitized communication network.

Description

Communication line terminal synchronization timing device
The utility model relates to digital transmission unit, refers more particularly to communication line terminal synchronization timing device.
In the telecommunications network there be known similar devices at present: the basic group multiplex equipment PCM TDLC 2MBit/S that Chongqing communication equipment factory of the Ministry of Posts and Telecommunications produces; 60 road 0+4 digital loop carrier systems and DYNA CARD DM2 primary group multiplexing equipment series that Weifang China transmission equipment branch company of photoelectron (group) limited company produces; The DPN of Northern Telecom-100 packet switch; The GW that China Greatwall Computer Group Co Ltd produces-OA51N1 five in one office communication system etc., its common trait is:
1, as at the communication multiplexing equipment that transmits on the copper cabling below the primary rate (2Mbit/s), do not possess the function that directly digital signal is extended at a distance user's end.Generally all will be through twice A/D (D/A) conversion at local side.As PCM 2Mbit/s, 0+4 digital loop carrier system, DYNA CARD DM2 primary group multiplexing equipment series etc.As telephone channel, they have increased equipment investment, and as digital channel, then must add modulator-demodulator (MODEM) in addition, this further increases cost, can not make full use of the 64Kbit/s in PCM and the u interface) potentiality of digital rate, if be transmitting digital information in the linear light fibre, utilize the said equipment must form bigger waste.
2, be implemented on the copper cabling transmission 64Kbit/s digital rate digital information and need rent private wire circuit (two pairs of simple lay zygonemas are also wanted in the transmission of four lines).At this moment, only be applicable to Packet Service, can not utilize the circuit-switching function of existing digital telephone network, as DPN-100 PSE, it has influenced flexibility and economy that Packet Service inserts, uses to the user and has also brought inconvenience.
3, can realize the terminal of integrated services communication, but make its aggreggate utility not obvious, as GW-OA51N1 five in one office communication system because of transmission rate is too low.
The common defects of above-mentioned known equipment is that the digital device that works in primary rate contains independently synchro timer separately with the digital device that adopts the u interface technology, when forming communication network is by repeatedly A/D (D/A) conversion, connect in the analog interface mode, thereby the speed of transmitting digital signals is limited in below the 2400bit/s.
The purpose of the utility model communication line terminal synchronization timing device is to overcome the shortcoming of above-mentioned existing known equipment, and adopts a kind of device that makes primary rate signal and u interface ST bus signals realize synchronization timing.Realized direct tap with the basic group digital channel, multiplexing and extend to the function of user's end at a distance.It has not only simplified the synchro timer of above-mentioned existing known equipment, repeatedly A/D (D/A) conversion and the drawback that must be connected in the analog interface mode have been avoided, thereby the speed that makes transmitting digital signals is brought up to more than the 64Kbit/s, has reached the digitized purpose of communication network.
The utility model communication line terminal synchronization timing device for achieving the above object, its technical scheme is as follows: the synchronization timing device of communication line terminal is made of coincidence counter, selector OR-NOT circuit and four parts of Schmidt's NAND gate circuit.
A kind of communication line terminal synchronization timing device is characterized in that comprising:
A coincidence counter, its input links to each other with the output of group bank equipment master clock after the shaping of Schmidt's NAND gate circuit, the two divided-frequency end of its output and four frequency division ends link to each other with two inputs of another Schmidt's NAND gate, eight frequency division ends of its output and 16 end frequently link to each other with the input of selector, thereby have realized the synchronous of this device and group bank equipment master clock;
A selector, except above-mentioned two inputs with corresponding two outputs of coincidence counter link to each other, two other input is connected to two positive and negative field pulses of group bank equipment, its output is divided into two groups, every group each four and respectively eight inputs of AND circuit link to each other, reach the function that makes this device and the timing of group bank equipment frame;
OR-NOT circuit except above-mentioned eight inputs with corresponding eight outputs of selector link to each other, totally three inputs of the OR-NOT circuit of corresponding negative field pulse is connected in parallel and is connected to a time-gap pulsing of basic group multiplex equipment, another input is connected to previous time-gap pulsing, and the OR-NOT circuit of corresponding positive field pulse totally four inputs be connected in parallel, be connected to a back time-gap pulsing of basic group multiplex equipment, they all to time-gap pulsing and frame commutator pulse be split into " with " relation, and make eight outputs become the enabling pulse of adaptive coding/decoding device, wherein the 3rd also is specific enabling pulse;
Schmidt's NAND gate circuit such as above-mentioned when playing to the basic group master towards the signal shaping effect, another Schmidt's NAND gate circuit is except three inputs are connected to the 4th output of two outputs of respective synchronization counter and OR-NOT circuit respectively, also have an input to be connected to output after the shaping of aforementioned Schmidt's NAND gate, its output just forms the frame-synchronizing impulse of u interface ST bus like this.
The required master clock of ST bus is directly obtained by group bank equipment.
Coincidence counter is counted synchronously to the clock of group bank equipment, is controlled the output of selector again by two output, thereby reaches the purpose synchronous with the group bank equipment master clock.Selector is then selected two groups output up and down by the field pulse of group bank equipment, reaches frame purpose regularly.OR-NOT circuit receives the output of selector negative pulse and group bank equipment clock negative pulse form " with " relation, and make its output become the enabling pulse of adaptive coding/decoding device (ADPCM).Schmidt's NAND gate circuit carries out sending into coincidence counter after the shaping to the basic group clock signal on the one hand, on the other hand again the ST bus clock signal, two output end signals of coincidence counter and specific enable signal phase NAND are as the frame-synchronizing impulse of u interface ST bus, and the master clock of ST bus is directly obtained by group bank equipment.Therefore, communication line terminal synchronization timing device has played the effect that u interface and ADPCM and group bank equipment are directly linked to each other, and the purpose when having reached fully synchronously.
Compared with the prior art the utility model has following characteristics:
Can be with 2,048Mbit/s digroup signal directly is switched to user's end, has saved a cover synchro timer, has simplified equipment.Each means of subsistence can realize on a pair of simple lay zygonema of voice-frequency cable that the sound alive of 0+4 is multiplexing along separate routes.This provides equipment from the lossless relaying of four lines to the in-dialling private automatic branch exchange switch that realize just for C4, C5, Tm office with basic group interface (E1).It has not only increased system reliability (comparing with analog junction), and has reduced track investment.Therefore, subsection PABX and the PABX of rural area village community that the utility model is specially adapted to outlying dispersion realize golden digitized requirement, also provide equipment of high quality and at a reasonable price for telecommunication department at vast rural development main line subscriber.When not adopting ADPCM, can obtain the full duplex digital circuit of two 64Kbit/s (2B) at user side.And need not to increase any modulator-demodulator (MODEM), and avoided repeatedly A/D (D/A) conversion, improved the speed of transmitting digital signals.
The synchronization timing device accompanying drawing of the utility model communication line terminal is as follows:
Fig. 1: communication line terminal synchronization timing device sequence circuit
Fig. 2: communication line terminal synchronization timing device sequential chart
Below in conjunction with the embodiment accompanying drawing this utility model is further elaborated.
Communication line terminal synchronization timing device is made of coincidence counter U1, selector U2, OR-NOT circuit U3, U4 and Schmidt's NAND gate circuit U5.The synchronised clock CKT (the 4096KHZ two divided-frequency is 2048KHZ) that is come by group bank equipment (E1) uses rising edge triggering synchronous counter U1 after U5:B is anti-phase, its eight frequency division output Q2 and 16 frequency divisions output Q3 are used for selector U2 is selected, to determine which end may be exported in 0-3.And then determine that U2 is the upper or half of down output field pulse ET, ET-(, containing the frame synchronization locating information) also from group bank equipment (E1).Use time-gap pulsing Ф Tn again from group bank equipment (E1), n+16, Ф Tn+1, n+17 controls NOR gate, because of these time-gap pulsings not only contain gap information along separate routes, and real be negative pulse, thereby form jointly with the reverse output signal of U2 " with " relation, export from TS1-TS8 more at last and use for the ADPCM enable signal.
Introduce the second time-gap pulsing Ф Tn-1 of last shunt at U3 (11) end, n+15, like this TS ' 4 output be the 4th enable signal (specific enable signal) of the last shunt of reflection, it with Q0, the Q1 of U1 and CKT again in U5:A mutually " with " obtain the frame-synchronizing impulse of ST bus.Arrange like this, purpose is to guarantee that the u interface circuit is after frame pulse starts (Fob-), the 4th code element rising edge of clock pulse (C4b-) can be locked u interface equipment to all data, and can be this requirement of data output at the first code element trailing edge, and the scope of a broad is arranged.
ADPCM adopts the compression of 32Kbit/s channel, and therefore a PCM time slot can be opened two ADPCM speech circuits (to U mouth 0+4 function).After adopting the utility model, it has strict corresponding relationship each other.Use Chn, Chn+1, Chn+16, Chn+17 represent the corresponding time slot of PCM.Wherein N is 0-14 arbitrary integer.Use B11, B12, B12, B22 represent the ADPCM sound circuit, respectively account for 1/4th of 2B in the u interface channel.
Each time slot is made the relation of enable signal and is seen attached list
By table as seen Chn, Chn+1 time slot in pcm bus, corresponding A DPCM bus (ST-B21 BUS), B22 time slot, and Chh+16, Chn+17 time slot, corresponding B11, B12 time slot.
Obviously change the different corresponding relations of enable signal TS1-TS8 and ADPCM, can also realize the time gas exchange of different transmission directions, this performance can realize by microprocessor software.Thereby further can realize the incorporate function of transmission exchange.
The ADPCM Enable Pin is used time slot table (subordinate list)
Direction Enable Pin Chn/B22 CHn+1/B22 CHn+6/B11 CHn+17/B22
PCM ↓ ADPCM EIE TS1 TS3 TS5 TS7
EOE TS5 TS6 TS1 TS2
ADPCM ↓ PCM DIE TS5 TS6 TS1 TS2
DOE TS1 TS3 TS5 TS7

Claims (1)

  1. A kind of communication line terminal synchronization timing device is characterized in that comprising:
    A coincidence counter, its input links to each other with the output of group bank equipment master clock after the shaping of Schmidt's NAND gate circuit, the two divided-frequency end of its output and four frequency division ends link to each other with two inputs of another Schmidt's NAND gate, eight frequency division ends of its output and 16 end frequently link to each other with the input of selector, thereby have realized the synchronous of this device and group bank equipment master clock;
    A selector, except above-mentioned two inputs with corresponding two outputs of coincidence counter link to each other, two other input is connected to two positive and negative field pulses of group bank equipment, its output is divided into two groups, every group each four and respectively eight inputs of AND circuit link to each other, reach the function that makes this device and the timing of group bank equipment frame;
    OR-NOT circuit except above-mentioned eight inputs with corresponding eight outputs of selector link to each other, totally three inputs of the OR-NOT circuit of corresponding negative field pulse is connected in parallel and is connected to a time-gap pulsing of basic group multiplex equipment, another input is connected to previous time-gap pulsing, and the OR-NOT circuit of corresponding positive field pulse totally four inputs be connected in parallel, be connected to a back time-gap pulsing of basic group multiplex equipment, they all to time-gap pulsing and frame commutator pulse be split into " with " relation, and make eight outputs become the enabling pulse of adaptive coding/decoding device, wherein the 3rd also is specific enabling pulse;
    Schmidt's NAND gate circuit such as above-mentioned when playing to the basic group master towards the signal shaping effect, another Schmidt's NAND gate circuit is except three inputs are connected to the 4th output of two outputs of respective synchronization counter and OR-NOT circuit respectively, also have an input to be connected to output after the shaping of aforementioned Schmidt's NAND gate, its output just forms the frame-synchronizing impulse of u interface ST bus like this;
    The required master clock of ST bus is directly obtained by group bank equipment.
CN 94214159 1994-06-18 1994-06-18 Synchronous timing device for communication circuit terminal Expired - Fee Related CN2223537Y (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 94214159 CN2223537Y (en) 1994-06-18 1994-06-18 Synchronous timing device for communication circuit terminal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 94214159 CN2223537Y (en) 1994-06-18 1994-06-18 Synchronous timing device for communication circuit terminal

Publications (1)

Publication Number Publication Date
CN2223537Y true CN2223537Y (en) 1996-03-27

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN 94214159 Expired - Fee Related CN2223537Y (en) 1994-06-18 1994-06-18 Synchronous timing device for communication circuit terminal

Country Status (1)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100392542C (en) * 2003-05-29 2008-06-04 株式会社日立制作所 Communication control device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100392542C (en) * 2003-05-29 2008-06-04 株式会社日立制作所 Communication control device

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