CN2430817Y - Variable bandwidth digital loop carrier equipment - Google Patents

Variable bandwidth digital loop carrier equipment Download PDF

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Publication number
CN2430817Y
CN2430817Y CN 00226507 CN00226507U CN2430817Y CN 2430817 Y CN2430817 Y CN 2430817Y CN 00226507 CN00226507 CN 00226507 CN 00226507 U CN00226507 U CN 00226507U CN 2430817 Y CN2430817 Y CN 2430817Y
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CN
China
Prior art keywords
bus
clock
data
digital loop
loop carrier
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN 00226507
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Chinese (zh)
Inventor
邱燕炜
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Xian Jiaotong University
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Xian Jiaotong University
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Publication date
Application filed by Xian Jiaotong University filed Critical Xian Jiaotong University
Priority to CN 00226507 priority Critical patent/CN2430817Y/en
Application granted granted Critical
Publication of CN2430817Y publication Critical patent/CN2430817Y/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

The utility model discloses a variable bandwidth type digital loop carrier equipment. The utility model comprises a back board and a plurality of single boards connected with the back board in an inserting way. The back board adopts a bus mode, and comprises at least a data carrying bus which is used for transporting data streams and a control bus which is used for coordinating the running of each single board, at least one single board of the single boards is provided with an output frequency adjustable clock generating circuit which is used for providing a clock to the data carrying bus on the back board, the bandwidth of the data carrying bus can be changed by changing the frequency of the clock, so the equipment can satisfy the different requirements of a local end and a far end toward bandwidth at the same time, and the wastage or the deficiency of bandwidth is not caused.

Description

Variable bandwidth formula digital loop carrier equipment
The utility model relates to communication equipment, is a kind of user access networks equipment, specifically a kind of digital loop carrier equipment of backboard carrying adaptive-bandwidth.
Digital loop carrier DLC equipment is the access network equipment between network node and the subscriber terminal equipment, be mainly used in the telecommunication service of supporting the following speed of 2Mbit/s, as: plain old telephone service POTS, integrated services digital network ISDN business, Digital Data Net DDN business etc.Digital loop carrier equipment has the branch of local side apparatus and remote equipment, and local side apparatus is mainly used in provides network management interface and miscellaneous service node interface, and remote equipment is used to provide various user interfaces.
Local side apparatus generally links to each other with several far-end equipment by optical line terminal, all business that insert on the remote equipment all need be carried out processing such as multiplexing and demultiplexing and interconnection on local side apparatus, like this, processing speed that local side apparatus is required and Gbps all will be higher than remote equipment far away, and this makes local side apparatus and remote equipment be difficult to adopt identical backboard.
Existing digital loop carrier equipment is at local side and the different backboard of the general employing of far-end, and the veneer major part that local side apparatus and remote equipment adopted can not be exchanged, thereby the veneer kind is many, and maintenance difficulties is big, and structural integrity is poor.Some digital loop carrier equipment makes local side apparatus can adopt identical backboard with remote equipment by the following method: one of method is to reduce the Gbps of local side apparatus, make it identical with remote equipment, the problem that this method exists is that the capacity of equipment is little, and range of application is restricted; Two of method is to improve the Gbps of remote equipment, makes it identical with local side apparatus, and the problem that this method exists is that the Gbps waste of remote equipment is serious, causes cost height, the power consumption height of equipment.
The purpose of this utility model is to overcome the existing shortcoming of above-mentioned existing equipment, provides a kind of and not only can be common to local side and far-end but also not cause Gbps waste or not enough variable bandwidth formula digital loop carrier equipment.
The utility model comprises backboard and the some veneers that link to each other with backboard with plugging mode.Backboard adopts bus mode, comprises that at least one is used for Data-carrying bus and control bus that is used to coordinate each veneer operation of transmitting data stream.Have at least a veneer to dispose the adjustable clock generation circuit of output frequency in the described some veneers, the Data-carrying bus that is used on the toward back plate provides clock, the frequency that changes this clock can change the Data-carrying bus width, and the veneer that links to each other with the Data-carrying bus has adaptive capacity to the frequency change of this clock.Like this, when as local side apparatus, can make backboard work in high bandwidth, and during as remote equipment, then can make backboard work in low bandwidth, thereby equipment both can satisfy local side and the different requirements of far-end to bandwidth simultaneously, not cause the waste or the deficiency of bandwidth again.
Below in conjunction with drawings and Examples the utility model is elaborated:
Fig. 1 is a composition frame chart of the present utility model.
Fig. 2 is the annexation figure between each veneer of the utility model.
Fig. 3 is the block diagram of the utility model master control borad.
Fig. 4 is the electrical schematic diagram of the utility model clock regulating circuit.
Fig. 5 is the utility model Analog Subscriber Line Board block diagram.
Fig. 6 is the electrical schematic diagram of the utility model Analog Subscriber Line Board coding-decoding circuit.
Referring to Fig. 1 and Fig. 2, the utility model comprises backboard 1 and the some veneers 2 that link to each other with backboard 1 with plugging mode.Backboard 1 adopts bus mode, comprises Data-carrying bus 6, control bus 7, test bus 11 and power supply ringing-current bus 12; Veneer 2 comprises master control borad 3, power supply ringing-current plate 4 and various interface plate 5.On mechanical structure, in the sub-frame of standard that backboard 1 and veneer 2 stuck-at-s are 9 inches, the antithetical phrase frame superposes the capacity of equipment is smoothly expanded.
Data-carrying bus 7 adopts the time division multiplexing tdm bus, form by clock line 9, line synchro 10 and some data wires 8, be used for transport stream through the data flow of backboard and the message flow that is embedded in data flow, the quantity of data wire 8 is decided by the bandwidth that backboard is required, generally can choose in 1~16 scope, every data wire 8 all comprises receives and sends out both direction; Control bus 7 adopts single-chip microcomputer MCS51 serial ports form and TTL interface level, be used to coordinate the operation between each veneer, other each veneer is configured, inquires about and manages by control bus 7 such as master control borad 3, for dominant frequency is the MCS51 single-chip microcomputer of 12MHz and 24MHz, the desirable 375K of its baud rate; Test bus 11 adopts the two wires mode, be mainly used in the routine test of CCS casual clearing station subscriber line test and equipment itself, comprise to the test of public switch telephone network PSTN with to the test of integrated services digital network ISDN, also can be used for the circuit test and loop line test of various digital junctions and analog junction; Power supply ringing-current bus 12 is used to transmit ringing-current and various power supply, as+5V ,-5V ,-48V etc.
Master control borad 3 is used for other each veneer is controlled, and it disposes network management interface a, can join with webmaster terminal or Telecommunication Management Network, makes entire equipment can be subjected to the unified management of network management system; Master control borad 3 also disposes the adjustable clock generation circuit of output frequency, and being used for toward back plate provides Data-carrying bus 6 required clock; Power supply ringing-current plate 4 provides ringing signal and various power supply by power supply ringing-current bus 12 to other each veneer; Interface board 5 comprises Analog Subscriber Line Board, digital subscriber board, analog junction plate, Digital Trunk Board, Leased line interface board and V5 interface board etc., be used to provide various User Network Interfaces and SNI, insert BRA interface and primary rate as audio frequency simulation Z interface, basic rate isdn and insert PRA interface, the professional DDN speed of Leased line and insert V.24 that interface and N * 64kbit/s insert V.35 interface, digital junction E1 interface, standardized V5.1 interface and V5.2 interface etc. synchronously.
Referring to Fig. 3, master control borad 3 comprises central processing unit 13, switching network 14 and clock generation circuit 15.The control that central processing unit 13 is realized other each veneer by control bus 7; Switching network 14 is used for data flow on the data carrying bus 6 is exchanged; Clock generation circuit 15 is used for providing clock to Data-carrying bus 6, be made up of clock generator 16 and clock regulating circuit 17, the difference of employed clock generation circuit has been to increase the clock regulating circuit 17 that is subjected to central processing unit 13 controls in it and the existing digital loop carrier equipment; Central processing unit 13 disposes network management interface a, can control the clock frequency of clock regulating circuit 17 outputs according to the assignation information from network management interface a.
Referring to Fig. 4, clock regulating circuit 17 is that N2a, N2b~N5a, N5b are formed by frequency dividing circuit N2~N5, the frequency of the clock b of clock generator 16 outputs is 16.384MHz, produces 8.192MHz and two kinds of frequencies of 4.096MHz that behind frequency dividing circuit N2~N5 frequency division two four select a circuit N1 to select a kind of clock line 9 and line synchro 10 of exporting under the control of central processing unit 13 control mouthful c from three kinds of clock frequencies.
Obtain stable clock by frequency division from clock line 9 for the ease of each interface board 5, half of the frequency of the data rate employing clock line 9 of data wire 8.Like this, if Data-carrying bus 6 includes n bar data wire 8, then its bandwidth can reach n * 8.192M, n * 4.096M and n * 2.048M respectively corresponding to clock frequency 16.384MHz, 8.192MHz and 4.096MHz.For the situation of n=16, its high bandwidth can reach 131.072M.
The variation of the bandwidth of 5 pairs of data carryings of each interface board bus 6 has adaptive capacity.With the Analog Subscriber Line Board is example, referring to Fig. 5 and Fig. 6, this plate is made up of coding-decoding circuit 18 and user interface circuit 19, user interface circuit 19 is used for providing standardized audio frequency simulation Z interface e to the user, coding-decoding circuit 18 is used to realize the conversion between analog signal and the digital signal, makes the voice signal of simulation to transmit on digitized data wire 8.Coding-decoding circuit 18 comprises MCS51 single-chip microcomputer N6, codec chip N7, clock division circuits N8, N12 and N9b, data transmit-receive buffer N13 and N14, control mouthful buffer circuit N11, watchdog circuit N10 etc.Codec chip N7 provides one group of interface k that can connect four road user interface circuits 19, and can work in 2.048Mbit/s, 4.096Mbit/s and three kinds of data rates of 8.192Mbit/s under the control of single-chip microcomputer N6.When the frequency of clock line 9 changes, master control borad 3 will be notified each interface board 5 by control bus 7.Single-chip microcomputer N6 reinitializes codec chip N7 after receiving this message from control mouth 7 at once, makes it work in new clock frequency.All required maximum bandwidths of Analog Subscriber Line Boards while are no more than 8.192Mbit/s in the sub-frame, so this veneer has only used a data wire 8, it comprises receives and send out both direction.This adaptive capacity to different clock frequencies of Analog Subscriber Line Board makes it can be common to local side apparatus and remote equipment, and design specialized is in the Analog Subscriber Line Board and the Analog Subscriber Line Board that is exclusively used in remote equipment of local side apparatus respectively, and this has just reduced the kind of veneer.Other each interface board 5 also can be realized the function of this automatic adaptation Bus Clock Rate in the same way as digital subscriber board, analog junction plate, Digital Trunk Board, Leased line interface board etc.
The utility model contrast existing equipment has following advantage: 1, the bandwidth of backboard is decided by that clock produces The clock frequency of circuit output can be carried out assignment by webmaster, so both can satisfy simultaneously local side apparatus and far away End equipment does not cause again waste or the deficiency of bandwidth to the different requirements of bandwidth; 2, each veneer can be general In local side apparatus and remote equipment, thereby reduced the kind of veneer; 3, local side apparatus and far-end have been desalinated The difference of equipment makes the installation of equipment and networking flexibility convenient; 4, all can select different networking capacity Suitable bandwidth has further improved the utilization rate of bandwidth.

Claims (7)

1, a kind of variable bandwidth formula digital loop carrier equipment, it comprises backboard (1) and the some veneers (2) that link to each other with backboard (1) with plugging mode, it is characterized in that: described backboard (1) adopts bus mode, comprise that at least one is used for Data-carrying bus (6) and control bus (7) that is used to coordinate each veneer operation of transmitting data stream, having at least a master control borad (3) to dispose adjustable being used for of output frequency in the described veneer (2) provides clock clock generation circuit (15) to Data-carrying bus (6).
2, variable bandwidth formula digital loop carrier equipment as claimed in claim 1 is characterized in that: described Data-carrying bus (6) adopts the time division multiplexing tdm bus, is made up of clock line (9), line synchro (10) and some data wires (8).
3, variable bandwidth formula digital loop carrier equipment as claimed in claim 1 is characterized in that: described control bus (7) adopts single-chip microcomputer MCS51 serial ports form and TTL interface level.
4, variable bandwidth formula digital loop carrier equipment as claimed in claim 1 is characterized in that: described clock generation circuit (15) is by clock generator (16) and formed by the clock regulating circuit (17) of central processing unit (13) control.
5, variable bandwidth formula digital loop carrier equipment as claimed in claim 1 is characterized in that: the clock frequency adjustable extent of described clock generation circuit (15) output is 4.096MHz, 8.192MHz and three kinds of frequencies of 16.384MHz.
6, variable bandwidth formula digital loop carrier equipment as claimed in claim 1 or 2 is characterized in that: the transmission rate of the data wire (8) of described Data-carrying bus (6) is half of frequency of clock line (9).
7, variable bandwidth formula digital loop carrier equipment as claimed in claim 1, it is characterized in that: described veneer (2) comprises master control borad (3), power supply ringing-current plate (4) and various interface plate (5), and described clock generation circuit (15) is configured in the master control borad (3).
CN 00226507 2000-06-13 2000-06-13 Variable bandwidth digital loop carrier equipment Expired - Fee Related CN2430817Y (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 00226507 CN2430817Y (en) 2000-06-13 2000-06-13 Variable bandwidth digital loop carrier equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 00226507 CN2430817Y (en) 2000-06-13 2000-06-13 Variable bandwidth digital loop carrier equipment

Publications (1)

Publication Number Publication Date
CN2430817Y true CN2430817Y (en) 2001-05-16

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CN 00226507 Expired - Fee Related CN2430817Y (en) 2000-06-13 2000-06-13 Variable bandwidth digital loop carrier equipment

Country Status (1)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103729333A (en) * 2014-01-20 2014-04-16 烽火通信科技股份有限公司 Backplane bus structure sharing multiple channel time slots and implementation method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103729333A (en) * 2014-01-20 2014-04-16 烽火通信科技股份有限公司 Backplane bus structure sharing multiple channel time slots and implementation method thereof

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CF01 Termination of patent right due to non-payment of annual fee
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