CN221575155U - Multiphase voltage stabilizer and current balance circuit - Google Patents

Abstract

The utility model provides a multiphase voltage stabilizer and a current balance circuit, wherein the multiphase voltage stabilizer is coupled to a multiphase direct current-direct current converter and comprises a plurality of voltage stabilizer circuits. The voltage regulator circuit is coupled between the power output stage circuit and the compensation circuit and is used for generating a plurality of control signals according to the compensation signals so as to enable the power output stage circuit to generate a plurality of output currents. The voltage regulator circuit includes a current comparison circuit and a delay circuit. The current comparison circuit is used for obtaining an error signal. The error signal is the difference between the threshold current and the corresponding output current. The delay circuit is coupled to the compensation circuit and the current comparison circuit and is used for generating a corresponding control signal according to the compensation signal. The delay circuit is used for adjusting the bias current in the delay circuit according to the error signal so as to adjust the duty cycle of the corresponding control signal. Accordingly, balance control of the respective phase currents will be achieved.

Description

Multiphase voltage stabilizer and current balance circuit

Technical Field

The present utility model relates to a current balancing technology, and more particularly, to a multiphase voltage regulator and a current balancing circuit.

Background

A direct current-to-direct current converter (DC-to-DC converter) is an electromechanical device for converting electric energy to convert the voltage of a direct current power supply. The DC-DC converter has wide application, and can be used for supplying power to a low-power device (such as a battery) or a high-power device (such as an industrial machine). The multiphase DC-DC converter comprises a plurality of converters with different phases so as to alternately output electric energy to the output end, and whether the output electric energy among the converters with different phases is consistent or not can affect the power supply stability of the DC-DC converter. Therefore, there is a need for a novel dc-dc converter that provides better power stability.

Disclosure of utility model

The present utility model relates to a multiphase voltage regulator coupled to a multiphase dc-dc converter and comprising a plurality of voltage regulator circuits. The voltage regulator circuit is coupled between the power output stage circuit and the compensation circuit of the multiphase DC-DC converter and is used for generating a plurality of control signals according to the compensation signals so as to enable the power output stage circuit to generate a plurality of output currents. One of the plurality of voltage regulator circuits includes a current comparison circuit and a delay circuit. The current comparison circuit is used for obtaining an error signal. The error signal is the difference between the threshold current and a corresponding one of the plurality of output currents. The delay circuit is coupled to the compensation circuit and the current comparison circuit and is used for generating a corresponding one of the control signals according to the compensation signal. The delay circuit is used for adjusting bias current in the delay circuit according to the error signal so as to adjust the duty cycle of a corresponding one of the control signals.

In one embodiment, the delay circuit includes a first current source circuit to provide a first bias current, and the current comparison circuit includes a first current comparator. The first end of the first current comparator is used for receiving the threshold current, the second end of the first current comparator is used for receiving a corresponding one of the plurality of output currents, and the first current comparator outputs a first error signal to the first current source circuit so as to change the first bias current.

In one embodiment, the delay circuit includes a second current source circuit to provide a second bias current, and the current comparison circuit includes a second current comparator. The first end of the second current comparator is used for receiving a corresponding one of the plurality of output currents, the second end of the second current comparator is used for receiving a threshold current, and the second current comparator outputs a second error signal to the second current source circuit so as to change the second bias current.

In an embodiment, the threshold current is an average current of the plurality of output currents.

In one embodiment, the delay circuit further includes an inverter and a delay capacitor. The inverter has an input terminal, an output terminal, a first correction terminal, and a second correction terminal. The input end of the inverter is coupled to the output end of the compensation circuit to receive the compensation signal, the first correction end of the inverter is used for receiving the first bias current, the second correction end of the inverter is used for receiving the second bias current, and the output end of the inverter is used for outputting the node signal. The first bias current and the second bias current are used for adjusting the phase of the node signal. The delay capacitor is coupled between the output end of the inverter and the reference potential. When the error signal is at a high level, the delay capacitor is used for delaying the time of the node signal from the high logic level to the low logic level. When the error signal is at a low level, the delay capacitor is used for delaying the time of the node signal from the low logic level to the high logic level.

In one embodiment, the delay circuit further includes a hysteresis comparator. The hysteresis comparator is coupled to the output end of the inverter and is used for generating a corresponding one of the control signals according to the node signal.

In one embodiment, the delay circuit further includes an inverter. The inverter has an input end and an output end, the input end of the inverter is used for receiving the compensation signal, and the output end of the inverter is used for outputting the node signal.

In one embodiment, the delay circuit further includes a hysteresis comparator. The hysteresis comparator is coupled to the output end of the inverter. The hysteresis comparator is provided with an input end, an output end, a first correction end and a second correction end. The input end of the hysteresis comparator is coupled with the output end of the inverter to receive the node signal from the inverter. The first correction end of the hysteresis comparator is used for receiving the first bias current. The second correction end of the hysteresis comparator is used for receiving a second bias current. The hysteresis comparator is used for generating a corresponding one of the control signals according to the node signal, the first bias current and the second bias current.

In one embodiment, the first threshold voltage and the second threshold voltage of the hysteresis comparator are changed according to the first bias current and the second bias current. When the error signal is high, the second threshold voltage is lowered to delay the time for the node signal to go from the high logic level to the low logic level. When the error signal is at a low level, the first threshold voltage is raised to delay the time for the node signal to go from the low logic level to the high logic level.

The utility model also relates to a multiphase current balance circuit which is applied to a multiphase direct current-direct current converter and comprises a current detection circuit and a plurality of voltage stabilizer circuits. The current detection circuit is coupled to the power output stage circuit of the multiphase DC-DC converter to obtain a plurality of output currents and threshold currents. The voltage regulator circuit is coupled between the current detection circuit and the compensation circuit of the multiphase DC-DC converter and is used for generating a plurality of control signals according to the compensation signals so as to enable the power output stage circuit to generate a plurality of output electricity. One of the plurality of voltage regulator circuits includes a current comparison circuit and a delay circuit. The current comparison circuit is used for obtaining an error signal. The error signal is the difference between the threshold current and a corresponding one of the plurality of output currents. The delay circuit is coupled to the compensation circuit and the current comparison circuit and is used for generating a corresponding one of the control signals according to the compensation signal. The delay circuit is used for adjusting bias current in the delay circuit according to the error signal so as to adjust the duty cycle of a corresponding one of the control signals.

The utility model adjusts the duty cycle of the control signal by the difference value of the first output current and the average current so as to achieve the technical effect of balancing the output currents of each phase without changing the level of the response voltage or the slope voltage. In contrast, the background art has to change the level of the response voltage or the ramp voltage to adjust the duty cycle of the control signal.

Drawings

Fig. 1A is a schematic diagram of a multiphase dc-dc converter according to some embodiments of the present disclosure.

Fig. 1B is a schematic diagram of a current detection circuit according to some embodiments of the present disclosure.

Fig. 2 is a waveform diagram of control signals according to some embodiments of the present disclosure.

Fig. 3A is a schematic diagram of a voltage regulator circuit according to some embodiments of the present disclosure.

Fig. 3B is a schematic diagram illustrating voltage characteristics of a hysteresis comparator according to some embodiments of the present disclosure.

Fig. 4A is a schematic diagram of a voltage regulator circuit according to some embodiments of the present disclosure.

Fig. 4B is a schematic diagram of voltage characteristics of a hysteresis comparator according to some embodiments of the present disclosure.

Detailed Description

Various embodiments of the utility model are disclosed in the accompanying drawings, and for purposes of explanation, numerous practical details are set forth in the following description. However, it should be understood that these practical details are not to be taken as limiting the utility model. That is, in some embodiments of the utility model, these practical details are unnecessary. In addition, for the sake of simplicity of the drawing, some of the conventional structures and elements are shown in the drawing in a simplified schematic manner.

Herein, when an element is referred to as being "connected" or "coupled," it can be referred to as being "electrically connected" or "electrically coupled. "connected" or "coupled" may also mean that two or more elements co-operate or interact with each other. Furthermore, although the terms "first," "second," …, etc. may be used herein to describe various elements, this term is merely intended to distinguish between elements or operations that are described in the same technical term. Unless the context clearly indicates otherwise, the terms do not specifically refer to or imply a sequence or order, nor are they intended to be limiting of the utility model.

The present disclosure relates to a multiphase dc-dc converter for converting an input voltage to output voltages of different voltages. In an embodiment, the multiphase dc-dc converter is applied to a power supply for a vehicle, for example, as a power transmission circuit, and may store the power of the charging pile into a battery or provide the stored power of the battery to an in-vehicle device. However, the present disclosure is not limited thereto, and in other embodiments, the multiphase dc-dc converter can be applied to other devices and loads.

Fig. 1A is a schematic diagram of a multiphase dc-dc converter 100 according to some embodiments of the present disclosure. The multiphase dc-dc converter 100 includes a power output stage 110, a current balancing circuit 120, and a compensation circuit 130. The power output stage 110 includes a plurality of driving circuits DC and a switching circuit 111 formed by a plurality of transistor switches, wherein each driving circuit DC and the corresponding switching circuit 111 are configured to generate corresponding output currents Is1 to Isn according to an input voltage Vin.

In the embodiment shown in fig. 1A, the power output stage 110 includes a plurality of sub-circuits (e.g., two or more sub-circuits), each of which includes a driving circuit DC, and the switch circuit 111 includes an upper switch Ta and a lower switch Tb, and is coupled to the input voltage Vin. The driving circuit DC Is used for controlling the upper bridge switch Ta and the lower bridge switch Tb to be turned on or turned off according to the received control signals so as to generate or adjust corresponding output currents IS 1-Isn. The phases of the output currents Is1 to Isn generated by each group of sub-circuits may be different from each other, for example, when the power output stage circuit 110 includes a plurality of groups of sub-circuits, there Is a predetermined phase difference between the output currents of adjacent sub-circuits.

In one embodiment, the power output stage 110 generates the output voltage Vout and the feedback voltage Vfb through the tank circuit 140 and the voltage divider circuit 150. The tank circuit 140 Is coupled to the output end of the power output stage 110, and includes a plurality of inductors L1-Ln and an output capacitor Cout for generating an output voltage Vout according to the output currents IS 1-Isn. The voltage divider circuit 150 is coupled to the power output stage 110 and the tank circuit 140, and includes a plurality of voltage dividing resistors R1 and R2 for dividing the output voltage Vout to generate a feedback voltage Vfb. Since one skilled in the art can understand the manner in which the multiphase dc-dc converter 100 generates the output voltage Vout, further details are not described herein.

The current balancing circuit 120 is coupled to the power output stage 110, and includes a current detecting circuit 121 and a multiphase voltage regulator 122. The current balancing circuit 120 Is configured to generate and adjust a plurality of control signals Spwm 1-Spwmn corresponding to different phases, so that the power output stage 110 generates a plurality of output currents Is 1-Isn corresponding to different phases, and thus the currents of the phases are balanced. The generation of the control signal will be described in detail in the following paragraphs.

The current balancing circuit 120 is coupled to the compensation circuit 130 and the power output stage 110. The compensation circuit 130 is configured to receive the response voltage Vea from the power output stage 110 and generate the compensation signal Vcomp. The response voltage Vea is generated according to a difference between the feedback voltage Vfb provided by the output terminal of the multiphase dc-dc converter 100 and a reference voltage (e.g., a reference voltage or a predetermined fixed voltage). Specifically, in one embodiment, the feedback voltage Vfb generated by the power output stage 110 is subtracted from the reference voltage to obtain the response voltage Vea. In other embodiments, the power output stage 110 may also directly use the feedback voltage Vfb as the response voltage Vea.

The compensation circuit 130 is configured to compare the response voltage Vea with the ramp voltage Vramp to generate the compensation signal Vcomp according to a difference between the response voltage Vea and the ramp voltage Vramp. The compensation signal Vcomp is used to reflect the current state (e.g., heavy load or light load) of the output voltage Vout. After the compensation signal Vcomp is provided to the current balancing circuit 120, the current balancing circuit 120 generates the control signals Spwm 1-Spwmn according to the compensation signal Vcomp.

In one embodiment, the positive terminal of the compensation circuit 130 is configured to receive the response voltage Vea, and the negative terminal of the compensation circuit 130 is configured to receive the ramp voltage Vramp, so that the magnitude of the compensation signal Vcomp is positively correlated with the "difference between the response voltage Vea and the ramp voltage Vramp". However, the disclosure is not limited thereto, and in other embodiments, the signals received by the positive and negative terminals of the compensation circuit 130 can be exchanged according to the actual circuit design.

In one embodiment, the ramp voltage Vramp is a periodic signal whose signal magnitude varies periodically over a period of time. In other embodiments, the ramp voltage Vramp may be a sawtooth wave having a fixed slope during the signal period. The term "sawtooth" refers to a signal that starts to change (e.g., rise or fall) from a fixed level during each signal cycle and returns to the original fixed level when the current signal cycle ends and the next signal cycle is entered. In some embodiments, the signal slope of the ramp voltage Vramp is positive, i.e., the level of the ramp voltage Vramp gradually rises during the signal period. However, the disclosure is not limited thereto, and in other embodiments, the ramp voltage Vramp may be a triangle wave according to different slopes.

In an embodiment of the present utility model, a plurality of voltage regulator circuits 200 are disposed in the current balance circuit 120, and the voltage regulator circuits 200 can selectively change the level change time of the control signals Spwm 1-Spwmn according to the power supply state of the multiphase dc-dc converter 100 (e.g. according to the magnitude of the compensation signal Vcomp and/or the output current) so as to ensure that the phase currents outputted by the multiphase dc-dc converter 100 can be kept balanced (i.e. the output currents of the phases can be kept substantially equal). For ease of description, the plurality of voltage regulator circuits 200 in the multiphase dc-dc converter 100 corresponding to the multiphase are collectively referred to herein as a "multiphase voltage regulator".

As shown in fig. 1A, in the present embodiment, the current balancing circuit 120 includes a current detecting circuit 121 and a multiphase voltage regulator 122. The current detection circuit 121 Is coupled to the power output stage 110 to obtain the output currents Is1 to Isn and the threshold current. The current detection circuit 121 Is also configured to generate a plurality of error signals provided to the plurality of voltage regulator circuits 200 according to the threshold current and the output currents Is1 to Isn.

In one embodiment, the threshold current is an average value or a median value of the plurality of driving currents generated by the power output stage 110, in other words, the threshold current is calculated by the current detection circuit 121, but the disclosure is not limited thereto. In other embodiments, the threshold current may also be a predetermined fixed current value, such as an ideal current value output by the power output stage circuit 110 of each phase when the multiphase dc-dc converter 100 is operating normally. In other embodiments, the threshold current may be obtained by a lookup table, for example, the values of the corresponding output currents Is1 to Isn are looked up according to the level of the input voltage Vin.

In one embodiment, the error signal is the difference between the threshold current and each output current, such as the error currents Idiff 1-Idiffn shown in FIG. 1A. In other embodiments, the current detection circuit 121 is configured to perform signal processing on the threshold current and the corresponding output current to generate error signals for outputting to the corresponding voltage regulator circuit 200, respectively.

Specifically, in some embodiments, the current detection circuit 121 can detect the phase nodes N1 to Nn between the upper bridge switch Ta and the lower bridge switch Tb in the power output stage 110 to obtain the voltages Lx1 to Lxn of the phase nodes N1 to Nn, and further calculate the corresponding output currents, and the current detection circuit 121 can calculate the average current of the output currents as the threshold current.

Fig. 1B is a schematic diagram of a current detection circuit 121 according to some embodiments of the present disclosure. As shown in fig. 1A and 1B, the current detection circuit 121 includes a transfer circuit 121A, an adder circuit 121B, a divider circuit 121c, and a subtractor circuit 121d. The transfer circuit 121a Is coupled to the power output stage 110 for receiving the output currents Is1 to Isn. In one embodiment, the transfer circuit 121a includes a transfer amplifier (transconductance amplifier) to receive the voltages Lx 1-Lxn at the phase nodes N1-Nn and calculate the output currents IS 1-Isn.

The adder circuit 121b Is coupled to the transfer circuit 121a for receiving the output currents Is1 to Isn, and calculates an average current Iavg of the output currents Is1 to Isn through the divider circuit 121 c. The subtractor circuit 121d is coupled to the divider circuit 121c for calculating a difference between the output current of the corresponding phase and the average current Iavg to generate error currents Idiff 1-Idiffn.

The multiphase voltage regulator 122 includes a plurality of voltage regulator circuits 200 coupled between the compensation circuit 130 and the current detection circuit 121 for receiving the error signal and the compensation signal Vcomp. As described above, the error signal provided by the current detection circuit 121 may be the error currents Idiff1 to Idiffn calculated and generated by the current detection circuit 121, or may be the calculation result of the threshold current and the corresponding output current provided by the current detection circuit 121. The multiphase voltage regulator 122 Is configured to generate a plurality of control signals Spwm 1-Spwmn corresponding to different phases according to the error signal and the compensation signal Vcomp, so that the power output stage 110 generates the output currents Is 1-Isn. In addition, the voltage regulator circuit 200 can selectively change the level change time point (e.g., delay or advance) of the corresponding control signal, so that the plurality of output currents Is1 to Isn between different phases can be balanced.

In one embodiment, the multiphase voltage regulator 122 includes a plurality of voltage regulator circuits 200, each voltage regulator circuit 200 Is configured to generate control signals Spwm 1-Spwmn of the output currents Is 1-Isn of the corresponding phases to provide the control signals Spwm 1-Spwmn to the respective driving circuits DC.

In some embodiments, the control signals Spwm 1-Spwmn generated by each of the voltage regulator circuits 200 are Pulse-width modulation (PWM) signals. The voltage regulator circuit 200 can also adjust duty cycles (duty ratios) of the control signals Spwm 1-Spwmn, so as to change the magnitudes of the output currents Is 1-Isn generated by the power output stage circuit 110. Since those skilled in the art can understand the manner of transmitting the control signal between the power output stage 110 and the current balancing circuit by using the digital signal, the description is omitted herein.

Fig. 2 illustrates a concept of "the level change time points of the control signals Spwm 1-Spwmn are controlled to ensure that the phase currents outputted by the multiphase dc-dc converter 100 are balanced" according to some embodiments of the present utility model. Referring to fig. 1A and 2, a current balancing circuit 120 and a voltage regulator circuit 200 for controlling the output current Is1 are described herein as an example. In FIG. 2, waveforms Spwm-A through Spwm-C represent the waveform changes of the control signal Spwm1 in different situations, respectively. The waveform Spwm-a represents the waveform of "when the output current Is1 Is equal to the average current Iavg". The waveform Spwm-B represents the waveform (i.e., the turndown duty cycle) that the control signal Spwm1 should be adjusted to "when the output current Is1 Is greater than the average current Iavg". The waveform Spwm-C represents the waveform (i.e., the lifting duty cycle) that the control signal Spwm1 should be adjusted to "when the output current Is1 Is less than the average current Iavg".

As shown in fig. 2, the time point when the level of the response voltage Vea is the same as the level of the ramp voltage Vramp will be the time point when the level of the control signal Spwm1 is changed. In other words, the "time point when the levels of the response voltage Vea and the ramp voltage Vramp are the same" is related to the duty cycle of the control signal Spwm 1. As shown in the waveform Spwm-a, when the response voltage Vea decreases from a high level to a level with the ramp voltage Vramp (i.e., the time point P1), the control signal Spwm1 will change from a low level to a high level. When the response voltage Vea rises from the low level to the level of the ramp voltage Vramp (i.e., the time point P3), the control signal Spwm1 will change from the high level to the low level. It should be noted that the present disclosure does not adjust the duty cycle of the control signal Spwm1 by changing the level of the response voltage Vea or the ramp voltage Vramp, but adjusts the duty cycle of the control signal Spwm1 by the difference between the output current Is1 and the average current Iavg, so as to achieve the technical effect of equalizing the output currents of the phases.

Referring to fig. 2, for example, in a positive half period (from the time point P1 to the time point P3 of the waveform Spwm-a) of the power output stage 110, when the control signal Spwm1 Is at a high level and the ramp voltage Vramp Is lower than the response voltage Vea, the upper bridge switch Ta Is turned on and the lower bridge switch Tb Is turned off, the input voltage Vin charges the output capacitor Cout and the inductor L1, and an output current Is1 flowing from the phase node N1 to the output capacitor Cout Is formed. Then, the current detection circuit 121 receives the voltages Lx1 to Lxn of the phase nodes N1 to Nn, and calculates the output currents Is1 to Isn from the voltages Lx1 to Lxn. As shown in fig. 1B and 2, the current detection circuit 121 compares the output currents Is1 to Isn with the current average value (i.e., the average current Iavg or the threshold current described above) of these currents. For example, when the output current Is1 Is greater than the average current Iavg, the duty cycle of the control signal Spwm1 should be reduced to reduce the output current Is1. Therefore, the voltage regulator circuit 200 corresponding to the control signal Spwm1 delays the control signal Spwm 1' from the low level to the high level (e.g., the waveform Spwm-B is delayed from the time point P1 to the time point P2) to reduce the duty cycle of the control signal Spwm 1. In this way, by decreasing the duty cycle of the control signal Spwm1, that Is, the on time of the upper bridge switch Ta Is shortened, the output current Is1 can be decreased.

Similarly, when the output current Is1 Is smaller than the average current Iavg, the duty cycle of the control signal Spwm1 should be increased to increase the output current Is1. Therefore, the voltage regulator circuit 200 corresponding to the control signal Spwm1 delays the time point when the control signal Spwm 1' falls from the high level to the low level (e.g., the waveform Spwm-C, and delays from the time point P3 to the time point P4) to increase the duty cycle of the control signal Spwm 1. In this way, by increasing the duty cycle of the control signal Spwm1, that Is, the on time of the upper bridge switch Ta becomes longer, the output current Is1 can be increased.

The following description begins with the implementation of the voltage regulator circuit 200 and the corresponding circuits for adjusting the time points at which the control signals Spwm 1-Spwmn change the level. As shown in fig. 1A, the voltage regulator circuit 200 includes a current comparing circuit 210 and a delay circuit 220, wherein the current comparing circuit 210 is coupled to the delay circuit 220. The current comparison circuit 210 Is coupled to the current detection circuit 121 to obtain an error signal, for example, to receive a corresponding one of the error currents Idiff1-Idiffn from the current detection circuit 121, or to receive a threshold current (e.g., a current average value, refer to the average current Iavg of FIG. 3A) and a corresponding output current (refer to the output current IS1 of FIG. 3A) from the current detection circuit 121.

The delay circuit 220 is coupled to the compensation circuit 130 and the current comparison circuit 210, and generates a corresponding control signal according to the compensation signal Vcomp. The delay circuit 220 Is further configured to adjust the bias current in the delay circuit according to the error signal (e.g. the corresponding error current Idiff1, or the average current Iavg and the output current Is1 shown in the following FIGS. 1B and 3A) to adjust the duty cycle of the corresponding control signal.

The utility model utilizes the error signal to confirm the state (such as overlarge or overlarge) of the output current of each phase, and then selectively changes the level change time of the corresponding control signal, such as changing the time point when the control signal enters a high level or changing the time point when the control signal enters a low level, thereby adjusting the duty cycle of the control signal and realizing the purpose of keeping balance of the currents of each phase.

In some embodiments, the multiphase dc-dc converter 100 can control the phase of the signal at the control node in the delay circuit 220 to achieve the objective of "control the level change time of the signal". In other embodiments, the multiphase dc-dc converter 100 can also control the threshold voltages of the circuit elements in the delay circuit 220 to achieve the objective of "level change time of control signal". The respective control modes of the present utility model will be described by the embodiments of fig. 3A, 3B, 4A, and 4B.

Fig. 3A is a schematic diagram of a voltage regulator circuit 300 according to some embodiments of the present disclosure, which can be applied to the multiphase dc-dc converter 100 shown in fig. 1A. The voltage regulator circuit shown in fig. 3A may be an example of the voltage regulator circuit 200 shown in fig. 1A. The voltage regulator circuit 300 includes a current comparing circuit 310 and a delay circuit 320, wherein the current comparing circuit 310 is coupled to the delay circuit 320. The current comparing circuit 310 Is coupled to the current detecting circuit 121 for receiving the average current Iavg and the output current Is1. The delay circuit 320 is coupled to the compensation circuit 130 and the current comparison circuit 310, and adjusts the phase of a signal on the control node NA (hereinafter referred to as the node signal S3) in the delay circuit 320 according to the error signal, so as to adjust the duty cycle of the corresponding control signal. The current comparing circuit 310 and the delay circuit 320 may be examples of the current comparing circuit 210 and the delay circuit 220, respectively.

As shown in fig. 3A, in one embodiment, the current comparison circuit 310 includes a first current comparator 311. The first current comparator 311 Is coupled to the current detection circuit 121, and has a first end (e.g., a negative electrode) for receiving a threshold current (i.e., an average current Iavg in the present embodiment) and a second end (e.g., a positive electrode) for receiving a corresponding output current Is1. The first current comparator 311 will generate a first error signal S1 based on the difference between the average current Iavg and the output current Is1.

In one embodiment, the delay circuit 320 includes a first current source 321 for providing the first bias current Ib1 according to the power supply Vcc. The first current source circuit 321 is further configured to receive the first error signal S1 generated by the first current comparator 311, and change the magnitude of the output first bias current Ib1 according to the first error signal S1. In some embodiments, the first error signal S1 may be a voltage signal for changing the magnitude of the first bias current Ib1. In some other embodiments, the current comparing circuit 310 may be omitted, and in this arrangement, the first current source circuit 321 and the second current source circuit 322 may be directly coupled to the current detecting circuit 121 to receive a corresponding one of the error currents Idiff1-Idiffn, such as the error current Idiff1, and directly use the error current Idiff1 as the first error signal S1 and use the inverted error current Idiff1 as the second error signal S2; or directly takes the error current Idiff1 as the second error signal S2 and takes the inverted error current Idiff1 as the first error signal S1.

Similarly, in an embodiment, the current comparison circuit 310 may also include a second current comparator 312. The second current comparator 312 Is coupled to the current detection circuit 121 and the inverter 323, wherein a first end (e.g., a negative electrode) of the second current comparator 312 Is configured to receive the corresponding output current Is1, and a second end (e.g., a positive electrode) of the second current comparator 312 Is configured to receive the threshold current (i.e., the average current Iavg in the present embodiment). The second current comparator 312 generates a second error signal S2 according to the difference between the average current Iavg and the output current Is 1.

In addition, the delay circuit 320 further includes a second current source circuit 322 for providing a second bias current Ib2 according to the power supply Vcc. The second current source circuit 322 is coupled to the second current comparator 312 and the inverter 323, and is configured to receive the second error signal S2 generated by the second current comparator 312, and change the magnitude of the output second bias current Ib2 according to the second error signal S2. It Is particularly mentioned that the first current comparator 311 and the second current comparator 312 are used for receiving the corresponding output current Is1 and the average current Iavg, but the receiving positions (i.e., the positive and negative poles) are opposite, so that the first error signal S1 and the second error signal S2 have different logic levels.

Specifically, as shown in fig. 3A, the delay circuit 320 includes an inverter 323, a delay capacitor C31, and a hysteresis comparator 324. The input end of the inverter 323 is coupled to the output end of the compensation circuit 130 for receiving the compensation signal Vcomp, and the output end of the inverter 323 is coupled to the control node NA for outputting the node signal. The first calibration end of the inverter 323 is coupled to the first current source 321 to receive the first bias current Ib1, and the second calibration end of the inverter 323 is coupled to the second current source 322 to receive the second bias current Ib2. The inverter 323 is used for controlling the delay capacitor C31 to charge or discharge according to the first bias current and/or the second bias current so as to adjust the phase of the node signal of the control node NA.

The delay capacitor C31 is coupled between the output terminal (e.g., the control node NA) of the inverter 323 and a reference potential (e.g., a ground potential). The hysteresis comparator 324 is also coupled to the output terminal (control node NA) of the inverter 323 for generating the corresponding control signal Spwm1 according to the node signal S3. In one embodiment, the hysteresis comparator 324 may be implemented by a schmitt trigger.

Fig. 3B is a diagram showing the voltage characteristics of the hysteresis comparator 324 in some embodiments, wherein the horizontal axis represents the input voltage (i.e. the node signal S3) received by the hysteresis comparator 324, and the vertical axis represents the output voltage (i.e. Spwm 1) outputted by the hysteresis comparator 324. The voltage characteristic of the hysteresis comparator 324 presents a hysteresis curve, and when the input voltage of the hysteresis comparator 324 rises to the first threshold voltage VTH, the output voltage will flip to a low level (as shown by a curve L31); when the input voltage of the hysteresis comparator 324 drops to the second threshold voltage VTL, the output voltage will flip to a high level (as shown by the change curve L32); when the input voltage of the hysteresis comparator 324 is between the first threshold voltage VTH and the second threshold voltage VTL, the output voltage will not flip. Since one skilled in the art can understand the characteristics and implementation of the hysteresis comparator 324, further details are not described herein.

Referring to fig. 1A, fig. 2, and fig. 3A to fig. 3B, the following describes an operation process of the delay circuit 320 for adjusting the bias current in the delay circuit according to the error signal, thereby changing the duty cycle of the corresponding control signal. As shown in fig. 2, under the positive half period of the power output stage circuit operation, i.e. when the response voltage Vea Is greater than the ramp voltage Vramp, the compensation signal Vcomp Is at a high level, the node signal S3 output by the inverter 323 should be turned to a low level, and if the output current Is1 Is greater than the average current Iavg, the first error signal S1 Is at a high level and the second error signal S2 Is at a low level, so as to control the first current source circuit 321 to increase the first bias current Ib1 and control the second current source circuit 322 to decrease the second bias current Ib2, respectively. In the case where the first bias current Ib1 becomes larger and the second bias current Ib2 becomes smaller, the delay capacitor C31 is additionally charged, so that the time point when the node signal S3 falls to the low level (to at least the second threshold voltage VTL) will be slower, that is, the time point when the delay comparator 324 converts the received node signal S3 with the low level into the control signal Spwm1 with the high level will be delayed, as shown by the waveform Spwm-B shown in fig. 2, and the time point when the control signal Spwm1 rises to the high level will be delayed from the original time point P1 to the time point P2. In this way, the duty cycle of Spwm1 is reduced. When the duty cycle of Spwm1 decreases, the on time of the upper bridge switch Ta becomes shorter, so that the output current Is1 Is reduced, and the effect of balancing the currents of each phase Is achieved.

For the positive half period of the power output stage 110, referring to the waveform Spwm-C, if the output current Is1 Is smaller than the average current Iavg, the first bias current Ib1 decreases and the second bias current Ib2 increases, so that the delay capacitor C31 Is smoothly discharged, and the time for the node signal S3 to go low (at least to the second threshold voltage VTL) Is not affected, i.e. the time for the control signal Spwm1 to go high Is not affected, so the time for the waveform Spwm-C to go high Is the same as the time for the waveform Spwm-a to go high during the positive half period.

Next, as shown in fig. 2, in a negative half period of the operation of the power output stage 110, i.e. when the response voltage Vea Is smaller than the ramp voltage Vramp, the compensation signal Vcomp Is at a low level, the node signal S3 outputted by the inverter 323 should be turned to a high level, and if the output current Is1 Is smaller than the average current Iavg, the first error signal S1 Is at a low level and the second error signal S2 Is at a high level, the first current source circuit 321 Is controlled to decrease the first bias current Ib1 and the second current source circuit 322 Is controlled to increase the second bias current Ib2, respectively, and the delay capacitor C31 Is additionally discharged when the first bias current Ib1 Is smaller and the second bias current Ib2 Is larger. Therefore, the node signal S3 rises to a high level (at least the first threshold voltage VTH is required to satisfy the voltage inversion condition, and the principle can be referred to as fig. 3B), i.e. the delay comparator 324 delays the time point when the received node signal S3 with a high level is converted into the control signal Spwm1 with a low level, as shown in the waveform Spwm-C in fig. 2, and the time point when the control signal Spwm1 falls to a low level is delayed from the original time point P3 to the time point P4. This corresponds to an increase in the duty cycle of Spwm 1. When the duty cycle of Spwm1 increases, the on time of the upper bridge switch Ta becomes longer, so that the output current Is1 Is increased, and the current balance effect of each phase Is achieved.

In the negative half cycle of the power output stage 110, if the output current Is1 Is greater than the average current Iavg, the first bias current Ib1 Is raised and the second bias current Ib2 Is lowered, so that the delay capacitor C31 Is smoothly charged, and the time for the node signal S3 to go high (up to at least the first threshold voltage VTH) Is not affected, so that the time for the waveform Spwm-B to go low Is the same as the time for the waveform Spwm-a to go low in the negative half cycle.

In the foregoing embodiment, the voltage regulator circuit 300 includes the first current comparator 311, the second current comparator 312, the first current source circuit 321 and the second current source circuit 322. The first current comparator 311 and the corresponding first current source circuit 321 are configured to generate a first bias current Ib1 to change the phase change time of the node signal on the control node NA. Similarly, the second current comparator 312 and the corresponding second current source circuit 322 are also configured to generate the second bias current Ib2 to change the phase change time of the node signal on the control node NA. However, in other embodiments, the voltage regulator circuit 300 may also have only the first bias current Ib1 or the second bias current Ib2, so as to change the phase change time of the node signal on the control node NA. In other words, in other embodiments, the voltage regulator circuit 300 may include only the first current comparator 311 and the corresponding first current source circuit 321, or only the second current comparator 312 and the corresponding second current source circuit 322.

Fig. 4A is a schematic diagram of a voltage regulator circuit 400 according to some embodiments of the present disclosure, which can be applied to the multiphase dc-dc converter 100 shown in fig. 1A. The voltage regulator circuit shown in fig. 4A may be an example of the voltage regulator circuit 200 shown in fig. 1A. The voltage regulator circuit 400 includes a current comparison circuit 410 and a delay circuit 420. The current comparing circuit 410 is coupled to the current detecting circuit 121 for receiving the error signal. The delay circuit 420 is coupled to the compensation circuit 130 and the current comparison circuit 410, and adjusts the phase of the node signal on the control node NA in the delay circuit 420 according to the error signal to adjust the duty cycle of the corresponding control signal Spwm 1. The current comparison circuit 410 and the delay circuit 420 may be examples of the current comparison circuit 210 and the delay circuit 220, respectively.

As shown in fig. 4A, in an embodiment, the current comparison circuit 410 includes a first current comparator 411 and a second current comparator 412, and the delay circuit 420 includes a first current source circuit 421 and a first current source circuit 421.

The first current comparator 411 and the first current source circuit 421 are configured to receive the average current Iavg and the corresponding output current Is1 from the current detection circuit 121 to generate the first bias current Ib1. The second current comparator 412 and the second current source circuit 422 are configured to receive the average current Iavg and the corresponding output current Is1 from the current detection circuit 121 to generate the second bias current Ib2. In an embodiment, the circuits of the first current comparator 411, the first current source circuit 421, the second current comparator 412 and the second current source circuit 422 are similar to the circuits of the first current comparator 311, the first current source circuit 321, the second current comparator 312 and the second current source circuit 322 shown in fig. 3A, respectively, so the detailed description thereof is omitted.

Specifically, as shown in fig. 4A, the delay circuit 420 includes an inverter 423, a delay capacitor C41, and a hysteresis comparator 424. The input end of the inverter 423 is coupled to the output end of the compensation circuit 130 for receiving the compensation signal Vcomp, and the output end of the inverter 423 is coupled to the control node NA and the delay capacitor C41 for outputting the node signal S4.

An input terminal of the hysteresis comparator 424 is coupled to an output terminal of the inverter 423, and takes a node signal S4 of the control node NA as an input voltage. The first correction terminal (e.g., positive correction terminal) of the hysteresis comparator 424 is coupled to the first current source circuit 421 for receiving the first bias current Ib1. The second correction terminal (e.g., negative correction terminal) of the hysteresis comparator 424 is coupled to the second current source circuit 422 for receiving the second bias current Ib2. The output terminal of the hysteresis comparator 424 is used for outputting the control signal Spwm1. The hysteresis comparator 424 is configured to generate the control signal Spwm1 according to the node signal S4, the first bias current Ib1 and/or the second bias current Ib2, and can control the delay capacitor C41 to charge or discharge according to the magnitude of the first bias current Ib1 and/or the second bias current Ib, so as to adjust the phase of the node signal S4.

In one embodiment, hysteresis comparator 424 may also be implemented by a schmitt trigger, the voltage characteristics of which are shown in fig. 4B, as described above. The first threshold voltage VTH of the hysteresis comparator 424 is controlled by the second bias current Ib2 to change, for example, when the second bias current Ib2 increases, the first threshold voltage VTH also increases; similarly, the second threshold voltage VTL is controlled by the first bias current Ib1 to change, for example, when the first bias current Ib1 increases, the second threshold voltage VTL decreases.

When the first error signal S1 is at a high level, the first bias current Ib1 increases, so that the second threshold voltage VTL decreases (refer to fig. 4B, from the change curve L41 to the change curve L42), and thus the time of the node signal from the high logic level to the low logic level can be delayed. On the other hand, when the second error signal S2 is at a high level, the second bias current Ib2 increases, so that the first threshold voltage VTH increases (refer to fig. 4B, from the change curve L43 to the change curve L44), thereby delaying the time of the node signal from the low logic level to the high logic level.

Referring to fig. 1A, fig. 2, and fig. 4A to fig. 4B, the following description describes the operation process of the delay circuit 420 for adjusting the bias current in the delay circuit according to the error signals (i.e. the first error signal S1 and the second error signal S2), thereby changing the duty cycle of the corresponding control signal Spwm 1. Under the positive half period of the power output stage circuit, i.e. when the response voltage Vea Is greater than the ramp voltage Vramp, the compensation signal Vcomp Is at a high level, the node signal S4 output by the inverter 423 should be converted to a low level, and if the output current Is1 Is greater than the average current Iavg, the error signal S1 Is at a high level and the error signal S2 Is at a low level, so as to control the first current source circuit 421 to increase the bias current Ib1 and control the second current source circuit 422 to decrease the bias current Ib2. When the first bias current Ib1 becomes larger and the second bias current Ib2 becomes smaller, the second threshold voltage VTL will be lowered and the first threshold voltage VTH will be increased. Therefore, as the second threshold voltage VTL decreases, the level of the control node NA (i.e., the node signal S4) needs to decrease to a lower level, so that the hysteresis comparator 324 converts the control signal Spwm1 to a high level, i.e., the time point when the control signal Spwm1 goes high is delayed, as shown in the waveform Spwm-B of fig. 2, and the time point when the control signal Spwm1 goes high is delayed from the original time point P1 to the time point P2. In this way, the duty cycle of the control signal Spwm1 is reduced. When the duty cycle of the control signal Spwm1 decreases, the on time of the upper bridge switch Ta becomes shorter, so that the output current Is1 Is reduced, and the current balance of each phase Is achieved.

For the positive half period of the power output stage 110, if the output current Is1 Is smaller than the average current Iavg, the first bias current Ib1 Is decreased and the second bias current Ib2 Is increased, so that the second threshold voltage VTL (only the first threshold voltage VTH Is increased) Is not affected, and thus the time when the node signal S4 Is converted into the control signal Spwm1 with the high level Is not affected, i.e. the control signal Spwm1 still enters the high level at the time point P1, so that the time point when the waveform Spwm-C enters the high level Is the same as the time point when the waveform Spwm-a enters the high level under the positive half period.

Next, as shown in fig. 2, under the negative half period of the operation of the power output stage 110, i.e. when the response voltage Vea Is smaller than the ramp voltage Vramp, the compensation signal Vcomp Is at a low level, the node signal S4 outputted by the inverter 423 should be changed to a high level, and if the output current Is1 Is smaller than the average current Iavg, the first error signal S1 Is at a low level and the second error signal S2 Is at a high level, so as to control the first current source circuit 421 to decrease the first bias current Ib1 and control the second current source circuit 322 to increase the second bias current Ib2, respectively. When the first bias current Ib1 becomes smaller and the second bias current Ib2 becomes larger, the first threshold voltage VTH is raised. Therefore, the node signal S4 should rise to a higher level to be converted into the control signal Spwm1 having a low level, i.e. the time point when the control signal Spwm1 goes low is delayed, as shown by the waveform Spwm-C in FIG. 2, and the time point when the control signal Spwm1 falls to a low level is delayed from the original time point P3 to the time point P4. This corresponds to an increase in the duty cycle of Spwm 1. When the duty cycle of Spwm1 increases, the on time of the upper bridge switch Ta becomes longer, so as to promote Is1 and achieve the effect of current balance of each phase.

For the negative half cycle of the power output stage 110, if the output current Is1 Is greater than the average current Iavg, the first bias current Ib1 Is raised and the second bias current Ib2 Is lowered, so that the first threshold voltage VTH Is not affected (only the second threshold voltage VTL Is pulled down), i.e. the time point when the node signal Is converted into the control signal Spwm1 with the low level Is not affected (still the time point P3), so that the time when the waveform Spwm-B goes low Is the same as the time when the waveform Spwm-a goes low during the negative half cycle.

In the foregoing embodiment, the voltage regulator circuit 400 includes the first current comparator 411, the second current comparator 412, the first current source circuit 421 and the second current source circuit 422.

The first current comparator 411 and the corresponding first current source circuit 421 are used for generating a first bias current Ib1 to change the first threshold voltage VTH and the second threshold voltage VTL of the hysteresis comparator 424. Similarly, the second current comparator 412 and the corresponding second current source circuit 422 are also configured to generate a second bias current Ib2 to change the first threshold voltage VTH and the second threshold voltage VTL of the hysteresis comparator 424. However, in other embodiments, the voltage regulator circuit 400 may also only have the first bias current Ib1 or the second bias current Ib2, i.e. the first threshold voltage VTH and the second threshold voltage VTL of the hysteresis comparator 424 may be changed. In other words, in other embodiments, the voltage regulator circuit 400 may include only the first current comparator 411 and the corresponding first current source circuit 421, or only the second current comparator 412 and the corresponding second current source circuit 422.

In summary, the duty cycle of the control signal Spwm1 Is adjusted by the difference between the first output current Is1 and the average current Iavg to achieve the technical effect of equalizing the output currents of each phase, without changing the level of the response voltage Vea or the ramp voltage Vramp. In contrast, the background art must change the level of the response voltage Vea or the ramp voltage Vramp to adjust the duty cycle of the control signal Spwm 1.

The elements, method steps or technical features of the foregoing embodiments may be combined with each other, and are not limited to the text description order or the drawing presentation order in the present disclosure.

While the present utility model has been described with reference to the above embodiments, it should be understood that the utility model is not limited thereto, but may be variously modified and modified by those skilled in the art without departing from the spirit and scope of the present utility model, and thus the scope of the present utility model is defined by the appended claims.

[ Symbolic description ]

100-Multiphase DC-DC converter

110 Power output stage circuit

111 Switch circuit

120 Current balancing circuit

121 Current detection circuit

121A transfer circuit

121B adder circuit

121C divider circuit

121D subtractor circuit

122 Multiphase voltage stabilizer

130 Compensation circuit

140 Energy storage circuit

150 Voltage divider circuit

200 Voltage stabilizer circuit

210 Current comparison circuit

220 Delay circuit

300 Voltage stabilizer circuit

310 Current comparison circuit

311 First current comparator

312 Second current comparator

320 Delay circuit

321 First current source circuit

322 Second current source circuit

323 Inverter

324 Hysteresis comparator

400 Voltage stabilizer circuit

410 Current comparison circuit

411 First current comparator

412 Second current comparator

420 Delay circuit

421 First current source circuit

422 Second current source circuit

423 Inverter

424 Hysteresis comparator

C31 delay capacitor

C41 delay capacitor

Cout output capacitance

DC-drive circuit

Iavg average current

Idiff1-Idiffn error Current

Is1-Isn output current

Ib1-Ib2 bias current

L1-Ln inductor

L31-L32 change curve

L41-L44 change curve

Lx1-Lxn Voltage

N1-Nn phase node

NA control node

P1-P4 time points

R1-R2 divider resistor

S1-S2 error Signal

S3-S4 node signals

Spwm1-Spwmn control signal

Spwm-A waveform

Spwm-B waveform

Spwm-C waveform

Ta upper bridge switch

Tb lower bridge switch

Vramp, ramp voltage

Vcomp compensation signal

Vfb feedback voltage

Vin: input voltage

Vout output Voltage

Vcc power supply

Vea response voltage

VTH threshold voltage

VTL, threshold voltage.

Claims (10)

1. A multiphase voltage regulator coupled to a multiphase dc-dc converter, comprising:

The voltage stabilizer circuits are coupled between the power output stage circuit and the compensation circuit of the multiphase direct current-direct current converter and are used for generating a plurality of control signals according to the compensation signals so as to enable the power output stage circuit to generate a plurality of output currents;

wherein one of the plurality of voltage regulator circuits comprises:

A current comparison circuit for obtaining an error signal, wherein the error signal is a difference between a threshold current and a corresponding one of the plurality of output currents; and

And the delay circuit is coupled to the compensation circuit and the current comparison circuit and is used for generating a corresponding one of the plurality of control signals according to the compensation signal, wherein the delay circuit is used for adjusting the bias current in the delay circuit according to the error signal so as to adjust the duty cycle of the corresponding one of the plurality of control signals.

2. The multiphase voltage regulator of claim 1, wherein the delay circuit comprises a first current source circuit to provide a first bias current, and wherein the current comparison circuit comprises:

A first current comparator, a first end of the first current comparator is configured to receive the threshold current, a second end of the first current comparator is configured to receive the corresponding one of the plurality of output currents, and the first current comparator outputs a first error signal to the first current source circuit to change the first bias current.

3. The multiphase voltage regulator of claim 2, wherein the delay circuit comprises a second current source circuit to provide a second bias current, and wherein the current comparison circuit comprises:

A second current comparator, a first end of the second current comparator being configured to receive the corresponding one of the plurality of output currents, a second end of the second current comparator being configured to receive the threshold current, and the second current comparator outputting a second error signal to the second current source circuit to change the second bias current.

4. A multiphase voltage regulator of claim 3, wherein the threshold current is an average current of the plurality of output currents.

5. The multiphase voltage regulator of claim 4, wherein the delay circuit further comprises:

an inverter having an input terminal, an output terminal, a first correction terminal and a second correction terminal, wherein the input terminal of the inverter is coupled to the output terminal of the compensation circuit to receive the compensation signal, the first correction terminal of the inverter is configured to receive the first bias current, the second correction terminal of the inverter is configured to receive the second bias current, and the output terminal of the inverter is configured to output a node signal, wherein the first bias current and the second bias current are configured to adjust a phase of the node signal; and

A delay capacitor coupled between the output terminal of the inverter and a reference potential, wherein the delay capacitor is configured to delay a time when the node signal goes from a high logic level to a low logic level when the error signal is at a high level; when the error signal is at a low level, the delay capacitor is used for delaying the time when the node signal enters a high logic level from a low logic level.

6. The multiphase voltage regulator of claim 5, wherein the delay circuit further comprises:

And the hysteresis comparator is coupled to the output end of the inverter and used for generating a corresponding one of the control signals according to the node signal.

7. The multiphase voltage regulator of claim 4, wherein the delay circuit further comprises:

The inverter is provided with an input end and an output end, wherein the input end of the inverter is used for receiving the compensation signal, and the output end of the inverter is used for outputting a node signal.

8. The multiphase voltage regulator of claim 7, wherein the delay circuit further comprises:

A hysteresis comparator coupled to the output of the inverter, the hysteresis comparator having an input, an output, a first correction, and a second correction, the input of the hysteresis comparator being coupled to the output of the inverter to receive the node signal from the inverter; the first correction end of the hysteresis comparator is used for receiving the first bias current; the second correction end of the hysteresis comparator is used for receiving the second bias current, wherein the hysteresis comparator is used for generating a corresponding one of the control signals according to the node signal, the first bias current and the second bias current.

9. The multiphase voltage regulator of claim 8, wherein a first threshold voltage and a second threshold voltage of the hysteresis comparator vary according to the first bias current and the second bias current, wherein the second threshold voltage is reduced to delay a time for the node signal to go from a high logic level to a low logic level when the error signal is at a high level; when the error signal is low, the first threshold voltage will rise to delay the time the node signal goes from low to high logic.

10. A multiphase current balancing circuit for a multiphase dc-dc converter, comprising:

The current detection circuit is coupled to the power output stage circuit of the multiphase direct current-direct current converter so as to obtain a plurality of output currents and threshold currents; and

The voltage stabilizer circuits are coupled between the current detection circuit and the compensation circuit of the multiphase direct current-direct current converter and are used for generating a plurality of control signals according to the compensation signals so as to enable the power output stage circuit to generate a plurality of output currents;

wherein one of the plurality of voltage regulator circuits comprises:

A current comparison circuit for obtaining an error signal, wherein the error signal is a difference between the threshold current and a corresponding one of the plurality of output currents; and

And the delay circuit is coupled to the compensation circuit and the current comparison circuit and is used for generating a corresponding one of the plurality of control signals according to the compensation signal, wherein the delay circuit is used for adjusting the bias current in the delay circuit according to the error signal so as to adjust the duty cycle of the corresponding one of the plurality of control signals.