CN221575155U - Multiphase voltage stabilizer and current balance circuit - Google Patents

Abstract

The utility model provides a multi-phase voltage regulator and a current balancing circuit. A multi-phase voltage regulator is coupled to a multi-phase DC-DC converter and includes multiple voltage regulator circuits. The voltage regulator circuit is coupled between the power output stage circuit and the compensation circuit to generate multiple control signals according to the compensation signal so that the power output stage circuit generates multiple output currents. The voltage regulator circuit includes a current comparison circuit and a delay circuit. The current comparison circuit is used to obtain an error signal. The error signal is the difference between the threshold current and the corresponding output current. The delay circuit is coupled to the compensation circuit and the current comparison circuit to generate a corresponding control signal according to the compensation signal. The delay circuit is used to adjust the bias current in the delay circuit according to the error signal to adjust the duty cycle of the corresponding control signal. Accordingly, the balanced control of each phase current can be achieved.

Description

Multiphase voltage regulator and current balancing circuit

Technical Field

The utility model relates to a current balancing technology, and in particular to a multi-phase voltage stabilizer and a current balancing circuit.

Background Art

A DC-to-DC converter is an electromechanical device used for power conversion, which is used to convert the voltage of a DC power source. DC-to-DC converters are widely used and can be used to supply power to low-power devices (such as batteries) or high-power devices (such as industrial machines). Among them, a multi-phase DC-to-DC converter includes multiple converters of different phases to output power to the output end in turn. Whether the output power between the converters of each phase is maintained consistent will affect the power supply stability of the DC-to-DC converter. Therefore, there is a real need for a novel DC-to-DC converter to provide better power supply stability.

Utility Model Content

The utility model relates to a multi-phase voltage regulator, which is coupled to a multi-phase DC-DC converter and includes a plurality of voltage regulator circuits. The voltage regulator circuit is coupled between a power output stage circuit and a compensation circuit of the multi-phase DC-DC converter, and is used to generate a plurality of control signals according to a compensation signal, so that the power output stage circuit generates a plurality of output currents. One of the plurality of voltage regulator circuits includes a current comparison circuit and a delay circuit. The current comparison circuit is used to obtain an error signal. The error signal is the difference between a threshold current and a corresponding one of the plurality of output currents. The delay circuit is coupled to the compensation circuit and the current comparison circuit, and is used to generate a corresponding one of the plurality of control signals according to the compensation signal. The delay circuit is used to adjust a bias current in the delay circuit according to the error signal, so as to adjust a duty cycle of a corresponding one of the plurality of control signals.

In one embodiment, the delay circuit includes a first current source circuit to provide a first bias current, and the current comparison circuit includes a first current comparator. A first end of the first current comparator is used to receive a threshold current, a second end of the first current comparator is used to receive a corresponding one of the plurality of output currents, and the first current comparator outputs a first error signal to the first current source circuit to change the first bias current.

In one embodiment, the delay circuit includes a second current source circuit to provide a second bias current, and the current comparison circuit includes a second current comparator. A first end of the second current comparator is used to receive a corresponding one of the plurality of output currents, a second end of the second current comparator is used to receive a threshold current, and the second current comparator outputs a second error signal to the second current source circuit to change the second bias current.

In one embodiment, the threshold current is an average current of the plurality of output currents.

In one embodiment, the delay circuit further includes an inverter and a delay capacitor. The inverter has an input terminal, an output terminal, a first correction terminal and a second correction terminal. The input terminal of the inverter is coupled to the output terminal of the compensation circuit to receive the compensation signal, the first correction terminal of the inverter is used to receive the first bias current, the second correction terminal of the inverter is used to receive the second bias current, and the output terminal of the inverter is used to output the node signal. The first bias current and the second bias current are used to adjust the phase of the node signal. The delay capacitor is coupled between the output terminal of the inverter and the reference potential. When the error signal is at a high level, the delay capacitor is used to delay the time for the node signal to enter a low logic level from a high logic level. When the error signal is at a low level, the delay capacitor is used to delay the time for the node signal to enter a high logic level from a low logic level.

In one embodiment, the delay circuit further comprises a hysteresis comparator. The hysteresis comparator is coupled to the output terminal of the inverter and is used to generate a corresponding one of the plurality of control signals according to the node signal.

In one embodiment, the delay circuit further includes an inverter having an input terminal and an output terminal, wherein the input terminal of the inverter is used to receive the compensation signal, and the output terminal of the inverter is used to output the node signal.

In one embodiment, the delay circuit further includes a hysteresis comparator. The hysteresis comparator is coupled to the output end of the inverter. The hysteresis comparator has an input end, an output end, a first correction end and a second correction end. The input end of the hysteresis comparator is coupled to the output end of the inverter to receive a node signal from the inverter. The first correction end of the hysteresis comparator is used to receive a first bias current. The second correction end of the hysteresis comparator is used to receive a second bias current. The hysteresis comparator is used to generate a corresponding one of the multiple control signals according to the node signal, the first bias current and the second bias current.

In one embodiment, the first threshold voltage and the second threshold voltage of the hysteresis comparator are changed according to the first bias current and the second bias current. When the error signal is at a high level, the second threshold voltage will be reduced to delay the time for the node signal to enter a low logic level from a high logic level. When the error signal is at a low level, the first threshold voltage will be increased to delay the time for the node signal to enter a high logic level from a low logic level.

The present invention also relates to a multi-phase current balancing circuit, which is applied to a multi-phase DC-DC converter, and includes a current detection circuit and a plurality of voltage regulator circuits. The current detection circuit is coupled to the power output stage circuit of the multi-phase DC-DC converter to obtain a plurality of output currents and a threshold current. The voltage regulator circuit is coupled between the current detection circuit and the compensation circuit of the multi-phase DC-DC converter, and is used to generate a plurality of control signals according to the compensation signal so that the power output stage circuit generates the plurality of output currents. One of the plurality of voltage regulator circuits includes a current comparison circuit and a delay circuit. The current comparison circuit is used to obtain an error signal. The error signal is the difference between the threshold current and a corresponding one of the plurality of output currents. The delay circuit is coupled to the compensation circuit and the current comparison circuit, and is used to generate a corresponding one of the plurality of control signals according to the compensation signal. The delay circuit is used to adjust the bias current in the delay circuit according to the error signal to adjust the duty cycle of a corresponding one of the plurality of control signals.

The present invention adjusts the duty cycle of the control signal by the difference between the first output current and the average current to achieve the technical effect of balancing the output currents of each phase without changing the level of the response voltage or the ramp voltage. In contrast, the background technology must change the level of the response voltage or the ramp voltage to adjust the duty cycle of the control signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic diagram of a multi-phase DC-DC converter according to some embodiments of the present invention.

FIG. 1B is a schematic diagram of a current detection circuit according to some embodiments of the present invention.

FIG. 2 is a waveform diagram of a control signal according to some embodiments of the present invention.

FIG. 3A is a schematic diagram of a voltage regulator circuit according to some embodiments of the present invention.

FIG. 3B is a schematic diagram of voltage characteristics of a hysteresis comparator according to some embodiments of the present invention.

FIG. 4A is a schematic diagram of a voltage regulator circuit according to some embodiments of the present invention.

FIG. 4B is a schematic diagram of voltage characteristics of a hysteresis comparator according to some embodiments of the present invention.

DETAILED DESCRIPTION

The following will disclose multiple embodiments of the present invention with the accompanying drawings. For the purpose of clear description, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present invention. In other words, in some embodiments of the present invention, these practical details are not necessary. In addition, in order to simplify the drawings, some conventional structures and elements will be illustrated in a simple schematic manner in the drawings.

In this document, when an element is referred to as "connected" or "coupled", it may refer to "electrically connected" or "electrically coupled". "Connected" or "coupled" may also be used to indicate that two or more elements cooperate or interact with each other. In addition, although the terms "first", "second", etc. are used in this document to describe different elements, the terms are only used to distinguish between elements or operations described by the same technical terms. Unless the context clearly indicates otherwise, the terms do not specifically refer to or imply an order or sequence, nor are they used to limit the present invention.

The present invention relates to a multi-phase DC-DC converter for converting an input voltage to output an output voltage of different voltages. In one embodiment, the multi-phase DC-DC converter is applied to a vehicle power supply, for example, as a power transmission circuit, which can store the power of a charging pile in a battery, or provide the stored power of the battery to in-vehicle equipment. However, the present invention is not limited to this, and in other embodiments, the multi-phase DC-DC converter can also be applied to other devices and loads.

FIG1A is a schematic diagram of a multi-phase DC-DC converter 100 according to some embodiments of the present invention. The multi-phase DC-DC converter 100 includes a power output stage circuit 110, a current balancing circuit 120, and a compensation circuit 130. The power output stage circuit 110 includes a plurality of driving circuits DC and a switch circuit 111 formed by a plurality of transistor switches, wherein each driving circuit DC and the corresponding switch circuit 111 are used to generate corresponding output currents Is1 to Isn according to an input voltage Vin.

In the embodiment shown in FIG. 1A , the power output stage circuit 110 includes a plurality of sub-circuits (e.g., two or more), each sub-circuit includes a driving circuit DC, and the switch circuit 111 includes an upper bridge switch Ta and a lower bridge switch Tb, and is coupled to an input voltage Vin. The driving circuit DC is used to control the upper bridge switch Ta and the lower bridge switch Tb to be turned on or off according to a received control signal, so as to generate or adjust the corresponding output currents Is1 to Isn. The phases of the output currents Is1 to Isn generated by each sub-circuit may be different from each other. For example, when the power output stage circuit 110 includes a plurality of sub-circuits, there is a predetermined phase difference between the output currents of adjacent sub-circuits.

In one embodiment, the power output stage circuit 110 generates an output voltage Vout and a feedback voltage Vfb through an energy storage circuit 140 and a voltage divider circuit 150. The energy storage circuit 140 is coupled to the output end of the power output stage circuit 110, and includes a plurality of inductors L1-Ln and an output capacitor Cout for generating an output voltage Vout according to the output currents Is1-Isn. The voltage divider circuit 150 is coupled to the power output stage circuit 110 and the energy storage circuit 140, and includes a plurality of voltage divider resistors R1 and R2 for dividing the output voltage Vout to generate a feedback voltage Vfb. Since those skilled in the art can understand the manner in which the multi-phase DC-DC converter 100 generates the output voltage Vout, further details are not described herein.

The current balancing circuit 120 is coupled to the power output stage circuit 110, and includes a current detection circuit 121 and a multi-phase regulator 122. The current balancing circuit 120 is used to generate and adjust a plurality of control signals Spwm1-Spwmn corresponding to different phases, so that the power output stage circuit 110 generates a plurality of output currents Is1-Isn of different phases, thereby keeping the currents of each phase balanced. The generation method of the control signal will be described in detail in the following paragraphs.

The current balancing circuit 120 is coupled to the compensation circuit 130 and the power output stage circuit 110. The compensation circuit 130 is used to receive the response voltage Vea from the power output stage circuit 110 and generate a compensation signal Vcomp. The response voltage Vea is generated according to the difference between the feedback voltage Vfb provided by the output terminal of the multi-phase DC-DC converter 100 and a reference voltage (e.g., a reference voltage or a preset fixed voltage). Specifically, in one embodiment, the feedback voltage Vfb generated by the power output stage circuit 110 is subtracted from the reference voltage to obtain the response voltage Vea. In other embodiments, the power output stage circuit 110 may also directly use the feedback voltage Vfb as the response voltage Vea.

The compensation circuit 130 is used to compare the response voltage Vea with the ramp voltage Vramp to generate a compensation signal Vcomp according to the difference between the response voltage Vea and the ramp voltage Vramp. The compensation signal Vcomp is used to reflect the current state of the output voltage Vout (e.g., heavy load or light load state). When the compensation signal Vcomp is provided to the current balancing circuit 120, the current balancing circuit 120 generates control signals Spwm1-Spwmn according to the compensation signal Vcomp.

As mentioned above, in one embodiment, the positive terminal of the compensation circuit 130 is used to receive the response voltage Vea, and the negative terminal of the compensation circuit 130 is used to receive the ramp voltage Vramp. Therefore, the magnitude of the compensation signal Vcomp is positively correlated with the “difference between the response voltage Vea and the ramp voltage Vramp”. However, the present invention is not limited thereto. In other embodiments, the signals received by the positive and negative terminals of the compensation circuit 130 can be interchanged according to the actual circuit design.

In one embodiment, the ramp voltage Vramp is a periodic signal, and its signal size changes periodically within a time period. In other embodiments, the ramp voltage Vramp may be a sawtooth wave with a fixed slope in the signal cycle. "Sawtooth wave" means that in each signal cycle, it will change from a fixed level (such as rising or falling), and when the current signal cycle ends and enters the next signal cycle, it will return to the original fixed level. In some embodiments, the signal slope of the ramp voltage Vramp is positive, that is, in the signal cycle, the level of the ramp voltage Vramp gradually increases. However, the content of the utility model is not limited to this. In other embodiments, depending on the slope, the ramp voltage Vramp may also be a triangular wave.

In one embodiment of the present invention, a plurality of voltage regulator circuits 200 are disposed in the current balancing circuit 120. The voltage regulator circuit 200 can selectively change the level change time of the control signals Spwm1-Spwmn according to the power supply state of the multi-phase DC-DC converter 100 (e.g., according to the compensation signal Vcomp and/or the magnitude of the output current) to ensure that the current of each phase outputted by the multi-phase DC-DC converter 100 can be kept balanced (i.e., the output current of each phase can be kept substantially equal). For ease of explanation, the plurality of voltage regulator circuits 200 corresponding to the multi-phases in the multi-phase DC-DC converter 100 are collectively referred to as "multi-phase voltage regulators".

As shown in FIG1A , in this embodiment, the current balancing circuit 120 includes a current detection circuit 121 and a multi-phase regulator 122. The current detection circuit 121 is coupled to the power output stage circuit 110 to obtain the output currents Is1 to Isn and the threshold current. The current detection circuit 121 is also used to generate a plurality of error signals provided to the plurality of regulator circuits 200 according to the threshold current and the output currents Is1 to Isn.

In one embodiment, the threshold current is an average value or a median value of a plurality of driving currents generated by the power output stage circuit 110. In other words, the threshold current is calculated and generated by the current detection circuit 121, but the content of the utility model is not limited thereto. In other embodiments, the threshold current may also be a preset fixed current value, such as the ideal current value output by each phase power output stage circuit 110 when the multi-phase DC-DC converter 100 is in normal operation. In other embodiments, the threshold current may be obtained by looking up a table, for example, looking up the corresponding output current Is1 to Isn values according to the level of the input voltage Vin.

In one embodiment, the error signal is the difference between the threshold current and each output current, such as the error currents Idiff1 to Idiffn shown in FIG1A . In other embodiments, the current detection circuit 121 is used to perform signal processing on the threshold current and the corresponding output current to generate an error signal, which is output to the corresponding regulator circuit 200 respectively.

Specifically, in some embodiments, the current detection circuit 121 can detect the phase nodes N1~Nn between the upper bridge switch Ta and the lower bridge switch Tb in the power output stage circuit 110 to obtain the voltages Lx1~Lxn of the phase nodes N1~Nn, and then calculate the corresponding output current. At the same time, the current detection circuit 121 can also calculate the average current of multiple output currents as a threshold current.

FIG1B is a schematic diagram of a current detection circuit 121 according to some embodiments of the present invention. As shown in FIG1A and FIG1B , the current detection circuit 121 includes a transconductance circuit 121a, an adder circuit 121b, a divider circuit 121c, and a subtractor circuit 121d. The transconductance circuit 121a is coupled to the power output stage circuit 110 to receive the output currents Is1 to Isn. In one embodiment, the transconductance circuit 121a includes a transconductance amplifier to receive the voltages Lx1 to Lxn of the phase nodes N1 to Nn and then calculate the output currents Is1 to Isn.

The adder circuit 121b is coupled to the transconductance circuit 121a, and is used to receive the output currents Is1 to Isn, and calculate the average current Iavg of the output currents Is1 to Isn through the divider circuit 121c. The subtractor circuit 121d is coupled to the divider circuit 121c, and is used to calculate the difference between the output current of the corresponding phase and the average current Iavg to generate error currents Idiff1 to Idiffn.

The multi-phase regulator 122 includes a plurality of regulator circuits 200, which are coupled between the compensation circuit 130 and the current detection circuit 121, and are used to receive the error signal and the compensation signal Vcomp. As mentioned above, the error signal provided by the current detection circuit 121 can be the error current Idiff1-Idiffn calculated by the current detection circuit 121, or can be the operation result of the threshold current and the corresponding output current provided by the current detection circuit 121. The multi-phase regulator 122 is used to generate a plurality of control signals Spwm1-Spwmn corresponding to different phases according to the error signal and the compensation signal Vcomp, so that the power output stage circuit 110 generates the output current Is1-Isn. In addition, the regulator circuit 200 can also selectively change the level change time point of the corresponding control signal (e.g., delay or advance) so that the plurality of output currents Is1-Isn between different phases can be balanced.

In one embodiment, the multi-phase regulator 122 includes a plurality of regulator circuits 200 , each of which is used to generate a control signal Spwm1 ˜Spwmn of an output current Is1 ˜Isn of a corresponding phase, so as to provide the control signal Spwm1 ˜Spwmn to each driving circuit DC.

In some embodiments, the control signals Spwm1-Spwmn generated by each voltage regulator circuit 200 are pulse-width modulation (PWM) signals. The voltage regulator circuit 200 can also adjust the duty ratio (duty ratio, also known as duty cycle) of the control signals Spwm1-Spwmn, thereby changing the magnitude of the output currents Is1-Isn generated by the power output stage circuit 110. Since those skilled in the art can understand the method of transmitting control signals between the power output stage circuit 110 and the current balancing circuit by digital signals, it will not be further described here.

FIG2 shows some embodiments of the present invention, illustrating the concept of "ensuring that the currents of each phase output by the multi-phase DC-DC converter 100 are balanced by controlling the time point of the level change of the control signals Spwm1 to Spwmn". Please refer to FIG1A and FIG2, where the current balancing circuit 120 and the regulator circuit 200 for controlling the output current Is1 are used as examples for illustration. In FIG2, the waveforms Spwm-A to Spwm-C respectively represent the waveform changes of the control signal Spwm1 under different circumstances. The waveform Spwm-A represents the waveform when "the output current Is1 is equal to the average current Iavg". The waveform Spwm-B represents the waveform to which the control signal Spwm1 should be adjusted (i.e., the duty cycle is reduced) when "the output current Is1 is greater than the average current Iavg". The waveform Spwm-C represents the waveform to which the control signal Spwm1 should be adjusted (i.e., the duty cycle is increased) when "the output current Is1 is less than the average current Iavg".

As shown in FIG2 , the time point when the response voltage Vea and the ramp voltage Vramp are at the same level will be the time point when the level of the control signal Spwm1 changes. In other words, the “time point when the response voltage Vea and the ramp voltage Vramp are at the same level” is associated with the duty cycle of the control signal Spwm1. As shown in the waveform Spwm-A, when the response voltage Vea decreases from a high level to the level of the ramp voltage Vramp (i.e., time point P1), the control signal Spwm1 will change from a low level to a high level. When the response voltage Vea increases from a low level to the level of the ramp voltage Vramp (i.e., time point P3), the control signal Spwm1 will change from a high level to a low level. Please note that the present invention does not adjust the duty cycle of the control signal Spwm1 by changing the level of the response voltage Vea or the ramp voltage Vramp, but adjusts the duty cycle of the control signal Spwm1 by the difference between the output current Is1 and the average current Iavg, so as to achieve the technical effect of balancing the output current of each phase.

Please refer to FIG. 2 , for example, in the positive half cycle of the power output stage circuit 110 (in terms of the waveform Spwm-A, the positive half cycle is from time point P1 to time point P3), when the control signal Spwm1 is at a high level and the ramp voltage Vramp is lower than the response voltage Vea, the upper bridge switch Ta is turned on and the lower bridge switch Tb is turned off, and the input voltage Vin charges the output capacitor Cout and the inductor L1, forming an output current Is1 flowing from the phase node N1 to the output capacitor Cout. Then, the current detection circuit 121 receives the voltages Lx1 to Lxn of the phase nodes N1 to Nn, and calculates the output currents Is1 to Isn according to the voltages Lx1 to Lxn. As shown in FIG. 1B and FIG. 2 , the current detection circuit 121 compares the output currents Is1 to Isn with the current average value of these currents (i.e., the average current Iavg or the aforementioned threshold current). For example, when the output current Is1 is greater than the average current Iavg, the duty cycle of the control signal Spwm1 should be reduced to reduce the output current Is1. Therefore, the voltage regulator circuit 200 corresponding to the control signal Spwm1 can delay the time point when the control signal Spwm1 "rises from a low level to a high level" (such as: waveform Spwm-B, delayed from time point P1 to time point P2) to reduce the duty cycle of the control signal Spwm1. In this way, by reducing the duty cycle of the control signal Spwm1, that is, the time when the upper bridge switch Ta is turned on becomes shorter, the output current Is1 can be reduced.

Similarly, when the output current Is1 is less than the average current Iavg, the duty cycle of the control signal Spwm1 should be increased to increase the output current Is1. Therefore, the voltage regulator circuit 200 corresponding to the control signal Spwm1 can delay the time point when the control signal Spwm1 "drops from a high level to a low level" (such as the waveform Spwm-C, delayed from time point P3 to time point P4) to increase the duty cycle of the control signal Spwm1. In this way, by increasing the duty cycle of the control signal Spwm1, that is, the time when the upper bridge switch Ta is turned on becomes longer, the output current Is1 can be increased.

The following is a description of the method and corresponding circuit for the voltage regulator circuit 200 to adjust the time point at which the control signals Spwm1-Spwmn change their levels. As shown in FIG1A , the voltage regulator circuit 200 includes a current comparison circuit 210 and a delay circuit 220, and the current comparison circuit 210 is coupled to the delay circuit 220. The current comparison circuit 210 is coupled to the current detection circuit 121 to obtain an error signal, such as receiving a corresponding one of the error currents Idiff1-Idiffn from the current detection circuit 121, or receiving a threshold current (e.g., current average value, refer to the average current Iavg in FIG3A ) and a corresponding output current (refer to the output current Is1 in FIG3A ) from the current detection circuit 121.

The delay circuit 220 is coupled to the compensation circuit 130 and the current comparison circuit 210 to generate a corresponding control signal according to the compensation signal Vcomp. The delay circuit 220 is also used to adjust the bias current in the delay circuit according to the error signal (e.g., the corresponding error current Idiff1, or the average current Iavg and the output current Is1 as shown in the subsequent FIG. 1B and FIG. 3A) to adjust the duty cycle of the corresponding control signal.

The present invention utilizes an error signal to confirm the current state of each phase output current (e.g., too large or too small), and then selectively changes the level change time of the corresponding control signal, such as changing the time point when the control signal enters a high level, or changing the time point when the control signal enters a low level. Accordingly, the duty cycle of the control signal can be adjusted to achieve the purpose of maintaining a balance in the currents of each phase.

In some embodiments, the multi-phase DC-DC converter 100 can achieve the purpose of "controlling the level change time of the signal" by controlling the signal phase on the control node in the delay circuit 220. In other embodiments, the multi-phase DC-DC converter 100 can also achieve the purpose of "controlling the level change time of the signal" by controlling the threshold voltage of the circuit element in the delay circuit 220. The various control methods of the present utility model will be described through the embodiments of Figures 3A, 3B, 4A, and 4B.

FIG3A is a schematic diagram of a voltage regulator circuit 300 according to some embodiments of the present invention, which can be applied to the multi-phase DC-DC converter 100 shown in FIG1A . The voltage regulator circuit shown in FIG3A can be an example of the voltage regulator circuit 200 shown in FIG1A . The voltage regulator circuit 300 includes a current comparison circuit 310 and a delay circuit 320, wherein the current comparison circuit 310 is coupled to the delay circuit 320. The current comparison circuit 310 is coupled to the current detection circuit 121 to receive the average current Iavg and the output current Is1. The delay circuit 320 is coupled to the compensation circuit 130 and the current comparison circuit 310 to adjust the phase of the signal on the control node NA in the delay circuit 320 (hereinafter referred to as the node signal S3) according to the error signal to adjust the duty cycle of the corresponding control signal. Among them, the current comparison circuit 310 and the delay circuit 320 can be examples of the current comparison circuit 210 and the delay circuit 220, respectively.

As shown in FIG3A , in one embodiment, the current comparison circuit 310 includes a first current comparator 311. The first current comparator 311 is coupled to the current detection circuit 121, and its first terminal (e.g., negative terminal) is used to receive a threshold current (in this embodiment, the average current Iavg), and its second terminal (e.g., positive terminal) is used to receive the corresponding output current Is1. The first current comparator 311 generates a first error signal S1 according to the difference between the average current Iavg and the output current Is1.

As mentioned above, in one embodiment, the delay circuit 320 includes a first current source circuit 321 for providing a first bias current Ib1 according to the power supply Vcc. The first current source circuit 321 is also used to receive the first error signal S1 generated by the first current comparator 311, and change the magnitude of the output first bias current Ib1 according to the first error signal S1. In some embodiments, the first error signal S1 may be a voltage signal for changing the magnitude of the first bias current Ib1. In some other embodiments, the current comparison circuit 310 may be omitted. Under this configuration, the first current source circuit 321 and the second current source circuit 322 may be directly coupled to the current detection circuit 121 to receive a corresponding one of the error currents Idiff1-Idiffn, such as the error current Idiff1, and directly use the error current Idiff1 as the first error signal S1, and use the inverted error current Idiff1 as the second error signal S2; or, directly use the error current Idiff1 as the second error signal S2, and use the inverted error current Idiff1 as the first error signal S1.

Similarly, in one embodiment, the current comparison circuit 310 may further include a second current comparator 312. The second current comparator 312 is coupled to the current detection circuit 121 and the inverter 323, wherein a first end (e.g., a negative electrode) of the second current comparator 312 is used to receive the corresponding output current Is1, and a second end (e.g., a positive electrode) of the second current comparator 312 is used to receive a threshold current (in this embodiment, the average current Iavg). The second current comparator 312 generates a second error signal S2 according to the difference between the average current Iavg and the output current Is1.

As mentioned above, the delay circuit 320 further includes a second current source circuit 322 for providing a second bias current Ib2 according to the power supply Vcc. The second current source circuit 322 is coupled to the second current comparator 312 and the inverter 323, for receiving the second error signal S2 generated by the second current comparator 312, and changing the magnitude of the output second bias current Ib2 according to the second error signal S2. It is particularly mentioned here that the first current comparator 311 and the second current comparator 312 are both used to receive the corresponding output current Is1 and the average current Iavg, but the receiving positions (i.e., the positive and negative poles) are opposite, so the first error signal S1 and the second error signal S2 will be at different logic levels.

Specifically, as shown in FIG3A , the delay circuit 320 includes an inverter 323, a delay capacitor C31, and a hysteresis comparator 324. The input terminal of the inverter 323 is coupled to the output terminal of the compensation circuit 130 to receive the compensation signal Vcomp, and the output terminal of the inverter 323 is coupled to the control node NA to output the node signal. The first correction terminal of the inverter 323 is coupled to the first current source circuit 321 to receive the first bias current Ib1, and the second correction terminal of the inverter 323 is coupled to the second current source circuit 322 to receive the second bias current Ib2. The inverter 323 is used to control the charging or discharging of the delay capacitor C31 according to the first bias current and/or the second bias current to adjust the phase of the node signal of the control node NA.

The delay capacitor C31 is coupled between the output terminal (e.g., control node NA) of the inverter 323 and a reference potential (e.g., ground potential). The hysteresis comparator 324 is also coupled to the output terminal (control node NA) of the inverter 323 to generate a corresponding control signal Spwm1 according to the node signal S3. In one embodiment, the hysteresis comparator 324 can be implemented by a Schmitt trigger.

FIG3B shows a voltage characteristic diagram of the hysteresis comparator 324 in some embodiments, wherein the horizontal axis is the input voltage (i.e., the node signal S3) received by the hysteresis comparator 324, and the vertical axis is the output voltage (i.e., Spwm1) output by the hysteresis comparator 324. The voltage characteristic of the hysteresis comparator 324 presents a hysteresis curve. When the input voltage of the hysteresis comparator 324 rises to the first threshold voltage VTH, the output voltage will flip to a low level (as shown by the curve L31); when the input voltage of the hysteresis comparator 324 drops to the second threshold voltage VTL, the output voltage will flip to a high level (as shown by the change curve L32); and when the input voltage of the hysteresis comparator 324 is between the first threshold voltage VTH and the second threshold voltage VTL, the output voltage will not flip. Since those skilled in the art can understand the characteristics and implementation of the hysteresis comparator 324, more details are not repeated here.

Please refer to FIG. 1A, FIG. 2 and FIG. 3A-3B in combination, and the following describes the operation process of the delay circuit 320 adjusting the bias current in the delay circuit according to the error signal, thereby changing the duty cycle of the corresponding control signal. As shown in FIG. 2, in the positive half cycle of the power output stage circuit, that is, when the response voltage Vea is greater than the ramp voltage Vramp, the compensation signal Vcomp is at a high level, and the node signal S3 output by the inverter 323 should be changed to a low level. If the output current Is1 is greater than the average current Iavg at this time, the first error signal S1 is at a high level and the second error signal S2 is at a low level, so that the first current source circuit 321 is controlled to increase the first bias current Ib1 and the second current source circuit 322 is controlled to reduce the second bias current Ib2. When the first bias current Ib1 increases and the second bias current Ib2 decreases, the delay capacitor C31 will be additionally charged, so the time point when the node signal S3 drops to a low level (to at least the second threshold voltage VTL) will be slower, that is, the time point when the hysteresis comparator 324 converts the received node signal S3 with a low level into the control signal Spwm1 with a high level will be delayed, as shown in the waveform Spwm-B shown in FIG2 , at this time, the time point when the control signal Spwm1 rises to a high level will be delayed from the original time point P1 to the time point P2. In this way, it is equivalent to reducing the duty cycle of Spwm1. When the duty cycle of Spwm1 decreases, the conduction time of the upper bridge switch Ta becomes shorter, thereby reducing the output current Is1, achieving the effect of balancing the currents of each phase.

As for the positive half cycle of the power output stage circuit 110, please refer to the waveform Spwm-C. If the output current Is1 is less than the average current Iavg, the first bias current Ib1 will decrease and the second bias current Ib2 will increase. In this way, the delay capacitor C31 will be discharged smoothly. Therefore, the time when the node signal S3 enters the low level (low to at least the second threshold voltage VTL) is not affected, that is, the time when the control signal Spwm1 enters the high level is not affected. Therefore, in the positive half cycle, the time when the waveform Spwm-C enters the high level is the same as the time when the waveform Spwm-A enters the high level.

Next, as shown in FIG. 2 , in the negative half cycle of the power output stage circuit 110, that is, when the response voltage Vea is less than the ramp voltage Vramp, the compensation signal Vcomp is at a low level, and the node signal S3 outputted by the inverter 323 should be converted to a high level. If the output current Is1 is less than the average current Iavg at this time, the first error signal S1 is at a low level and the second error signal S2 is at a high level, respectively controlling the first current source circuit 321 to reduce the first bias current Ib1 and controlling the second current source circuit 322 to increase the second bias current Ib2. When the first bias current Ib1 decreases and the second bias current Ib2 increases, the delay capacitor C31 will be additionally discharged. Therefore, the time point when the node signal S3 level rises to a high level (must be as high as at least the first threshold voltage VTH to meet the voltage reversal condition, the principle can be referred to FIG. 3B) will be slowed down, that is, the time point when the hysteresis comparator 324 converts the received node signal S3 with a high level into the control signal Spwm1 with a low level will be delayed, as shown in the waveform Spwm-C shown in FIG. 2, at this time, the time point when the control signal Spwm1 drops to a low level will be delayed from the original time point P3 to the time point P4. In this way, it is equivalent to increasing the duty cycle of Spwm1. When the duty cycle of Spwm1 increases, the conduction time of the upper bridge switch Ta becomes longer, thereby increasing the output current Is1 and achieving the effect of balancing the currents of each phase.

As for the negative half cycle of the power output stage circuit 110, if the output current Is1 is greater than the average current Iavg, the first bias current Ib1 will increase and the second bias current Ib2 will decrease, so that the delay capacitor C31 can be charged smoothly. Therefore, the time for the node signal S3 to enter a high level (high to at least the first threshold voltage VTH) is not affected. Therefore, in the negative half cycle, the time for the waveform Spwm-B to enter a low level is the same as the time for the waveform Spwm-A to enter a low level.

In the aforementioned embodiment, the voltage regulator circuit 300 includes a first current comparator 311, a second current comparator 312, a first current source circuit 321, and a second current source circuit 322. The first current comparator 311 and the corresponding first current source circuit 321 are used to generate a first bias current Ib1 to change the phase change time of the node signal on the control node NA. Similarly, the second current comparator 312 and the corresponding second current source circuit 322 are also used to generate a second bias current Ib2 to change the phase change time of the node signal on the control node NA. However, in other embodiments, the voltage regulator circuit 300 may also only have the first bias current Ib1 or the second bias current Ib2, that is, to change the phase change time of the node signal on the control node NA. In other words, in other embodiments, the voltage regulator circuit 300 may only include the first current comparator 311 and the corresponding first current source circuit 321, or only include the second current comparator 312 and the corresponding second current source circuit 322.

FIG4A is a schematic diagram of a voltage regulator circuit 400 according to some embodiments of the present invention, which can be applied to the multi-phase DC-DC converter 100 shown in FIG1A. The voltage regulator circuit shown in FIG4A can be an example of the voltage regulator circuit 200 shown in FIG1A. The voltage regulator circuit 400 includes a current comparison circuit 410 and a delay circuit 420. The current comparison circuit 410 is coupled to the current detection circuit 121 to receive an error signal. The delay circuit 420 is coupled to the compensation circuit 130 and the current comparison circuit 410 to adjust the phase of the node signal on the control node NA in the delay circuit 420 according to the error signal to adjust the duty cycle of the corresponding control signal Spwm1. Among them, the current comparison circuit 410 and the delay circuit 420 can be examples of the current comparison circuit 210 and the delay circuit 220, respectively.

As shown in FIG. 4A , in one embodiment, the current comparison circuit 410 includes a first current comparator 411 and a second current comparator 412 , and the delay circuit 420 includes a first current source circuit 421 and a second current source circuit 422 .

The first current comparator 411 and the first current source circuit 421 are used to receive the average current Iavg and the corresponding output current Is1 from the current detection circuit 121 to generate the first bias current Ib1. The second current comparator 412 and the second current source circuit 422 are used to receive the average current Iavg and the corresponding output current Is1 from the current detection circuit 121 to generate the second bias current Ib2. In one embodiment, the circuits of the first current comparator 411, the first current source circuit 421, the second current comparator 412 and the second current source circuit 422 are respectively similar to the first current comparator 311, the first current source circuit 321, the second current comparator 312 and the second current source circuit 322 shown in FIG. 3A, so the details are not further described here.

4A , the delay circuit 420 includes an inverter 423, a delay capacitor C41, and a hysteresis comparator 424. The input terminal of the inverter 423 is coupled to the output terminal of the compensation circuit 130 to receive the compensation signal Vcomp, and the output terminal of the inverter 423 is coupled to the control node NA and the delay capacitor C41 to output the node signal S4.

The input end of the hysteresis comparator 424 is coupled to the output end of the inverter 423 to use the node signal S4 of the control node NA as an input voltage. The first correction end (e.g., positive correction end) of the hysteresis comparator 424 is coupled to the first current source circuit 421 to receive the first bias current Ib1. The second correction end (e.g., negative correction end) of the hysteresis comparator 424 is coupled to the second current source circuit 422 to receive the second bias current Ib2. The output end of the hysteresis comparator 424 is used to output the control signal Spwm1. The hysteresis comparator 424 is used to generate the control signal Spwm1 according to the node signal S4, the first bias current Ib1 and/or the second bias current Ib2, and can control the charging or discharging of the delay capacitor C41 according to the size of the first bias current Ib1 and/or the second bias current Ib2 to adjust the phase of the node signal S4.

In one embodiment, the hysteresis comparator 424 can also be implemented by a Schmitt trigger, and its voltage characteristics are shown in the aforementioned FIG4B. The first threshold voltage VTH of the hysteresis comparator 424 is changed by the control of the second bias current Ib2. For example, when the second bias current Ib2 increases, the first threshold voltage VTH also increases accordingly; similarly, the second threshold voltage VTL is changed by the control of the first bias current Ib1. For example, when the first bias current Ib1 increases, the second threshold voltage VTL decreases accordingly.

When the first error signal S1 is at a high level, the first bias current Ib1 will increase, thereby reducing the second threshold voltage VTL (refer to FIG. 4B , changing from the change curve L41 to the change curve L42), so that the time for the node signal to "go from a high logic level to a low logic level" can be delayed. On the other hand, when the second error signal S2 is at a high level, the second bias current Ib2 will increase, thereby increasing the first threshold voltage VTH (refer to FIG. 4B , changing from the change curve L43 to the change curve L44), so that the time for the node signal to "go from a low logic level to a high logic level" can be delayed.

Please refer to FIG. 1A, FIG. 2 and FIG. 4A-4B, and the following describes the operation process of the delay circuit 420 adjusting the bias current in the delay circuit according to the error signal (i.e., the first error signal S1 and the second error signal S2), thereby changing the corresponding duty cycle of the control signal Spwm1. In the positive half cycle of the power output stage circuit, that is, when the response voltage Vea is greater than the ramp voltage Vramp, the compensation signal Vcomp is at a high level, and the node signal S4 output by the inverter 423 should be changed to a low level. If the output current Is1 is greater than the average current Iavg at this time, the error signal S1 is at a high level and the error signal S2 is at a low level, respectively controlling the first current source circuit 421 to increase the bias current Ib1 and controlling the second current source circuit 422 to reduce the bias current Ib2. When the first bias current Ib1 increases and the second bias current Ib2 decreases, the second threshold voltage VTL will decrease and the first threshold voltage VTH will increase. Therefore, as the second threshold voltage VTL decreases, the level on the control node NA (i.e., the node signal S4) needs to decrease to a lower level before it is converted into a control signal Spwm1 with a high level by the hysteresis comparator 324, that is, the time point at which the control signal Spwm1 enters the high level is delayed, as shown in the waveform Spwm-B of FIG2 . At this time, the time point at which the control signal Spwm1 rises to the high level is delayed from the original time point P1 to the time point P2. In this way, it is equivalent to reducing the duty cycle of the control signal Spwm1. When the duty cycle of the control signal Spwm1 decreases, the conduction time of the upper bridge switch Ta becomes shorter, thereby reducing the output current Is1, achieving the effect of balancing the currents of each phase.

As for the positive half cycle of the power output stage circuit 110, if the output current Is1 is less than the average current Iavg, the first bias current Ib1 will decrease and the second bias current Ib2 will increase, which does not affect the second threshold voltage VTL (it only increases the first threshold voltage VTH). Therefore, the time when the node signal S4 is converted into a control signal Spwm1 with a high level is not affected, that is, the control signal Spwm1 still enters a high level at the time point P1. Therefore, in the positive half cycle, the time point when the waveform Spwm-C enters a high level is the same as the time point when the waveform Spwm-A enters a high level.

Next, as shown in FIG. 2 , in the negative half cycle of the power output stage circuit 110, that is, when the response voltage Vea is less than the ramp voltage Vramp, the compensation signal Vcomp is at a low level, and the node signal S4 outputted by the inverter 423 should be changed to a high level. If the output current Is1 is less than the average current Iavg at this time, the first error signal S1 is at a low level and the second error signal S2 is at a high level, respectively controlling the first current source circuit 421 to reduce the first bias current Ib1 and controlling the second current source circuit 322 to increase the second bias current Ib2. When the first bias current Ib1 decreases and the second bias current Ib2 increases, the first threshold voltage VTH increases. Therefore, the node signal S4 must rise to a higher level before it can be converted into a control signal Spwm1 with a low level, that is, the time point when the control signal Spwm1 enters the low level will be delayed, as shown in the waveform Spwm-C shown in Figure 2. At this time, the time point when the control signal Spwm1 drops to the low level will be delayed from the original time point P3 to the time point P4. In this way, it is equivalent to increasing the duty cycle of Spwm1. When the duty cycle of Spwm1 increases, the conduction time of the upper bridge switch Ta becomes longer, thereby increasing Is1 to achieve the effect of balancing the current of each phase.

As for the negative half cycle of the power output stage circuit 110, if the output current Is1 is greater than the average current Iavg, it will cause the first bias current Ib1 to rise and the second bias current Ib2 to drop, so the first threshold voltage VTH is not affected (only the second threshold voltage VTL is pulled down), that is, the time point when the node signal is converted into a control signal Spwm1 with a low level is not affected (still time point P3), so in the negative half cycle, the time when the waveform Spwm-B enters the low level is the same as the time when the waveform Spwm-A enters the low level.

In the aforementioned embodiment, the regulator circuit 400 includes a first current comparator 411 , a second current comparator 412 , a first current source circuit 421 , and a second current source circuit 422 .

The first current comparator 411 and the corresponding first current source circuit 421 are used to generate a first bias current Ib1 to change the first threshold voltage VTH and the second threshold voltage VTL of the hysteresis comparator 424. Similarly, the second current comparator 412 and the corresponding second current source circuit 422 are also used to generate a second bias current Ib2 to change the first threshold voltage VTH and the second threshold voltage VTL of the hysteresis comparator 424. However, in other embodiments, the voltage regulator circuit 400 may also only have the first bias current Ib1 or the second bias current Ib2, that is, the first threshold voltage VTH and the second threshold voltage VTL of the hysteresis comparator 424 can be changed. In other words, in other embodiments, the voltage regulator circuit 400 may only include the first current comparator 411 and the corresponding first current source circuit 421, or only include the second current comparator 412 and the corresponding second current source circuit 422.

In summary, the present invention adjusts the duty cycle of the control signal Spwm1 by the difference between the first output current Is1 and the average current Iavg to achieve the technical effect of balancing the output currents of each phase without changing the level of the response voltage Vea or the ramp voltage Vramp. In contrast, the background technology must change the level of the response voltage Vea or the ramp voltage Vramp to adjust the duty cycle of the control signal Spwm1.

The various elements, method steps or technical features in the aforementioned embodiments may be combined with each other, and are not limited to the order of textual description or the order of presentation of the drawings in the content of the utility model.

Although the contents of the present invention have been disclosed as above in the form of implementation methods, they are not intended to limit the contents of the present invention. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the contents of the present invention. Therefore, the protection scope of the contents of the present invention shall be determined by the definition of the attached claims.

【Explanation of symbols】

100:Multi-phase DC-DC converter

110: Power output stage circuit

111: Switching circuit

120: Current balancing circuit

121: Current detection circuit

121a: Transduction circuit

121b: Adder circuit

121c: Divider Circuit

121d: Subtractor circuit

122:Multi-phase regulator

130: Compensation circuit

140: Energy Storage Circuit

150: Voltage divider circuit

200: Voltage regulator circuit

210: Current comparison circuit

220: Delay circuit

300: Voltage regulator circuit

310: Current comparison circuit

311: first current comparator

312: Second current comparator

320: Delay circuit

321: First current source circuit

322: Second current source circuit

323: Inverter

324: Hysteresis Comparator

400: Voltage regulator circuit

410: Current comparison circuit

411: first current comparator

412: Second current comparator

420: Delay circuit

421: first current source circuit

422: Second current source circuit

423: Inverter

424: Hysteresis Comparator

C31: Delay capacitor

C41: Delay capacitor

Cout: output capacitance

DC: drive circuit

Iavg: average current

Idiff1-Idiffn: Error current

Is1-Isn: output current

Ib1-Ib2: Bias current

L1-Ln: Inductor

L31-L32: Change curve

L41-L44: Change curve

Lx1-Lxn: Voltage

N1-Nn: Phase nodes

NA: Control Node

P1-P4: Time Points

R1-R2: voltage divider resistor

S1-S2: Error signal

S3-S4: Node signal

Spwm1-Spwmn: control signal

Spwm-A: Waveform

Spwm-B: Waveform

Spwm-C: Waveform

Ta: Upper bridge switch

Tb: Lower bridge switch

Vramp: Ramp voltage

Vcomp: compensation signal

Vfb: Feedback voltage

Vin: Input voltage

Vout: output voltage

Vcc: power supply

Vea: Response voltage

VTH:Threshold voltage

VTL: threshold voltage.

Claims (10)

1. A multi-phase voltage regulator coupled to a multi-phase DC-DC converter, comprising: A plurality of voltage regulator circuits coupled between the power output stage circuit and the compensation circuit of the multi-phase DC-DC converter, for generating a plurality of control signals according to the compensation signal so that the power output stage circuit generates a plurality of output currents; One of the plurality of voltage regulator circuits comprises: a current comparison circuit for obtaining an error signal, wherein the error signal is a difference between a threshold current and a corresponding one of the plurality of output currents; and A delay circuit is coupled to the compensation circuit and the current comparison circuit, and is used to generate a corresponding one of the multiple control signals according to the compensation signal, wherein the delay circuit is used to adjust the bias current in the delay circuit according to the error signal to adjust the duty cycle of the corresponding one of the multiple control signals. 2. The multi-phase regulator according to claim 1, wherein the delay circuit comprises a first current source circuit to provide a first bias current, and the current comparison circuit comprises: A first current comparator, wherein the first end of the first current comparator is used to receive the threshold current, the second end of the first current comparator is used to receive the corresponding one of the multiple output currents, and the first current comparator outputs a first error signal to the first current source circuit to change the first bias current. 3. The multi-phase regulator according to claim 2, wherein the delay circuit comprises a second current source circuit to provide a second bias current, and the current comparison circuit comprises: A second current comparator, wherein the first end of the second current comparator is used to receive the corresponding one of the multiple output currents, the second end of the second current comparator is used to receive the threshold current, and the second current comparator outputs a second error signal to the second current source circuit to change the second bias current. 4 . The multi-phase regulator according to claim 3 , wherein the threshold current is an average current of the plurality of output currents. 5. The multi-phase regulator according to claim 4, wherein the delay circuit further comprises: an inverter having an input terminal, an output terminal, a first correction terminal and a second correction terminal, wherein the input terminal of the inverter is coupled to the output terminal of the compensation circuit to receive the compensation signal, the first correction terminal of the inverter is used to receive the first bias current, the second correction terminal of the inverter is used to receive the second bias current, and the output terminal of the inverter is used to output a node signal, wherein the first bias current and the second bias current are used to adjust the phase of the node signal; and A delay capacitor is coupled between the output terminal of the inverter and a reference potential, wherein when the error signal is at a high level, the delay capacitor is used to delay the time for the node signal to enter a low logic level from a high logic level; when the error signal is at a low level, the delay capacitor is used to delay the time for the node signal to enter a high logic level from a low logic level. 6. The multi-phase regulator according to claim 5, characterized in that the delay circuit further comprises: A hysteresis comparator is coupled to the output terminal of the inverter, and is used for generating a corresponding one of the plurality of control signals according to the node signal. 7. The multi-phase regulator according to claim 4, wherein the delay circuit further comprises: The inverter has an input terminal and an output terminal. The input terminal of the inverter is used to receive the compensation signal, and the output terminal of the inverter is used to output a node signal. 8. The multi-phase regulator according to claim 7, wherein the delay circuit further comprises: A hysteresis comparator is coupled to the output end of the inverter, the hysteresis comparator has an input end, an output end, a first correction end and a second correction end, the input end of the hysteresis comparator is coupled to the output end of the inverter to receive the node signal from the inverter; the first correction end of the hysteresis comparator is used to receive the first bias current; the second correction end of the hysteresis comparator is used to receive the second bias current, wherein the hysteresis comparator is used to generate a corresponding one of the multiple control signals according to the node signal, the first bias current and the second bias current. 9. The multi-phase regulator according to claim 8 is characterized in that the first threshold voltage and the second threshold voltage of the hysteresis comparator change according to the first bias current and the second bias current, wherein when the error signal is at a high level, the second threshold voltage will be reduced to delay the time for the node signal to enter a low logic level from a high logic level; when the error signal is at a low level, the first threshold voltage will be increased to delay the time for the node signal to enter a high logic level from a low logic level. 10. A multi-phase current balancing circuit, applied to a multi-phase DC-DC converter, characterized by comprising: A current detection circuit coupled to the power output stage circuit of the multi-phase DC-DC converter to obtain a plurality of output currents and a threshold current; and a plurality of voltage regulator circuits coupled between the current detection circuit and the compensation circuit of the multi-phase DC-DC converter, for generating a plurality of control signals according to a compensation signal so as to enable the power output stage circuit to generate the plurality of output currents; One of the plurality of voltage regulator circuits comprises: a current comparison circuit for obtaining an error signal, wherein the error signal is a difference between the threshold current and a corresponding one of the plurality of output currents; and A delay circuit is coupled to the compensation circuit and the current comparison circuit, and is used to generate a corresponding one of the multiple control signals according to the compensation signal, wherein the delay circuit is used to adjust the bias current in the delay circuit according to the error signal to adjust the duty cycle of the corresponding one of the multiple control signals.