KR101829346B1 - Voltage converter and voltage converting method - Google Patents

Abstract

A voltage converter of the present invention includes: a first P-type transistor having a drain terminal connected to a first node; A first N-type transistor having a drain terminal connected to the first node; And a gate driver for applying a first gate voltage to a first gate terminal of the first P-type transistor and applying a second gate voltage to a second gate terminal of the first N-type transistor, The driver includes a boosting capacitor and controls a swing level of the first gate voltage and the second gate voltage by switching a voltage at one end of the boosting capacitor.

Description

[0001] DESCRIPTION [0002] VOLTAGE CONVERTER AND VOLTAGE CONVERTING METHOD [

The present invention relates to a voltage converter and a voltage converting method.

Many portable terminals, such as smart phones, tablet PCs, and wearable devices, are being used variously in daily life. Since such portable terminals have a limited battery capacity, efficient power management is very important.

Such portable terminals generally spend most of their operating time in stand-by mode, so light load efficiency is a particularly important issue.

Most of the power losses in the DC-DC converter are conduction loss and switching loss. In a low-load environment, the switching losses are more dominant than the load conditions. Conduction losses tend to decrease as the load is lighter. Therefore, it is important to minimize the switching losses in order to improve the low-load efficiency of the DC-DC converter.

One effective way to minimize the switching losses of DC-DC converters is the charge recycling technique. , "Fully integrated 660 MHz low-swing energy-recycling dc dc converter," IEEE Trans. On Power Electr., Vol.24, no. 6, pp. 1475, June 2009 Prior Art 1) discloses a method for reusing the charge stored in the gate capacitance of a power MOSFET.

Prior Art 1 can reuse the power MOSFET gate charge by stacking power MOSFET drivers so that the PMOS gate charge can be directly transferred to the NMOS gate capacitance.

However, the prior art 1 requires a linear regulator to provide a mid-rail voltage, and the gate voltage swing is fixed to this mid-rail voltage, .

 M. Alimadadi, et al., "Fully integrated 660MHz low-swing energy-recycling dc dc converter," IEEE Trans. on Power Electr., vol.24, no. 6, pp. 1475, June 2009.

A technical problem to be solved is to provide a voltage converter and a voltage conversion method capable of controlling charge reuse and gate voltage swing level.

A voltage converter according to an embodiment of the present invention includes: a first P-type transistor having a drain terminal connected to a first node; A first N-type transistor having a drain terminal connected to the first node; And a gate driver for applying a first gate voltage to a first gate terminal of the first P-type transistor and applying a second gate voltage to a second gate terminal of the first N-type transistor, The driver includes a boosting capacitor and controls a swing level of the first gate voltage and the second gate voltage by switching a voltage at one end of the boosting capacitor.

The voltage converter may further include a boosting voltage generator for generating a boosting voltage fed to one end of the boosting capacitor by receiving a current of the first node.

The swing level of the first gate voltage and the swing level of the second gate voltage may be proportional to the magnitude of the boosting voltage.

Wherein the gate driving unit further includes a first switch and a second switch connected to one end of the boosting capacitor, the first switch connects a first reference voltage to one end of the boosting capacitor in accordance with a first switch control signal, The second switch may couple the boosting voltage to one end of the boosting capacitor according to a second switch control signal.

Wherein the gate driver further comprises a first buffer controlled according to a first PWM delay signal to generate the first gate voltage and a second buffer controlled according to a second PWM delay signal to generate the second gate voltage, The low voltage providing end of the first buffer and the high voltage providing end of the second buffer may be connected to the other end of the boosting capacitor.

The voltage converter receives a first PWM signal and a second PWM signal, and receives the first PWM delay signal, the second PWM delay signal, the first switch control signal And a control signal generator for generating the second switch control signal.

Wherein the control signal generator comprises: a first delay unit for delaying the first PWM signal to generate the first PWM delay signal; A first inverter for inverting the first PWM signal to generate a first PWM inversion signal; A first short pulse generator for detecting an edge of the first PWM delay signal to generate a first short pulse; A second short pulse generator for detecting an edge of the first PWM inversion signal to generate a second short pulse; And a first RS latch that receives the first short pulse and the second short pulse and generates the first switch control signal.

A second delay unit for delaying the second PWM signal to generate the second PWM delay signal; A second inverter for inverting the second PWM delay signal to generate a second PWM delay inversion signal; A third short pulse generator for detecting an edge of the second PWM delay inversion signal to generate a third short pulse; A fourth short pulse generator for detecting an edge of the second PWM signal to generate a fourth short pulse; And a second RS latch receiving the third short pulse and the fourth short pulse and generating the second switch control signal.

Wherein the boosting voltage generator comprises: a current sensor for sensing a current of the first node and outputting a selection signal; And a multiplexer for outputting one of the plurality of reference voltages according to the selection signal, wherein the boosting voltage may correspond to the selected one reference voltage.

The first buffer includes a second P-type transistor in which the first PWM delay signal is applied to the gate terminal and the source terminal is connected to the high voltage providing terminal; A second N-type transistor having a gate terminal connected to the gate terminal of the second P-type transistor, a source terminal connected to the low voltage providing terminal, and a drain terminal connected to the drain terminal of the second P-type transistor; A third P-type transistor having a gate terminal connected to the drain terminal of the second P-type transistor, a source terminal connected to the high voltage providing terminal, and a drain terminal connected to the gate terminal of the first P-type transistor; And a third N-type transistor having a gate terminal connected to the gate terminal of the third P-type transistor, a source terminal connected to the low voltage providing terminal, and a drain terminal connected to the drain terminal of the third P- . ≪ / RTI >

The second buffer includes a fourth P-type transistor in which the second PWM delay signal is applied to the gate terminal and the source terminal is connected to the high voltage providing terminal; A fourth N-type transistor having a gate terminal connected to the gate terminal of the fourth P-type transistor, a source terminal connected to the low voltage providing terminal, and a drain terminal connected to the drain terminal of the fourth P-type transistor; A fifth P-type transistor having a gate terminal connected to the drain terminal of the fourth P-type transistor, a source terminal connected to the high voltage providing terminal, and a drain terminal connected to the gate terminal of the first N-type transistor; And a fifth N-type transistor having a gate terminal connected to the gate terminal of the fifth P-type transistor, a source terminal connected to the low voltage providing terminal, and a drain terminal connected to the drain terminal of the fifth P- . ≪ / RTI >

Wherein the voltage converter includes a first P-type transistor and a first N-type transistor, the voltage converter converting an input voltage into an output voltage according to the first gate voltage and the second gate voltage; And a PWM signal generator for generating the first PWM signal and the second PWM signal by receiving the output voltage.

A voltage conversion method according to an embodiment of the present invention includes a first P-type transistor and a first N-type transistor each having a drain terminal connected to a first node, the first P-type transistor and the first P- 1. A voltage converting method of a voltage converter for converting an input voltage into an output voltage by controlling ON / OFF of an N-type transistor, the method comprising: discharging a gate capacitance of the first N-type transistor to a first reference voltage; Rail voltage of a mid-rail node of a first buffer supplying a first gate voltage to the first P-type transistor and a second buffer supplying a second gate voltage to the first N-type transistor, Down; Charging the mid-rail voltage by sharing a charge with the gate capacitance of the first P-type transistor; Charging a gate capacitance of the first P-type transistor to a second reference voltage; Pulling up the mid-rail voltage; And discharging the mid-rail voltage by charge sharing the gate capacitance of the first N-type transistor.

The voltage converter further includes a boosting capacitor connected at one end to the mid-rail node, and the step of pulling down the mid-rail voltage is performed by switching the voltage at the other end of the boosting capacitor to the first reference voltage .

The step of pulling up the mid-rail voltage may be performed by switching the voltage of the other end of the boosting capacitor to a boosting voltage.

The swing level of the first gate voltage and the second gate voltage may be proportional to the magnitude of the boosting voltage.

The voltage conversion method may further include determining the magnitude of the boosting voltage in proportion to the magnitude of the load.

The voltage converter and the voltage conversion method according to the present invention are capable of charge reuse and control of the gate voltage swing level.

1 is a view for explaining a voltage converter according to an embodiment of the present invention.
2 is a view for explaining a boosting voltage generator according to an embodiment of the present invention.
3 is a view for explaining a control signal generator according to an embodiment of the present invention.
4 is a view for explaining a first buffer and a second buffer according to an embodiment of the present invention.
5 is a view for explaining a first PWM delay signal, a second PWM delay signal, a first switch control signal, and a second switch control signal.
6 is a diagram for explaining the gate voltage swing level when the magnitude of the boosting voltage is relatively small.
7 is a diagram for explaining the gate voltage swing level when the magnitude of the boosting voltage is relatively large.
8 is a diagram for comparing switching losses of a voltage converter according to an embodiment of the present invention and a conventional voltage converter.
9 is a diagram for comparing conduction losses of a voltage converter and a conventional voltage converter according to an embodiment of the present invention.
10 is a diagram for comparing total losses of a voltage converter according to an embodiment of the present invention and a conventional voltage converter.
11 is a diagram for comparing efficiency of a voltage converter according to an embodiment of the present invention and a conventional voltage converter.
12 is a diagram for comparing the performance of a voltage converter according to an embodiment of the present invention and a conventional voltage converter.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may be embodied in many different forms and is not limited to the embodiments described herein.

In order to clearly illustrate the present invention, parts not related to the description are omitted, and the same or similar components are denoted by the same reference numerals throughout the specification. Therefore, the above-mentioned reference numerals can be used in other drawings.

In addition, since the sizes and thicknesses of the respective components shown in the drawings are arbitrarily shown for convenience of explanation, the present invention is not necessarily limited to those shown in the drawings. In the drawings, thicknesses may be exaggerated for clarity of presentation of layers and regions.

1 is a view for explaining a voltage converter according to an embodiment of the present invention.

1, a voltage converter 10 according to an embodiment of the present invention includes a voltage conversion unit 100, a gate driving unit 200, a boosting voltage generation unit 300, a control signal generation unit 400, And a PWM signal generator 500.

The voltage conversion unit 100 includes a first P-type transistor PTR1 having a drain terminal connected to the first node N1 and a first N-type transistor NTR1 having a drain terminal connected to the first node N1 do. The voltage conversion unit 100 includes a first gate voltage V _gp applied to the gate terminal of the first P-type transistor PTR1 and a second gate voltage V _gp applied to the gate terminal of the second N-type transistor NTR1. (V _in ) to the output voltage (V _out ) _in accordance with the output voltage (V _gn ).

The first P-type transistor PTR1 may be a P-type power MOSFET and the second N-type transistor NTR1 may be an N-type power MOSFET.

The voltage converting unit 100 may have a configuration of a DC-DC buck converter (DC-DC buck converter). The voltage conversion unit 100 may include an inductor L connected at one end to the first node N1, a capacitor C connected in series to the other end of the inductor L, and a resistor R _esr . The current source I _load may be modeling the load current.

The input voltage V _in may be applied to the source terminal of the first P-type transistor PTR 1 and converted to the output voltage V _out at the other end of the inductor L. The output voltage V _out may be smaller than the input voltage V _in . At this time, the output voltage V _out may be fed back to the PWM signal generating unit 500.

The gate driver 200 applies a first gate voltage V _gp to the first gate terminal of the first P-type transistor PTR1 and applies a second gate voltage V _gp to the second gate terminal of the first N-type transistor NTR1. And the gate voltage V _gn is applied.

The gate driving unit 200 includes a boosting capacitor C _s and switches the voltage of one end of the boosting capacitor C _s so that the swing level of the first gate voltage V _gp and the second gate voltage V _gn .

Specifically, the gate driving part 200 may further include a first switch (SW1) and the second switch (SW2) is connected to one end of the boosting capacitor (C _s). The first switch SW1 couples one end of the boosting capacitor C _s to a first reference voltage (e.g., ground voltage) in accordance with the first switch control signal S _p and the second switch SW2 The boosting voltage V _boost may be connected to one end of the boosting capacitor C _s according to the second switch control signal S _n .

At this time, the swing level of the first gate voltage V _gp and the swing level of the second gate voltage V _gn may be proportional to the magnitude of the boosting voltage V _boost . This will be described later in detail with reference to FIGS. 6 and 7. FIG.

Gate driver 200 is controlled in response to the first PWM delay signal (PWM _pd) is controlled in response to a first gate voltage of the first buffer (BUF1) and the 2 PWM delay signal (PWM _pd) for generating a (V _gp) the may further comprise a second buffer (BUF2) for generating a second gate voltage (V _gn). The first buffer providing a low voltage stage and a second stage provides high voltage of the buffer (BUF2) of (BUF1) it may be connected to the other terminal of the boosting capacitor (C _s). At this time, the voltage of a node to which the low voltage providing terminal of the first buffer BUF1 and the high voltage providing terminal of the second buffer BUF2 are connected to each other may be referred to as a mid-rail voltage. The detailed configuration of the first buffer and the second buffer will be described later with reference to FIG.

Boosting voltage generator 300 may generate a boosted voltage (V _boost) that is provided at one end of the receive feed back the current of the first node (N1), the boosting capacitors (C _s). An exemplary configuration of the boosting voltage generator 300 will be described later with reference to FIG.

The control signal generator 400 receives the first PWM signal PWM _p and the second PWM signal PWM _n and outputs the first PWM signal PWM _p and the second PWM signal PWM _n according to the first PWM signal PWM _p and the second PWM signal PWM _n , It generates the PWM delay signal (PWM _pd), a second delayed PWM signal (PWM _nd), the first switch control signal (S _p), and the second switch control signal (S _n). An exemplary configuration of the control signal generator 400 will be described later with reference to Fig.

Generally, the smaller the voltage swing level reduces the switching losses, but the conduction losses increase as the on-resistance of the power MOSFET increases. Thus, the optimum voltage swing level exists when the sum of switching loss and conduction loss can be minimized. In order to obtain such an optimum voltage swing level, the boosting voltage generator 300 and the control signal generator 400 may be configured as shown in FIGS. 2 and 3 to be described later and controlled according to the timing of FIG. 5 .

The PWM signal generator 500 receives the output voltage V _out and generates a first PWM signal PWM _p and a second PWM signal PWM _n . The PWM signal generator 500 includes a Type-3 Compensation Network 510, a Ramp Generator 520, a PWM Modulator 530, a dead- (Dead Time Controller & Zero Current Detector) 540. The configuration of the PWM signal generator 500 described above is not described separately because it is based on the prior art.

2 is a view for explaining a boosting voltage generator according to an embodiment of the present invention.

2, a boosting voltage generator 300 according to an embodiment of the present invention senses the current of the first node N1 or senses the amount of the load current to generate a selection signal CS [1: 0] and a reference voltage of one of a plurality of reference voltages V [0], V [1], V [2], and V [3] 0]) output from the multiplexer 320. The boosting voltage (V _boost ) may correspond to a selected reference voltage.

The boosting voltage generating unit 300 includes a bandgap reference 330 for generating a plurality of reference voltages V [0], V [1], V [2], and V [3] And a comparator 340 for comparing and outputting the reference voltage and the feedback voltage. The bandgap reference 330 is not described separately because it conforms to the prior art configuration.

In this embodiment, four generated reference voltages V [0], V [1], V [2], and V [3] , But in other embodiments it may be configured to increase the resolution of the current sensor 310 to increase the number of bits of the selection signal and the bandgap reference 330 to generate a greater number of reference voltages accordingly. In such a case, the multiplexer 320 would also have to be modified to correspond to the number of reference voltages increased.

The on / off of the transistor 350 is adjusted according to the output of the comparator 340, and the boosting voltage V _boost accumulated in the capacitor 360 is determined. The value of the boosting voltage V _boost may be fed back to the comparator 340 according to the resistance ratio of the resistor 371 and the resistor 372.

3 is a view for explaining a control signal generator according to an embodiment of the present invention.

3, a control signal generator 400 according to an exemplary embodiment of the present invention includes a first delay unit 411 for generating a first PWM delay signal PWM _pd by delaying a first PWM signal PWM _p , A first inverter 421 for generating a first PWM inversion signal by inverting the first PWM signal PWM _p and a second inverter 423 for detecting the edge of the first PWM delay signal PWM _pd to generate a first short pulse a second short pulse generator 432 for detecting an edge of the first PWM inversion signal to generate a second short pulse, and a second short pulse generator 432 for generating a first short pulse and a second short pulse, And a first RS latch (RS latch) 441 receiving the pulse and generating a first switch control signal S _p .

The control signal generator 400 further includes a second delay unit 412 for delaying the second PWM signal PWM _n to generate a second PWM delay signal PWM _nd and a second delay unit 412 for delaying the second PWM delay signal PWM _nd A third short pulse generator 433 for detecting the edge of the second PWM delay inversion signal to generate a third short pulse, a second PWM signal generating circuit 433 for generating a third short pulse, the generating a fourth short pulse generator 434, and a third short pulse and the second switch control signal (S _n) receives the four short pulse for generating a fourth short pulse by detecting the edge of the PWM _n) 2 < / RTI > RS latch 442, as shown in FIG.

In order to switch the bias voltage of the boosting capacitor C _s before the gate charge sharing of the first P-type transistor PTR 1, the first switch control signal S _p must be at a high level (on level). In order to switch the bias voltage of the boosting capacitor C _s before the gate charge sharing of the first N-type transistor NTR1, the second switch control signal S _n must be at a high level (on level).

Claim is generated by the first and the second switch control signal (S _p, S _n) comprises a first and a second PWM signal (PWM _p, PWM _n) and a delayed signal (PWM _{pd, nd} PWM). The PWM signals PWM _p and PWM _n are used to set the switch control signals S _p and S _n while the PWM delay signals PWM _pd and PWM _nd are used to set the switch control signals S _p and S _n , _n ). < / RTI >

4 is a view for explaining a first buffer and a second buffer according to an embodiment of the present invention.

Referring to FIG. 4, a first buffer BUF1 according to an embodiment of the present invention includes a first P-type buffer P-1 having a first PWM delay signal PWM _pd applied to its gate terminal and a source terminal connected to a high- type transistor PTR2, a gate terminal connected to the gate terminal of the second P-type transistor PTR2, a source terminal connected to the low voltage providing terminal, a drain terminal connected to the drain terminal of the second P-type transistor PTR2, Type transistor NTR2 having a gate terminal connected to the drain terminal of the second P-type transistor PTR2, a source terminal connected to the high voltage providing terminal, a drain terminal connected to the first P-type transistor PTR2, A third P-type transistor PTR3 connected to the gate terminal of the transistor PTR1 and a gate terminal connected to the gate terminal of the third P-type transistor PTR3, a source terminal connected to the low voltage providing terminal, Drain terminal of the third P-type transistor PTR3 is connected to the drain terminal Which is connected to may include a first 3 N-type transistor (NTR3).

The second buffer BUF2 includes a fourth P-type transistor PTR4 having a second PWM delay signal PWM _nd applied to its gate terminal and a source terminal connected to a high voltage providing terminal, a fourth N-type transistor NTR4 connected to the gate terminal of the P-type transistor PTR4, the source terminal connected to the low voltage providing terminal and the drain terminal connected to the drain terminal of the fourth P-type transistor PTR4, The fifth P-type transistor NTR1 has a gate terminal connected to the drain terminal of the fourth P-type transistor PTR4, a source terminal connected to the high voltage providing terminal, and a drain terminal connected to the gate terminal of the first N- type transistor PTR5 and the gate terminal thereof are connected to the gate terminal of the fifth P-type transistor PTR5, the source terminal thereof is connected to the low voltage providing terminal, and the drain terminal thereof is connected to the fifth P-type transistor PTR5 And a fifth N-type transistor (NPTR5) connected to the drain terminal Can.

In Fig. 4, although each buffer BUF1 and BUF2 is shown as two inverters connected in series, the number of serially connected inverters can be changed by a person skilled in the art.

5 is a view for explaining a first PWM delay signal, a second PWM delay signal, a first switch control signal, and a second switch control signal.

First as an input signal of the first PWM delay signal (PWM _pd), a second PWM delay signal (PWM _nd), the first switch control signal (S _p), and the second switch control signal (S _n), a gate driver 200, Is used.

The second PWM delay signal PWM _nd is pulled down before the pull-down of the first PWM delay signal PWM _pd to give a dead time of a certain portion, and the second PWM The first PWM delay signal PWM _pd is pulled up before the delay signal PWM _nd is pulled up.

The first switch control signal (S _p) and the second switch control signal (S _n) is allowed to transition (transitions) only during this dead time.

6 is a diagram for explaining the gate voltage swing level when the magnitude of the boosting voltage is relatively small.

Referring to FIG. 6, it can be confirmed how much the first gate voltage V _gp and the second gate voltage V _gn have swing levels according to time (horizontal axis). In this embodiment, the first gate voltage V _gp has a swing level of V _in -V _p and the second gate voltage has a swing level of V _n . The method of deriving the voltages V _p and V _n will be described with reference to Equations (1) to (3). It is also possible to confirm a change in the voltage at the other end of the boosting capacitor C _s and the value of the mid-rail voltage V _s .

During the first period P1, the pull-down of the second PWM delay signal PWM _nd causes the fifth P-type transistor PTR5 to turn off and the fifth N-type transistor NTR5 to turn on a second gate voltage (V _gn) the pool to the ground level - to discharge the C _gn is the gate capacitance of the by-off, a 1 N-type transistor (NTR1) - turned down to claim 1 N-type transistor (NTR1) .

만큼 풀-다운되고, 여기서

는 부스팅 커패시터(C_s)의 일단인 미드-레일 노드에서의 전하-재사용 커패시턴스 및 전체 기생 커패시턴스 사이의 비율(the ratio between the charge-recycling capacitance and total parasitic capacitance)이다.Next, during the second period P2, the pull-down of the second switch control signal S _n and the pull-up of the first switch control signal S _{p cause one} end of the boosting capacitor C _s to be boosted Is switched and connected from a voltage (V _boost ) to a first reference voltage (e.g., ground voltage). Therefore, when the mid-rail voltage V _s is

Down < / RTI >

Is the ratio between the charge-reuse capacitance and the total parasitic capacitance at the mid-rail node, which is one end of the boosting capacitor (C _s ).

Next, during the third period P3, when the first PWM delay signal PWM _pd is pulled down, the third P-type transistor PTR3 is turned off and the third N-type transistor NTR3 is turned - sharing causes charge sharing between the gating capacitance C _gp and the boosting capacitor C _{s of} the first P-type transistor PTR1. After charge sharing, the mid-rail voltage V _s becomes equal to the voltage V _p . Equation 1 below can be derived from the charge conservation law. According to an embodiment, the input voltage V _in may be equal in value to the second reference voltage V _DD .

[Equation 1]

Therefore, the voltage V _p can be derived by the following equation (2).

&Quot; (2) "

Similarly, during the fourth period P4, as the first PWM delay signal PWM _pd is _pulled up, the capacitance C _gp is charged to the second reference voltage V _DD and the first P-type transistor PTR1) is turned off.

만큼 풀-업시킨다.Next, during the fifth period P5, one end of the boosting capacitor C _s is pulled up by the pull-down of the first switch control signal S _p and the pull-up of the second switch control signal S _n , Is switched from the reference voltage to the boosting voltage (V _boost ), which causes the mid-rail voltage (V _s )

Up.

Next, during the sixth period P6, the second PWM delay signal PWM _nd is pulled up, the fifth N-type transistor NTR5 is turned off and the fifth P-type transistor PTR5 is turned - On, charge sharing occurs between the gate capacitance (C _gn ) and the boosting capacitor (C _s ).

Similarly, the voltage V _n may be derived as: < EMI ID = 3.0 >

&Quot; (3) "

It can be seen from Equations 2 and 3 that the voltage V _p and the voltage V _n corresponding to the gate voltage swing level can be controlled by the boosting voltage V _boost . When the boosting voltage V _boost rises, the voltage V _p falls and the voltage V _n rises, which means that the power MOSFET gate voltage swing level is raised.

7 is a diagram for explaining the gate voltage swing level when the magnitude of the boosting voltage is relatively large.

Referring to FIG. 7, there is shown a case where the boosting voltage V _boost has a larger value than in the case of FIG. As predicted, the gate voltage swing level is increased compared to Fig.

The voltage level of the boosting voltage (V _boost ) can be adjusted to the situation by monitoring the amount of load current. For example, in a heavier load condition a larger voltage swing level may be tolerated.

FIG. 8 is a diagram for comparing switching losses of a voltage converter according to an exemplary embodiment of the present invention and a conventional voltage converter. FIG. 9 is a graph illustrating a comparison between a switching loss of a voltage converter according to an exemplary embodiment of the present invention, FIG. 10 is a diagram for comparing total losses of a voltage converter according to an embodiment of the present invention and a conventional voltage converter, FIG. 11 is a diagram illustrating a voltage converter according to an embodiment of the present invention, Voltage converter according to an embodiment of the present invention.

For the comparison experiment of Figs. 8 to 11, the voltage converter 10 of this embodiment is illustratively designed in a 65 nm CMOS process. In this embodiment, the supply voltage was set at 3.3 V, the output voltage was set at 1.8 V, and the switching frequency was set at 8.4 MHz.

Referring to FIG. 8, in the light load condition of 100 mA or less, the voltage converter 10 of the present embodiment consumes a switching power reduced by 81% as compared with the conventional voltage converter. This performance can be achieved by the charge reuse technique and the low voltage swing technique inherent in the present embodiment.

Referring to FIG. 9, as the load condition changes from a low load to a high load, a voltage converter with a structure that only charges are reused without swing control shows an abruptly increasing conduction loss. This conduction loss leads to a higher total loss compared to conventional voltage converters.

To optimize the total loss, the voltage converter 10 according to one embodiment of the present invention controls the gate voltage swing. When the load current increases to 100 mA or more, the voltage converter 10 increases the gate voltage swing level.

Although this method increases the switching loss somewhat, the conduction loss is greatly reduced, so that the total loss is reduced by 27.5% under the 300 mA load condition, as shown in FIG.

Referring to FIG. 11, the efficiency of the voltage converter 10 is measured under different load conditions. The proposed voltage converter 10 shows an efficiency improvement of up to 24% compared to a conventional voltage converter.

12 is a diagram for comparing the performance of a voltage converter according to an embodiment of the present invention and a conventional voltage converter.

Referring to FIG. 12, the performance of the voltage converter 10 proposed in the first table (Table I) is compared with the performance of a conventional charge reuse DC-DC converter. The voltage converter 10 of this embodiment shows a peak efficiency of 92% and a light load efficiency of 85.8% under a 50mA load condition.

It is to be understood that both the foregoing general description and the following detailed description of the present invention are illustrative and explanatory only and are intended to be illustrative of the invention and are not to be construed as limiting the scope of the invention as defined by the appended claims. It is not. Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

10: voltage converter
100:
200: Gate driver
300: boosting voltage generating unit
400: control signal generating unit
500: PWM signal generating unit

Claims (17)

A first P-type transistor having a drain terminal connected to the first node;
A first N-type transistor having a drain terminal connected to the first node; And
And a gate driver for applying a first gate voltage to a first gate terminal of the first P-type transistor and applying a second gate voltage to a second gate terminal of the first N-type transistor,
Wherein the gate driver includes a boosting capacitor and controls a swing level of the first gate voltage and the second gate voltage by switching a voltage at one end of the boosting capacitor,
Further comprising a boosting voltage generator for receiving a current of the first node and generating a boosting voltage provided at one end of the boosting capacitor,
Voltage converter. delete The method according to claim 1,
Wherein a swing level of the first gate voltage and a swing level of the second gate voltage are proportional to a magnitude of the boosting voltage,
Voltage converter. The method according to claim 1,
The gate driving unit may further include a first switch and a second switch connected to one end of the boosting capacitor,
The first switch connects a first reference voltage to one end of the boosting capacitor in accordance with a first switch control signal,
And the second switch couples the boosting voltage to one end of the boosting capacitor in accordance with a second switch control signal,
Voltage converter. 5. The method of claim 4,
Wherein the gate driver further comprises a first buffer controlled according to a first PWM delay signal to generate the first gate voltage and a second buffer controlled according to a second PWM delay signal to generate the second gate voltage,
The low voltage providing end of the first buffer and the high voltage providing end of the second buffer are connected to the other end of the boosting capacitor,
Voltage converter. 6. The method of claim 5,
The first PWM signal and the second PWM signal and outputs the first PWM delay signal, the second PWM delay signal, the first switch control signal, and the second PWM signal in accordance with the first PWM signal and the second PWM signal, 2 < / RTI > switch control signal
Voltage converter. The method according to claim 6,
The control signal generator
A first delay unit for delaying the first PWM signal to generate the first PWM delay signal;
A first inverter for inverting the first PWM signal to generate a first PWM inversion signal;
A first short pulse generator for detecting an edge of the first PWM delay signal to generate a first short pulse;
A second short pulse generator for detecting an edge of the first PWM inversion signal to generate a second short pulse; And
And a first RS latch (RS latch) receiving the first short pulse and the second short pulse to generate the first switch control signal.
Voltage converter. 8. The method of claim 7,
The control signal generator
A second delay unit for delaying the second PWM signal to generate the second PWM delay signal;
A second inverter for inverting the second PWM delay signal to generate a second PWM delay inversion signal;
A third short pulse generator for detecting an edge of the second PWM delay inversion signal to generate a third short pulse;
A fourth short pulse generator for detecting an edge of the second PWM signal to generate a fourth short pulse; And
Further comprising a second RS latch which receives the third short pulse and the fourth short pulse and generates the second switch control signal,
Voltage converter. The method according to claim 1,
The boosting voltage generator
A current sensor for sensing a current of the first node and outputting a selection signal; And
And a multiplexer for outputting one of the plurality of reference voltages according to the selection signal,
Wherein the boosting voltage corresponds to the one selected reference voltage,
Voltage converter. 6. The method of claim 5,
The first buffer
A second P-type transistor in which the first PWM delay signal is applied to a gate terminal and the source terminal is connected to a high voltage providing terminal;
A second N-type transistor having a gate terminal connected to the gate terminal of the second P-type transistor, a source terminal connected to the low voltage providing terminal, and a drain terminal connected to the drain terminal of the second P-type transistor;
A third P-type transistor having a gate terminal connected to the drain terminal of the second P-type transistor, a source terminal connected to the high voltage providing terminal, and a drain terminal connected to the gate terminal of the first P-type transistor; And
A third N-type transistor having a gate terminal connected to the gate terminal of the third P-type transistor, a source terminal connected to the low voltage providing terminal, and a drain terminal connected to the drain terminal of the third P- Including,
Voltage converter. 11. The method of claim 10,
The second buffer
A fourth P-type transistor in which the second PWM delay signal is applied to the gate terminal and the source terminal is connected to the high voltage providing terminal;
A fourth N-type transistor having a gate terminal connected to the gate terminal of the fourth P-type transistor, a source terminal connected to the low voltage providing terminal, and a drain terminal connected to the drain terminal of the fourth P-type transistor;
A fifth P-type transistor having a gate terminal connected to the drain terminal of the fourth P-type transistor, a source terminal connected to the high voltage providing terminal, and a drain terminal connected to the gate terminal of the first N-type transistor; And
A fifth N-type transistor having a gate terminal connected to the gate terminal of the fifth P-type transistor, a source terminal connected to the low voltage providing terminal, and a drain terminal connected to the drain terminal of the fifth P- Including,
Voltage converter. The method of claim 6, wherein
A voltage conversion unit including the first P-type transistor and the first N-type transistor and converting an input voltage into an output voltage according to the first gate voltage and the second gate voltage; And
And a PWM signal generator for generating the first PWM signal and the second PWM signal by feedback of the output voltage
Voltage converter. And a first P-type transistor and a first N-type transistor each having a drain terminal connected to the first node, wherein the on / off state of the first P-type transistor and the first N-type transistor is controlled, To an output voltage, the method comprising:
Discharging the gate capacitance of the first N-type transistor to a first reference voltage;
Rail voltage of a mid-rail node of a first buffer supplying a first gate voltage to the first P-type transistor and a second buffer supplying a second gate voltage to the first N-type transistor, Down;
Charging the mid-rail voltage by sharing a charge with the gate capacitance of the first P-type transistor;
Charging a gate capacitance of the first P-type transistor to a second reference voltage;
Pulling up the mid-rail voltage; And
And discharging the mid-rail voltage by charge sharing the gate capacitance of the first N-type transistor
Voltage conversion method. 14. The method of claim 13,
The voltage converter further includes a boosting capacitor connected at one end to the mid-rail node,
The step of pulling down the mid-rail voltage
And switching the voltage of the other end of the boosting capacitor to the first reference voltage,
Voltage conversion method. 15. The method of claim 14,
The step of pulling up the mid-rail voltage
And switching the voltage of the other end of the boosting capacitor to a boosting voltage,
Voltage conversion method. 16. The method of claim 15,
Wherein the swing level of the first gate voltage and the second gate voltage is proportional to the magnitude of the boosting voltage,
Voltage conversion method. 17. The method of claim 16,
Further comprising determining the magnitude of the boosting voltage in proportion to the magnitude of the load.
Voltage conversion method.

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