CN221427719U - Semiconductor packaging structure - Google Patents

Abstract

The utility model provides a semiconductor packaging structure, wherein a substrate comprises a first surface and a second surface which are oppositely arranged, and a chip is arranged on the first surface; the heat dissipation cover is erected above the chip and fixed on the substrate, the thermal interface layer is arranged between the chip and the heat dissipation cover and is contacted with the chip and the heat dissipation cover, a boss is arranged at a preset part of the heat dissipation cover contacted with the thermal interface layer, and the boss is embedded into the thermal interface layer. According to the utility model, the thermal interface layer in the flip chip ball grid array package is a graphene-polymer composite material layer, so that the heat conduction capacity is improved, and the thermal stability is ensured; meanwhile, a boss is arranged on the heat dissipation cover in a matching way, so that the thickness of a thermal interface layer corresponding to a power consumption hot spot area of the chip is compressed, and the junction temperature of the chip is reduced; in addition, the structure that grooves exist in the thermal interface layer at the corresponding positions of the bosses is utilized, so that the whole thermal interface layer is free from compression; finally, the influence of the boss on the mechanical strength of the thermal interface layer is avoided by setting the boss size.

Description

Semiconductor packaging structure

Technical Field

The utility model belongs to the technical field of semiconductor integrated circuit manufacturing, and particularly relates to a semiconductor packaging structure.

Background

The current processor products have the characteristics of miniaturization, high integration, great calculation power and the like, so that the thermal design power consumption of the processor products is increased sharply, the power consumption density of chips is higher and higher, and great challenges are brought to packaging and system heat dissipation. FCBGA (Flip Chip Ball GRID ARRAY) packages are the dominant packaging form for processor products due to their large size, high signal density, high mechanical strength, and good heat dissipation. According to the characteristics of the FCBGA packaging structure, about 9 chips generate heat by transferring the heat to the heat dissipation cover through the first thermal interface material on the upper surface of the chips, and then transferring the heat to the fin type radiator through the second thermal interface material outside the package, and taking away the heat by adopting natural convection or forced convection.

The first thermal interface material inside an ideal FCBGA package needs to possess the following characteristics: a. high thermal conductivity and lower assembly thickness; b. good wettability with metal and nonmetal interfaces to achieve lower interface thermal resistance; c. the air in the interface gap is discharged and the packaging assembly tolerance is compensated by the air with certain compressibility; d. good thermal stability and insulation; e. good detachability and replaceability, etc.

At present, the industry does not have the characteristics that the material can have all the characteristics, and the heat conduction silicone grease and low-melting-point metal solder adopted by the main stream processor manufacturers mainly have the following defects: the heat conduction silicone grease is a traditional heat dissipation material, and is mainly prepared by adding metals such as aluminum, silver and the like or ceramic heat conduction particles such as aluminum oxide, aluminum nitride, boron nitride, silicon carbide and the like into a polymer matrix, wherein the heat conductivity is generally not higher than 4.0W/(m.k), and the heat conductivity of the heat conduction silicone grease is not high, so that the assembly thickness of the heat conduction silicone grease needs to be controlled within the range of 0.04-0.10mm, a substrate can be stained during preparation and smearing, the pumping effect is obvious, overflow and phase separation are easy to occur during use, the heat conduction silicone grease can be dried due to volatilization of a solvent during long-term use, and the reliability of the heat conduction silicone grease is greatly reduced; the current main stream high-end processor chip is mainly made of low-melting metal solder such as indium and the like as a first thermal interface material, the pure indium has a thermal conductivity of 81.8W/(m.times.K), the melting point is about 157 ℃, the texture is soft and the ductility is good, partial stress can be absorbed, but the storage capacity and annual output of the metal indium are limited, the cost is higher, the corrosion resistance is poor and the metal indium is easy to oxidize, the indium is difficult to infiltrate with a silicon coating and a nickel coating (a copper heat dissipation cover surface treatment mode), therefore, gold plating is needed to be carried out on the surfaces of a chip and a heat dissipation cover to improve the wettability of the chip, and before the chip is plated with gold, a barrier layer of titanium, nickel and vanadium is needed to prevent the indium from diffusing to silicon, if a surface-mounted device is required to be wrapped by insulating glue to prevent the indium solder from overflowing to cause short circuit, and after the indium is welded and subjected to severe temperature cycle, holes and microcracks are easy to generate, and even fail.

In order to ensure long-term high-performance operation of the chip, junction temperature is required to be lower than a set specification value during the operation of the chip. The junction temperature is directly related to the power consumption distribution besides being influenced by the whole power consumption of the chip and the thermal resistance of the first thermal interface material, and the current first thermal interface material is assembled in a certain thickness and cannot perform heat dissipation optimization on a hot spot area of the power consumption. Therefore, there is a need for a package structure that can reduce the junction temperature of the chip in the FCBGA package and improve the thermal conductivity of the first thermal interface material.

It should be noted that the foregoing description of the background art is only for the purpose of providing a clear and complete description of the technical solutions of the present application and is thus convenient for a person skilled in the art to understand, and it should not be construed that the above technical solutions are known to the person skilled in the art merely because these solutions are described in the background art section of the present application.

Disclosure of utility model

In view of the above drawbacks of the prior art, an object of the present utility model is to provide a semiconductor package structure, which is used for solving the problems of non-ideal thermal conductivity of an internal thermal interface layer and high junction temperature of a chip in the FCBGA package structure in the prior art.

In order to achieve the above object, the present utility model provides a semiconductor package structure including: a substrate, a thermal interface layer, a chip, and a heat spreader lid;

The substrate comprises a first surface and a second surface which are oppositely arranged, and the chip is arranged on the first surface; the heat dissipation cover is arranged above the chip and fixed on the substrate, the thermal interface layer is arranged between the chip and the heat dissipation cover and is contacted with the chip and the heat dissipation cover, a boss is arranged at a preset part of the heat dissipation cover, which is contacted with the thermal interface layer, and the boss is embedded into the thermal interface layer.

Optionally, the boss is located above a power consumption hot spot area of the chip.

Optionally, the semiconductor package structure includes a plurality of chips, and when a distance between two adjacent chips is greater than or equal to 2 mm and less than or equal to 15mm, the heat dissipation covers above the two adjacent chips are all provided with the boss.

Optionally, a cross-sectional area of the boss parallel to the chip is equal to or greater than 15% of a cross-sectional area of the chip, and a cross-sectional area of the boss parallel to the chip is equal to or less than 40% of a cross-sectional area of the chip.

Optionally, the cross section of the boss parallel to the first plane is triangular, the cross section of the boss parallel to the second plane is rectangular, the first plane is perpendicular to the plane where the thermal interface layer is located, the second plane is perpendicular to the plane where the thermal interface layer is located, and the first plane is perpendicular to the second plane.

Optionally, a predetermined amount of compression exists in the thermal interface layer at a corresponding location below the boss to embed the boss within the thermal interface layer.

Optionally, the preset compression amount of the thermal interface layer at the corresponding position below the boss is less than or equal to 50% of the height of the thermal interface layer.

Optionally, a groove is present in the thermal interface layer at a corresponding position below the boss so that the boss is embedded in the thermal interface layer, and the boss coincides with the projection of the groove on the plane of the thermal interface layer.

Optionally, the thermal interface layer is a composite material layer with a matrix of a high molecular material, filled graphene or carbon nanotubes.

Optionally, the thermal interface layer is a composite material layer obtained by mixing or melt blending a high polymer material and a graphene solution.

As described above, the semiconductor package structure of the present utility model has the following beneficial effects:

According to the utility model, the thermal interface layer in the flip chip ball grid array package is a graphene-polymer composite material layer, so that the heat conduction capacity is improved, and the thermal stability is ensured;

The heat dissipation cover is matched with the boss, so that the thickness of the thermal interface layer corresponding to the power consumption hot spot area of the chip is compressed, and the junction temperature of the chip is reduced;

The utility model uses the structure that the thermal interface layer at the corresponding position of the boss is provided with the groove, so that the whole thermal interface layer is ensured to have no compression;

The utility model utilizes the setting of the boss size to avoid the influence of the boss on the mechanical strength of the thermal interface layer.

Drawings

Fig. 1 is a schematic top view of a semiconductor package according to the present utility model.

Fig. 2 is a schematic diagram showing a cross-sectional side view of an MM' of the semiconductor package according to the present utility model.

Fig. 3 is a schematic perspective view showing a simulation model of a semiconductor package structure according to the present utility model.

Fig. 4 is a schematic cross-sectional side view of a semiconductor package according to the present utility model.

Fig. 5 is a graph showing a power consumption distribution of a simulation model of a semiconductor package structure according to the present utility model.

Fig. 6 shows a box diagram of thermal simulation results for 3 semiconductor package structures.

Description of element reference numerals

1. A substrate; 11. a first solder array; 12. a first surface; 13. a second surface; 2. a thermal interface layer; 21. a boss; 3. a chip; 31. a second solder array; 4. a filling layer; 5. a heat-dissipating cover; 6. an adhesive layer; 7. an external circuit board; 8. a fin-shaped heat sink; 9. a fan.

Detailed Description

Other advantages and effects of the present utility model will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present utility model with reference to specific examples. The utility model may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present utility model.

As described in detail in the embodiments of the present utility model, the schematic drawings showing the structure of the apparatus are not partially enlarged to general scale, and the schematic drawings are merely examples, which should not limit the scope of the present utility model. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.

For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures.

In the context of the present application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present utility model by way of illustration, and only the components related to the present utility model are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

As shown in fig. 1-2, fig. 2 is a cross-sectional view taken along the MM' line in fig. 1, and the present utility model provides a semiconductor package structure comprising: a substrate 1, a thermal interface layer 2, a chip 3 and a heat sink cap 5;

The substrate 1 comprises a first surface 12 and a second surface 13 which are oppositely arranged, and the chip 3 is arranged on the first surface 12; the heat dissipation cover 5 is arranged above the chip 3 and fixed on the substrate 1, the thermal interface layer 2 is arranged between the chip 3 and the heat dissipation cover 5 and is in contact with the chip 3 and the heat dissipation cover 5, a boss 21 is arranged at a preset part of the heat dissipation cover 5, which is in contact with the thermal interface layer 2, and the boss 21 is embedded into the thermal interface layer 2.

According to the utility model, the boss 21 is arranged on the preset part of the radiating cover 5, which is in contact with the thermal interface layer 2, so that the thickness of the part of the boss 21, which is correspondingly embedded into the thermal interface layer 2, is reduced, the thermal resistance of the thermal interface layer 2 is reduced, and the junction temperature of the chip 3, which is correspondingly positioned with the thermal interface layer 2, of the part of the boss 21, is reduced, and the radiating optimization is realized.

In one embodiment, the semiconductor package structure further includes a first solder array 11 and a second solder array 31, the first solder array 11 is disposed on the second surface 13, and the chip 3 is disposed on the first surface 12 through the second solder array 31.

In one embodiment, the boss 21 is manufactured by forging or milling.

In one embodiment, the boss 21 is located above a power consumption hot spot area of the chip 3.

In an embodiment, the power consumption hot spot area may be one power consumption hot spot with the highest power consumption, or may be a hot spot array formed by a plurality of power consumption hot spots above a certain threshold.

Specifically, as shown in fig. 3-4, by establishing a model identical to the semiconductor package structure in a simulation environment, and arranging a simplified structure similar to the practical application environment, such as an external circuit board 7, a fin-shaped radiator 8, a fan 9 and the like, outside the package, a power consumption distribution file of the chip 3 and the number of practical fans are imported to perform thermal simulation, and by establishing a power consumption distribution map of the model to correspond to the position of the chip 3, a histogram or a cloud chart as shown in fig. 5 is output, wherein the higher the power consumption of the column in the histogram is, the larger the higher the power consumption of the column is, the position of the heat dissipation cover 5 corresponding to the power consumption hot spot area of the chip 3 is found in the histogram or the cloud chart, and the position is a preset position for setting the boss 21.

In a simulation experiment, 3 different packaging structures are established, wherein the 1 st structure is that a thermal interface layer 2 material is made of heat conduction silicone grease, the heat conductivity of the silicone grease is 4.0W/(m is K), and the thickness of the silicone grease is typically 0.1 mm; the 2 nd structure is that a thermal interface layer 2 material is a graphene filled high-molecular heat conduction gasket, the heat conductivity of the gasket is not lower than 25.0W/(m.times.K), and the thickness of the gasket is typically 0.3 mm; the 3 rd structure is a thermal interface material, graphene is used for filling a high-molecular heat conduction gasket, the heat conductivity and the thickness of the gasket are the same as those of the 2 nd structure, the local protrusion height on the heat dissipation cover 5 is 0.15 millimeter in a power consumption distribution hot spot area of a wafer, and the length and the width of one surface of the heat dissipation cover 5 erected on the chip 3 are 2.5 millimeters. As shown in fig. 6, as can be seen from the box-type diagram of the results of thermal simulation of 3 structures, after the thermal interface material is changed from the heat conduction silicone grease to graphene filled high polymer heat conduction gaskets, the junction temperature at the hot spot of the chip 3 is reduced from 96.1 ℃ to 83.8 ℃, junction temperature benefit of 12.3 ℃ is obtained, and meanwhile, the temperature of the thermal interface material (thermal interface layer 2) is also reduced; after the local micro-boss 21 is made on the heat dissipation cover 5, the junction temperature is reduced from 83.8 ℃ to 79.1 ℃, and the junction temperature gain of 4.7 ℃ is obtained through the tiny change of the structure of the heat dissipation cover 5, so that more allowance is left for the specifications of the fin-shaped radiator 8 and the fan 9.

Specifically, in the industry, the thermal interface layer 2 modified in the present utility model is a first thermal interface inside the package structure, and a second thermal interface is typically disposed between the heat dissipating cover 5 and the fin heat spreader 8 outside the package structure.

According to the utility model, through reducing the thermal resistance of the power consumption hot spot area of the chip 3, the heat dissipation optimization of the junction temperature control of the chip 3 is realized, so that more allowance can be reserved for the specifications of the radiator and the fan outside the package.

In one embodiment, the semiconductor package structure includes a plurality of chips 3, each chip 3 is provided with a thermal interface layer 2, and the heat dissipation cover 5 may be provided with a boss 21 in a corresponding power consumption hot spot area on each chip 3.

In one embodiment, the semiconductor package structure includes a plurality of the chips 3, and when a distance between two adjacent chips 3 is 2mm or more and 15 mm or less, the heat dissipation covers 5 above the two adjacent chips 3 are each provided with the boss 21.

According to the utility model, whether the boss 21 is arranged is determined by the distance between two adjacent chips 3, so that the design scheme of the boss 21 can be directly obtained according to the structural design of the chips 3 under the condition of not carrying out thermal simulation, the heat dissipation optimization of the junction temperature control of the chips 3 is realized, the method is more convenient and quicker than the method of obtaining the power consumption hot spot area by thermal simulation, the method is beneficial to the general application in actual production, and compared with the scheme that the boss 21 is arranged on the heat dissipation cover 5 on each chip 3, the optimization of heat dissipation efficiency can be realized while the structural modification is reduced to the greatest extent.

In one embodiment, the cross-sectional area of the boss 21 parallel to the chip 3 is 15% or more of the cross-sectional area of the chip 3, and the cross-sectional area of the boss 21 parallel to the chip 3 is 40% or less of the cross-sectional area of the chip 3.

In one embodiment, the cross-sectional area of the boss 21 parallel to the chip 3 is 25% of the cross-sectional area of the chip 3.

According to the utility model, by setting the proportional relation between the cross-sectional area of the boss 21 and the cross-sectional area of the chip 3, the problem that the local heat dissipation optimization effect is not obvious when the cross-sectional area of the boss 21 is too small is avoided; meanwhile, the excessive cross-sectional area of the boss 21 is avoided, and the local compression amount of the thermal interface layer 2 is too large, so that the thermal interface layer 2 is cracked or crushed, and the structural yield of the packaging structure is ensured while the optimal heat dissipation effect is realized.

In one embodiment, the boss 21 is a triangular prism structure with a bottom surface perpendicular to the thermal interface layer 2, one side edge of the triangular prism structure is embedded in the thermal interface layer 2, a cross section of the boss 21 parallel to a first plane is triangular, a cross section of the boss 21 parallel to a second plane is rectangular, the first plane is perpendicular to the plane of the thermal interface layer 2, the second plane is perpendicular to the plane of the thermal interface layer 2, and the first plane is perpendicular to the second plane.

According to the utility model, the cross section of the boss 21 parallel to the first plane is triangular, so that the thickness of the thermal interface layer 2 embedded by the boss 21 is reduced, and the compression amount of the boss 21 on the thermal interface layer 2 is reduced, thereby being beneficial to maintaining the structural strength of the thermal interface layer 2.

In one embodiment, a predetermined amount of compression exists in the thermal interface layer 2 at a corresponding location below the boss 21 such that the boss 21 is embedded within the thermal interface layer 2.

In one embodiment, the predetermined amount of compression of the thermal interface layer 2 at a corresponding location below the boss 21 is less than or equal to 50% of the height of the thermal interface layer 2.

In one embodiment, the predetermined amount of compression of the thermal interface layer 2 at a corresponding location below the boss 21 is 30%, 40% or 50% of the height of the thermal interface layer 2.

The utility model prevents the thermal interface layer 2 from being easily broken due to the overlarge compression amount generated by the boss 21 by setting the preset compression amount of the thermal interface layer 2 so as to ensure the reliability of the packaging structure.

In one embodiment, a recess is present in the thermal interface layer 2 at a corresponding location below the boss 21 such that the boss 21 is embedded within the thermal interface layer 2, the boss 21 coinciding with the projection of the recess onto the plane of the thermal interface layer 2.

According to the utility model, the grooves are formed in the thermal interface layer 2 at the corresponding positions below the bosses 21, so that the thickness of the thermal interface layer 2 at the power consumption hot spots is reduced, the whole thermal interface layer 2 is ensured to have no compression, and the problems of warpage and the like caused by uneven compression of the thermal interface layer 2 due to the scheme of designing the bosses 21 by setting the preset compression of the thermal interface layer 2 are avoided.

In one embodiment, the material of the heat dissipating cover 5 is copper.

According to the utility model, the material of the heat dissipation cover 5 is copper with higher heat conductivity, so that the thickness change of the heat dissipation cover 5 has little influence on the reduction of thermal resistance, and the reaction of the thickness of the boss 21 on the reduction of thermal resistance is avoided.

In one embodiment, the thickness of the heat dissipating cover 5 is 0.5 mm-0.8 mm, and the thickness of the boss 21 is 0.1 mm-0.2 mm.

In particular, the thickness of the boss 21 is set to be within a range satisfying the pressure that the chip 3 can withstand and the compression that the thermal interface layer 2 can withstand.

In one embodiment, as shown in fig. 1, the heat dissipation cover 5 and the substrate 1 are fixed by an adhesive layer 6.

In one embodiment, the thermal interface layer 2 is a composite layer with a matrix of a polymeric material, filled graphene or carbon nanotubes.

In one embodiment, the thermal interface layer 2 is a composite material layer obtained by mixing or melt blending a high molecular material and a graphene solution.

Specifically, the thermal interface layer 2 may also adopt other suitable methods to form a composite material layer from graphene and a polymer material.

In one embodiment, the polymeric material is polyurethane or silicone rubber.

Specifically, other suitable polymer materials and graphene can be selected to form a composite material according to actual requirements.

According to the utility model, the graphene or carbon nano tube and high polymer composite material layer is used as the material of the thermal interface layer 2, the high polymer-based thermal interface layer 2 can provide stable dielectric properties at high temperature, has the advantages of oxidation resistance, good insulativity, water resistance, flame retardance, no pollution and convenient assembly, and enables the thermal interface layer 2 to have shock absorption; the graphene has extremely high heat conductivity, the maximum heat conductivity of single-layer graphene can reach 5300W/(m.K), the thermal stability is good, the thermal conductivity has stronger interaction force with a high polymer matrix, and the thermal pad can be prepared by various methods to serve as a first thermal interface to serve as a good choice for replacing thermal silicone grease or indium sheets.

Specifically, the reverse engineering chip 3 is used for packaging the physical cover, so that the packaging structure can be confirmed, whether the thermal interface layer 2 is a composite of graphene and a polymer matrix can be confirmed by scanning electron microscopic analysis, and whether the boss 21 is embedded in the thermal interface layer 2 can be confirmed by microscopic observation of the heat dissipation cover 5, so that the thickness of the thermal interface layer 2 can be reduced.

In one embodiment, the semiconductor package structure is a flip chip ball grid array package.

Because the FCBGA (Flip Chip Ball GridArray ) package is characterized in that most heat is firstly transferred to the heat dissipation cover 5 through the first thermal interface and then transferred to the fin-shaped heat radiator from the heat dissipation cover 5 through the second thermal interface, the heat transfer efficiency requirement on the first thermal interface is higher, and the heat dissipation performance of the FCBGA package is improved by improving the material of the thermal interface layer 2 and the heat dissipation cover 5 contacted with the thermal interface layer 2.

In one embodiment, as shown in fig. 1, the filler layer 4 fills the gaps between the second solder arrays 31.

In summary, according to the semiconductor packaging structure, the thermal interface layer in the flip chip ball grid array package is a graphene-polymer composite material layer, so that the heat conduction capability is improved, and the thermal stability is ensured; meanwhile, a boss is arranged on the heat dissipation cover in a matching way, so that the thickness of a thermal interface layer corresponding to a power consumption hot spot area of the chip is compressed, and the junction temperature of the chip is reduced; in addition, the structure that grooves exist in the thermal interface layer at the corresponding positions of the bosses is utilized, so that the whole thermal interface layer is free from compression; finally, the influence of the boss on the mechanical strength of the thermal interface layer is avoided by setting the boss size.

Therefore, the utility model effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles of the present utility model and its effectiveness, and are not intended to limit the utility model. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the utility model. Accordingly, it is intended that all equivalent modifications and variations of the utility model be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (7)

1. A semiconductor package structure, the semiconductor package structure comprising: a substrate, a thermal interface layer, a chip, and a heat spreader lid;

The substrate comprises a first surface and a second surface which are oppositely arranged, and the chip is arranged on the first surface; the heat dissipation cover is arranged above the chip and fixed on the substrate, the heat dissipation layer is arranged between the chip and the heat dissipation cover and is contacted with the chip and the heat dissipation cover, a boss is arranged at a preset part of the heat dissipation cover, which is contacted with the heat dissipation layer, and is embedded into the heat dissipation layer, and the boss is positioned above a power consumption hot spot area of the chip.

2. The semiconductor package according to claim 1, wherein the semiconductor package includes a plurality of the chips, and the heat dissipation covers above two adjacent chips are each provided with the boss when a distance between the two adjacent chips is 2 mm or more and 15 mm or less.

3. The semiconductor package according to claim 1, wherein a cross-sectional area of the boss parallel to the chip is 15% or more of a cross-sectional area of the chip, and a cross-sectional area of the boss parallel to the chip is 40% or less of a cross-sectional area of the chip.

4. The semiconductor package according to claim 1, wherein the cross section of the boss parallel to a first plane is triangular, the cross section of the boss parallel to a second plane is rectangular, the first plane is perpendicular to the plane in which the thermal interface layer is located, the second plane is perpendicular to the plane in which the thermal interface layer is located, and the first plane is perpendicular to the second plane.

5. The semiconductor package according to any one of claims 1-4, wherein a predetermined amount of compression exists in the thermal interface layer at a corresponding location below the boss to embed the boss within the thermal interface layer.

6. The semiconductor package according to claim 5, wherein the predetermined compression amount of the thermal interface layer at the corresponding position under the bump is 50% or less of the height of the thermal interface layer.

7. The semiconductor package according to any one of claims 1 to 4, wherein a recess is provided in the thermal interface layer at a position corresponding to a position below the bump so that the bump is embedded in the thermal interface layer, the projection of the bump onto a plane in which the thermal interface layer is located, the projection of the recess coinciding with the projection of the recess.