CN221304685U

CN221304685U - Wafer with electromagnetic shielding structure, chip and semiconductor packaging structure

Info

Publication number: CN221304685U
Application number: CN202322982058.8U
Authority: CN
Inventors: 陈晗玥
Original assignee: Jiangsu Silicon Integrity Semiconductor Technology Co Ltd
Current assignee: Jiangsu Silicon Integrity Semiconductor Technology Co Ltd
Priority date: 2023-11-03
Filing date: 2023-11-03
Publication date: 2024-07-09
Anticipated expiration: 2033-11-03

Abstract

The utility model provides a wafer with an electromagnetic shielding structure, chips and a semiconductor packaging structure, wherein the wafer comprises a plurality of chips, cutting channels are arranged between every two chips, grooves are formed in the cutting channels on the front surface of the wafer, the grooves surround each chip, the grooves are formed in the cutting channels, and metal parts are arranged in the grooves; the upper surface of the metal part is flush with the upper surface of the groove, or the upper surface of the metal part is higher than the upper surface of the groove; the back of the wafer is provided with a metal layer, the metal part is connected with the metal layer, an electromagnetic shielding structure is directly arranged on each chip on the wafer by forming the electromagnetic shielding structure on each chip, and after cutting, a single chip with an electromagnetic shielding function is formed, so that the production efficiency is high, and no overflow plating risk exists. The electromagnetic shielding chip is directly attached to the substrate in the follow-up process, and the semiconductor packaging structure formed after plastic packaging does not need to be designed and manufactured, so that the production efficiency of the semiconductor packaging structure is improved.

Description

Wafer with electromagnetic shielding structure, chip and semiconductor packaging structure

Technical Field

The utility model belongs to the technical field of semiconductor packaging, and particularly relates to a wafer with an electromagnetic shielding structure, a chip and a semiconductor packaging structure.

Background

Electromagnetic interference (EMI) has historically been a problem for electronic product design engineers to be headache, which threatens the safety, reliability and stability of electronic devices. Therefore, when designing electronic products, an electromagnetic shielding layer needs to be manufactured on an electronic system, so that the electromagnetic interference suffered by a chip is controlled within a certain range, the design requirement and standard are met, and the overall performance of a circuit is improved.

In the prior art, the shielding function is generally realized by connecting an inner metal cover, a Wire Bond (Wire Bond) vertical Wire bonding or laser slotting conductive silver paste filled, a sputtering metal layer and the like with an outer shielding (shielding) layer. In the process, a special machine is required to be used for overturning the cut single chip and then attaching the single chip to the single-sided high-temperature-resistant PI film or the double-sided high-temperature-resistant adhesive film, and the product is required to be taken down from the high-temperature-resistant adhesive film after sputtering is completed. The equipment, auxiliary materials and tools involved in the process are high in cost, and the single chip operation has high overflow plating risk, so that the yield of the subsequent packaged products is affected.

Disclosure of Invention

The utility model aims to provide a wafer with an electromagnetic shielding structure, wherein the electromagnetic shielding structure is directly arranged for each chip on the wafer, and a single chip with an electromagnetic shielding function is formed after cutting, so that the production efficiency is high, and the overflow plating risk is avoided. The electromagnetic shielding chip is directly attached to the substrate in the follow-up process, and the semiconductor packaging structure formed after plastic packaging does not need to be designed and manufactured, so that the production efficiency of the semiconductor packaging structure is improved.

In order to achieve the above objective, in one aspect, the present utility model provides a wafer with an electromagnetic shielding structure, the wafer includes a plurality of chips, dicing channels are disposed between every two chips, grooves are disposed on the dicing channels on the front surface of the wafer, the grooves surround each chip, the grooves are disposed on the dicing channels, and the width of the grooves is the depth; a metal part is arranged in the groove; the upper surface of the metal part is flush with the upper surface of the groove, or the upper surface of the metal part is higher than the upper surface of the groove; the back of the wafer is provided with a metal layer, the metal part is connected with the metal layer, and an electromagnetic shielding structure is formed for each chip.

In some embodiments, the grooves have a width of 300-1000um and a depth of 100-300um.

In some embodiments, the front surface of the chip is provided with ball implants or conductive bumps.

In a second aspect, the present utility model provides an electromagnetic shielding chip formed by dicing along the dicing streets.

In a third aspect, the present utility model provides a semiconductor package structure, where the package structure includes a substrate, at least one electromagnetic shielding chip and a plastic layer, the electromagnetic shielding chip is attached to a surface of the substrate, the plastic layer is disposed on the surface of the substrate, and the plastic layer covers the electromagnetic shielding chip.

Compared with the prior art, the utility model has the following beneficial effects:

1. According to the wafer with the electromagnetic shielding structure, the electromagnetic shielding structure is directly arranged for each chip on the wafer, and the chip with the electromagnetic shielding function is formed at the wafer stage; after cutting, forming a single chip with an electromagnetic shielding function, the production efficiency is high, and the overflow plating risk is avoided;

2. The electromagnetic shielding chip is directly attached to the substrate, and the semiconductor packaging structure formed after plastic packaging does not need to be designed and manufactured, so that the production efficiency of the semiconductor packaging structure is improved.

Drawings

Fig. 1 is a schematic diagram showing a structure of a wafer in embodiment 1 of the present utility model;

FIG. 2 is a schematic diagram showing the structure of the wafer of FIG. 1 with grooves;

FIG. 3 shows a partial schematic view of the cross-sectional structure of FIG. 2;

FIG. 4 shows a schematic view of the structure of the groove of FIG. 3 filled with metal parts;

FIG. 5 shows a schematic view of the structure of the metal layer of FIG. 4;

FIG. 6 shows a schematic diagram of the structure of a single chip in FIG. 5;

FIG. 7 shows another schematic structure of the groove of FIG. 3 filled with metal parts;

FIG. 8 shows a schematic view of the structure of the metal layer of FIG. 7;

FIG. 9 is a schematic diagram showing another structure of the single chip in FIG. 8;

fig. 10 is a schematic view showing a semiconductor package structure in embodiment 2;

Fig. 11 shows another schematic view of the semiconductor package structure in embodiment 2.

Detailed Description

In order to make the objects, technical solutions and advantages of the present utility model more apparent, the technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings.

Example 1

The embodiment provides a wafer with an electromagnetic shielding structure.

Fig. 1-3 show a schematic configuration of the recess 102 around each die 101 of the wafer 1.

Specifically, the wafer 1 includes a plurality of chips 101, and dicing channels are disposed between every two chips 101, and the dicing channels are not shown in the figure. Grooves 102 are formed in dicing streets on the front surface of the wafer 1, the grooves 102 are surrounded on the periphery of each chip 101, and the grooves 102 are formed in the dicing streets.

The width and depth of the recess 102 are adjusted according to the thickness of the thinned chip. The width of the recess 102 is typically 300-1000um and the depth is typically 100-300um; a metal portion 103 is provided in the groove 102. The metal portion 103 may be formed in the groove 102 in an electroplating manner.

As shown in fig. 4 and 5, the upper surface of the metal part 103 may be flush with the upper surface of the groove 102, which has the advantage that the shielding layer and the circuit layer can be led out simultaneously when the ball is plated or the conductive bump is plated; ball mounting or conductive bump arrangement is performed on the surface of the chip 101. The implant ball or conductive bump is shown as reference number 3. Then, the back surface of the wafer 1 is thinned, a metal layer 2 is provided on the back surface, and the metal portion 103 is connected to the metal layer 2, thereby forming an electromagnetic shielding structure for each chip 101. After the whole wafer 1 is cut, a single chip with an electromagnetic shielding function is formed, as shown in fig. 6.

Or as shown in fig. 7 and 8, the upper surface of the metal part 103 may be higher than the upper surface of the groove 102, and the shielding layer is led out by electroplating in advance, and then the circuit layer is led out by ball-planting operation; the leading-out terminal of the shielding layer is connected with the grounding end on the surface of the substrate 4, the welding interface is larger, the conducting performance is good, the shielding effect is better than that of the conventional sputtering shielding, the metal wire on the side surface of the substrate is conducted, the design of the substrate 4 is simpler (namely, the grounding terminal is not required to be led to the edge of the substrate through a wire specially, and only the grounding circuit is arranged at the corresponding position on the surface of the substrate). The two modes are suitable for different product requirements. Subsequently, balls are planted or conductive bumps are arranged on the surface of the chip 101. The implant ball or conductive bump is shown as reference number 3. Then, the back surface of the wafer 1 is thinned, a metal layer 2 is provided on the back surface, and the metal portion 103 is connected to the metal layer 2, thereby forming an electromagnetic shielding structure for each chip 101. After the whole wafer 1 is cut, a single chip with an electromagnetic shielding function is formed, as shown in fig. 9.

The wafer with the electromagnetic shielding structure disclosed in the embodiment is directly provided with the electromagnetic shielding structure for each chip 101 on the wafer 1, and the chip with the electromagnetic shielding function is formed at the wafer stage; and in the later stage, a single chip with an electromagnetic shielding function is formed after cutting according to the requirement, so that the production efficiency is greatly improved, and the single chip with the electromagnetic shielding function does not have the risk of overflow plating in the subsequent process application because the design of an electromagnetic shielding structure is not needed.

Example 2

As shown in fig. 10 and 11, the present embodiment provides a semiconductor package structure, which includes a substrate 4, at least one electromagnetic shielding chip 101 and a plastic layer 5, wherein the electromagnetic shielding chip 101 is attached to the surface of the substrate 4, the plastic layer 5 is disposed on the surface of the substrate 4, and the plastic layer 5 covers the electromagnetic shielding chip 101.

The electromagnetic shielding chip 101 may employ the chip structure of fig. 6 or fig. 9 in embodiment 1.

In this embodiment, the electromagnetic shielding chip 101 in embodiment 1 is directly attached to the substrate 4, and since the chip has an electromagnetic shielding function, the semiconductor package structure formed after plastic packaging does not need to be designed and manufactured, and the production efficiency of the semiconductor package structure is improved.

The above is only a preferred embodiment of the present utility model and is not intended to limit the present utility model, and various modifications and variations of the present utility model will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the gist and principle of the present utility model should be included in the protection scope of the present utility model.

Claims

1. The wafer with the electromagnetic shielding structure comprises a plurality of chips, and cutting channels are arranged between every two chips, and the wafer is characterized in that grooves are formed in the cutting channels on the front face of the wafer, the grooves surround each chip, the grooves are formed in the cutting channels, and metal parts are arranged in the grooves; the upper surface of the metal part is flush with the upper surface of the groove, or the upper surface of the metal part is higher than the upper surface of the groove; the back of the wafer is provided with a metal layer, the metal part is connected with the metal layer, and an electromagnetic shielding structure is formed for each chip.

2. The wafer with electromagnetic shielding structure of claim 1, wherein the width of the groove is 300-1000um and the depth is 100-300um.

3. The wafer with electromagnetic shielding structure according to claim 2, wherein the front surface of the chip is provided with ball implants or conductive bumps.

4. An electromagnetic shielding chip, characterized in that the electromagnetic shielding chip is formed by dicing along the dicing streets of any one of claims 1 to 3.

5. The semiconductor packaging structure is characterized by comprising a substrate, at least one electromagnetic shielding chip and a plastic sealing layer, wherein the electromagnetic shielding chip is attached to the surface of the substrate, the plastic sealing layer is arranged on the surface of the substrate, and the plastic sealing layer covers the electromagnetic shielding chip.