CN221283414U - Circuit board structure for optimizing series tolerance and impedance division - Google Patents
Circuit board structure for optimizing series tolerance and impedance division Download PDFInfo
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- CN221283414U CN221283414U CN202322732030.9U CN202322732030U CN221283414U CN 221283414 U CN221283414 U CN 221283414U CN 202322732030 U CN202322732030 U CN 202322732030U CN 221283414 U CN221283414 U CN 221283414U
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- 239000003990 capacitor Substances 0.000 claims abstract description 93
- 238000004806 packaging method and process Methods 0.000 abstract description 3
- 230000008859 change Effects 0.000 abstract description 2
- 230000008054 signal transmission Effects 0.000 description 7
- 238000000034 method Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 230000006872 improvement Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
Abstract
The utility model discloses a circuit board structure for optimizing serial tolerance and impedance division, which comprises a circuit board, wherein a differential wiring and a capacitor bonding pad are arranged on the top layer of the circuit board; the line width of the differential wire is 4.3mil, and the wire distance of a pair of differential wires is 9.2mil; the capacitor pads are square, the width of each capacitor pad is smaller than 14mil, the length of each capacitor pad is smaller than 20mil, two capacitor pads form a group, the distance between the capacitor pads of one group on the longitudinal axis is smaller than 10mil, and the distance between the capacitor pads of two groups corresponding to a pair of differential wires is smaller than 20mil. The utility model reduces the capacitance value by reducing the size of the packaging bonding pads of the series capacitor, reduces the attenuation of high-frequency signals, reduces abrupt change in a signal path by adjusting proper intervals among a group of capacitance bonding pads, and can solve the problem of discontinuous differential impedance at the series capacitor, so that the impedance is about 100 ohms.
Description
Technical Field
The utility model relates to the field of circuit boards, in particular to a circuit board structure for optimizing series tolerance and partial impedance.
Background
Printed circuit boards (Printed Circuit Board, PCB boards), also known as printed circuit boards, printed wiring boards, are an important component of the physical support and signal transmission of electronic products.
The differential signal is that the driving end sends two equivalent and opposite signals, the receiving end judges whether the logic value is 0 or 1 according to the voltage difference of the differential signal, and two circuits carrying the differential signal are called differential wiring. The continuity of the differential impedance is a critical factor in ensuring signal integrity, particularly for high-speed digital signals. The differential impedance discontinuity can cause reflections, distortion and noise of the signal, affecting the performance of the device. In order to ensure that the differential signals of the two circuits are completely consistent, the differential wiring requirements are kept in parallel, the line width and the line spacing are kept unchanged, so that the differential impedance of the two circuits is ensured to be consistent, and the reflection is reduced.
The impedance requirement of the differential wiring on the top layer of the circuit board is 100 ohms, and when the differential wiring passes through the capacitance of the surface-mounted bonding pad, namely the alternating-current coupling capacitance, the condition of abrupt line width and line distance exists, and the impedance deviation can be caused. The 0402 package typically used for the prior art capacitor has a 0402 package capacitor pad size of 20 mils, a 17mil spacing between the capacitor pads, and a calculated impedance value of 81.48 ohms when the trace is routed to the pad. The capacitance adopts 0402 encapsulation, and 100 ohm deviation with the impedance requirement of the differential wiring at the top layer of the circuit board is larger, and the differential wiring impedance deviation is larger, so that the signal transmission rate and the signal stability can be influenced.
Disclosure of utility model
In order to solve the problems that the impedance of the differential wiring has larger deviation from 100 ohm required by the impedance of the differential wiring on the top layer of the circuit board and can influence the transmission rate and the signal stability of signals, the utility model provides a circuit board structure for optimizing serial tolerance and differential impedance.
The technical scheme of the utility model is as follows:
The circuit board structure is characterized by comprising a circuit board, wherein a top layer of the circuit board is provided with a differential wire and a capacitor pad, and one end part of the differential wire is connected with the capacitor pad;
The line width of the differential wire is 4.3mil, and the line distance between a pair of differential wires is 9.2mil;
The capacitor pads are square, the width of each capacitor pad is smaller than 14mil, the length of each capacitor pad is smaller than 20mil, two capacitor pads form a group, the distance between the capacitor pads of one group on the longitudinal axis is smaller than 10mil, and the distance between the capacitor pads of two groups corresponding to a pair of differential wires is smaller than 20mil.
The utility model according to the above scheme is characterized in that a group of signal vias are arranged between a group of the capacitor pads.
The utility model according to the above-mentioned aspect is characterized in that a set of the capacitor pads are each provided with a set of ground vias corresponding to the signal vias.
The utility model according to the above scheme is characterized in that a group of the ground vias are arranged on the same edge of a group of the capacitor pads, and the central connecting lines of the two ground vias are parallel to the central connecting lines of the two pins of the capacitor pads.
The utility model according to the above scheme is characterized in that the diameter of the via hole is 8mil.
Further, one of the signal vias is located at the center of the capacitor pad, the other signal via is located at the edge of the capacitor pad, and the central connecting line of the two signal vias is parallel to the central connecting line of the two pins of the capacitor pad.
The utility model according to the above scheme is characterized in that the diameter of the signal via is 8mil.
Further, silk screen printing is arranged outside each group of capacitor pads.
The utility model according to the scheme has the advantages that the capacitance value is reduced by reducing the size of the packaging bonding pads of the series capacitor, the attenuation of high-frequency signals is reduced, abrupt changes in signal paths are reduced by adjusting proper intervals among a group of capacitance bonding pads, the problem of discontinuous differential impedance at the series capacitor can be further improved by further improving the consistency of impedance, and the smaller bonding pads also provide larger wiring space, thereby being beneficial to optimizing the layout of other wirings and elements and further improving the consistency of impedance.
Drawings
FIG. 1 is a schematic diagram of the structure of the present utility model;
FIG. 2 is a schematic diagram of a second embodiment of the present utility model;
Fig. 3 is a schematic structural diagram of a first embodiment of the present utility model.
In the drawings, the respective reference numerals are as follows:
1. A circuit board;
10. Differential wiring;
20. a capacitor pad; 21. silk screen printing;
30. A signal via;
40. And (5) a ground via.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the utility model is further described in detail below with reference to the accompanying drawings and embodiments.
It should be noted that the terms "comprising" and "having" and any variations thereof in the description and claims of the present utility model are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus. The term "disposed" and like terms are to be broadly interpreted, and may be fixedly connected, detachably connected, or integrally formed, for example; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The directions or positions indicated by the terms "upper", "lower", "left", "right", "front", "rear", "bottom", etc. are directions or positions based on those shown in the drawings, and are merely for convenience of description, and are not to be construed as limiting the present technical solution.
As shown in fig. 1-3, a circuit board structure for optimizing series capacitance and differential impedance comprises a circuit board 1, wherein a differential wire 10 and a capacitor pad 20 are arranged on the top layer of the circuit board 1, one end of the differential wire 10 is connected with the capacitor pad 20, and the series capacitance pad is reduced in size to improve the condition of impedance deviation, so that the problem of discontinuous differential impedance at the series capacitance can be solved.
Specifically, the line width of the differential trace 10 is 4.3mil, the line distance between the pair of differential traces 10 is 9.2mil, and the impedance of the differential trace 10 can reach 100 ohms to match the required impedance. The capacitor pads 20 are square, the width of the capacitor pads 20 is less than 14mil, the length of the capacitor pads 20 is less than 20mil, two capacitor pads 20 form a group, the distance between the capacitor pads 20 of one group on the longitudinal axis is less than 10mil, and the distance between the two groups of capacitor pads 20 corresponding to the pair of differential wires 10 is less than 20mil.
The utility model reduces the capacitance value by reducing the size of the packaging bonding pads of the series capacitor, reduces the attenuation of high-frequency signals, reduces abrupt changes in signal paths by adjusting proper intervals among a group of capacitance bonding pads 20, further improves the consistency of impedance, can improve the problem of discontinuous differential impedance at the series capacitor, and the smaller bonding pads also provide larger wiring space, thereby being beneficial to optimizing the layout of other wirings and elements and further improving the consistency of impedance.
When the differential signal transmission device is used, the capacitor is welded to the capacitor pad 20, the differential signal enters the capacitor, direct current noise in the signal is isolated through capacitor filtering, the quality of the differential signal is improved, and the differential signal enters other devices, so that the signal transmission is realized.
In one case, the capacitor pads 20 are square pads of 14mil in length and width, and the capacitor has a 9.62mil spacing between the two capacitor pads 20. In a specific layout, the differential trace 10 passes through one of the capacitor pads 20 of the capacitor, and the network before and after the capacitor is still a network after passing through the other capacitor pad 20. And welding the 0201 device when welding the device. The spacing between the two capacitive devices was 19 mils and the calculated impedance was 99.75 ohms, which was close to the desired impedance value of 100 ohms.
In case two, the capacitor pads 20 were rectangular pads having a width of 13mil and a length of 19.68mil, and the two capacitor pads 20 of the capacitor were spaced 9.06mil apart. The specific layout is similar to case one, and the device of 0201 is soldered when the device is soldered. The two capacitive devices were spaced 20 mils apart and the calculated impedance was 104.51 ohms, which was close to the desired impedance value of 100 ohms. The pad shape of the capacitor is optimized under the condition that the welding of the capacitor device is not affected, so that the problem of reducing the abrupt change of the impedance of the serial capacitance pad is solved. The optimized impedance is generally close to the required impedance value, and the closer the impedance is, the better the impedance is, and the control is as low as +/-5%.
In the second embodiment, a set of signal vias 30 are disposed between a set of capacitor pads 20, the set of signal vias 30 includes two signal vias 30, the two signal vias 30 are connected with one of the set of capacitor pads 20 on the top layer of the circuit board 1, the other capacitor pad 20 is connected with a pad of a chip, and the two signal vias 30 are respectively connected with differential signal lines in the middle layer of the circuit board 1. The utility model can realize the transmission of signals from the middle layer of the circuit board 1 to the devices on the top layer of the circuit board 1 through the signal through holes 30, and can also realize the transmission of signals from the top layer of the circuit board 1 to the middle layer or other layers of the circuit board 1.
Specifically, when in use, the chip is welded to the chip pad, the capacitor is welded to the capacitor pad 20, so that the circuit among the chip, the capacitor and the differential signal wires is conducted, the differential signal reaches the top layer of the circuit board 1 from the differential wires in the middle layer of the circuit board 1 through the signal via hole 30, then reaches one pin of the capacitor pad 20 from the top layer of the circuit board 1, thus entering the capacitor, the differential signal is filtered by the capacitor, the direct current noise in the signal is isolated, the quality of the differential signal is improved, then reaches the chip pad from the other pin of the capacitor pad 20, and then enters the chip, thereby realizing the signal transmission, and the signal can be transmitted from the chip to the differential signal wires.
In a preferred embodiment, a set of capacitive pads 20 are each provided with a set of ground vias 40 corresponding to the signal vias 30. The ground vias 40 are used to provide the shortest signal return path to ensure signal quality.
In a preferred embodiment, a set of ground vias 40 are disposed on the same edge of a set of capacitor pads 20, and the center line of two ground vias 40 is parallel to the center line of two pins of capacitor pads 20. One of the signal vias 30 is located in the center of the capacitor pad 20 and the other is located at the edge of the capacitor pad 20, and the center line of the two signal vias 30 is parallel to the center line of the two pins of the capacitor pad 20. The signal via 30 is disposed at the center of a group of capacitor pads 20, so that a larger distance exists between the signal via 30 and the capacitor pads 20, the arrangement between the two is not affected, and the interference between the two is reduced. The ground via holes 40 are arranged at the edges of a group of capacitor pads 20, so that a certain distance is reserved between the ground via holes 40 and the capacitor pads 20, the ground via holes 40 and the capacitor pads 20 are convenient to arrange, the proper distance between the ground via holes 40 and the signal via holes 30 is ensured, signal backflow is ensured, and further signal quality is ensured.
In a preferred embodiment, the diameter of the ground vias 40 is 8 mils. The diameter of the signal via 30 is 8 mils. The purpose of this is to design the circuit board 1 as desired, and to select the appropriate apertures for the ground vias 40 and the signal vias 30.
It will be understood that modifications and variations will be apparent to those skilled in the art from the foregoing description, and it is intended that all such modifications and variations be included within the scope of the following claims.
While the utility model has been described above with reference to the accompanying drawings, it will be apparent that the implementation of the utility model is not limited by the above manner, and it is within the scope of the utility model to apply the inventive concept and technical solution to other situations as long as various improvements made by the inventive concept and technical solution are adopted, or without any improvement.
Claims (8)
1. The circuit board structure is characterized by comprising a circuit board, wherein a top layer of the circuit board is provided with a differential wire and a capacitor pad, and one end part of the differential wire is connected with the capacitor pad;
The line width of the differential wire is 4.3mil, and the line distance between a pair of differential wires is 9.2mil;
The capacitor pads are square, the width of each capacitor pad is smaller than 14mil, the length of each capacitor pad is smaller than 20mil, two capacitor pads form a group, the distance between the capacitor pads of one group on the longitudinal axis is smaller than 10mil, and the distance between the capacitor pads of two groups corresponding to a pair of differential wires is smaller than 20mil.
2. A circuit board structure for optimizing series tolerance split impedance as claimed in claim 1, wherein a set of signal vias are provided between a set of said capacitor pads.
3. A circuit board structure for optimizing series tolerance split impedance according to claim 2, wherein a set of said capacitor pads are each provided with a set of ground vias corresponding to said signal vias.
4. A circuit board structure for optimizing series tolerance split impedance according to claim 3, wherein a group of said ground vias are disposed on the same edge of a group of said capacitor pads, and the center line of two ground vias is parallel to the center line of two pins of said capacitor pads.
5. A circuit board structure for optimizing series tolerance split impedance according to claim 3 or 4, wherein said ground vias have a diameter of 8mil.
6. A circuit board structure for optimizing serial tolerance split impedance according to claim 2, wherein one of said signal vias is located in the center of one of said capacitor pads and the other is located at the edge of said capacitor pad, and the center line of two signal vias is parallel to the center line of two pins of said capacitor pad.
7. The circuit board structure of claim 6, wherein the signal vias have a diameter of 8 mils.
8. A circuit board structure for optimizing series tolerance split impedance according to claim 1, wherein each set of said capacitor pads is provided with a screen print.
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN221283414U true CN221283414U (en) | 2024-07-05 |
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