CN221225405U

CN221225405U - Analog-digital double-loop LDO circuit

Info

Publication number: CN221225405U
Application number: CN202323351684.3U
Authority: CN
Inventors: 李海鸥; 奥鹏龙; 陈庆; 章金标; 张春燕; 徐卫林; 蒋品群
Original assignee: Guilin University of Electronic Technology
Current assignee: Guilin University of Electronic Technology
Priority date: 2023-12-08
Filing date: 2023-12-08
Publication date: 2024-06-25
Anticipated expiration: 2033-12-08

Abstract

The utility model discloses an analog digital double-loop LDO circuit, which adopts a digital loop and an analog loop double-loop mode to divide a power tube into an analog power tube and a digital power tube, so that the load current is larger under the condition of the same power tube size; in addition, as the digital power tube of the analog digital double-loop LDO bears a part of current, the load current of the analog power tube changes into a part of the total current, so that the size of the analog power tube of the analog digital double-loop LDO is smaller than that of a power tube bearing all load current in a single analog loop LDO, the parasitic capacitance of the grid electrode of the analog power tube is smaller, the charging and discharging speed is faster, the transient response of a circuit is effectively improved, the pole position at the grid electrode is higher, the loop is easy to compensate, meanwhile, the load current of the analog power tube changes into a part of the total current, the pole position change of the output end is smaller, and the loop is easier to compensate.

Description

Analog-digital double-loop LDO circuit

Technical Field

The utility model relates to the technical field of integrated circuits, in particular to an analog-digital double-loop LDO (Low Dropout Regulaor, low dropout linear voltage regulator) circuit.

Background

LDO is an indispensable part of electronic equipment because LDO has the outstanding advantages of simple structure, low cost, small size and the like and is widely applied to power management circuits. With the rapid development of wearable portable electronic devices, miniaturization of electronic devices is more and more important, and the area of an indispensable power management chip is an important index, so that it is required to reduce the area of LDO as much as possible. Today, devices are miniaturized, and off-chip capacitive LDOs are widely used in wearable portable electronic devices due to their small area. However, one difficulty in the off-chip capacitor-less LDO design process is the design of loop stability, which is mainly due to: the pole of the LDO output end changes along with the change of the load current, when the load current of the system changes rapidly, the pole position of the LDO output end also changes rapidly, which affects the loop stability, and the problem is particularly prominent especially under the condition of large load current change range; the excessive power tube size can generate large parasitic capacitance, so that the transient response is influenced, and meanwhile, a low-frequency pole is generated on the grid electrode of the power tube, and the loop stability is also influenced. For this reason, the off-chip capacitor LDO needs to be improved in terms of large load current, stability, and transient response.

Disclosure of utility model

The utility model aims to solve the problem of loop stability of the existing off-chip capacitor LDO circuit and provides an analog digital double-loop LDO circuit.

In order to solve the problems, the utility model is realized by the following technical scheme:

An analog-digital double-loop LDO circuit is characterized by comprising an analog loop and a digital loop; the analog loop consists of an error amplifying circuit, a buffer stage circuit and an analog power tube circuit; the digital loop consists of a current detection circuit, a control circuit and a digital power tube circuit; the input of the error amplifying circuit is connected with bias voltages VB1 to VB3, a reference voltage VREF3 and a feedback voltage VFB; the error amplifying circuit is used for amplifying the difference value of the reference voltage VREF3 and the feedback voltage VFB of the output VOUT of the LDO circuit and outputting a corresponding error signal Vg; the input of the buffer stage circuit is connected with the bias voltage VB4 and the error signal Vg output by the error amplifying circuit; the buffer stage circuit is used for amplifying the error signal Vg and outputting the amplified error signal VG to drive the analog power tube circuit, and meanwhile, the stability of the analog loop is compensated; the input of the analog power tube circuit is connected with the output of the buffer stage circuit, and the analog power tube circuit is used for sampling the output VOUT of the LDO circuit as feedback voltage VFB of the input error amplifying circuit; the input of the current detection circuit is connected with the output of the analog power tube circuit; the current detection circuit is used for detecting the current of the analog power tube circuit and generating corresponding voltage V1; the input of the control circuit is connected with reference voltages VREF 1-VREF 2 and the voltage V1 output by the current detection circuit; the control circuit generates a 3-bit digital code under the triggering of the voltage V1 so as to control the conduction number of the digital power tubes of the digital power tube circuit; the digital power tube circuit outputs the output VOUT of the LDO circuit.

In the scheme, the error amplifying circuit comprises MOS tubes M1-M8 and a MOS tube MB1; the source electrode of the MOS tube M3, the source electrode of the MOS tube M4 and the source electrode of the MOS tube MB1 are connected with a power supply voltage VDD; the source electrode of the MOS tube M7 and the source electrode of the MOS tube M8 are grounded to GND; the grid electrode of the MOS tube MB1 is connected with the bias voltage VB1; the grid electrode of the MOS tube M6 and the MOS tube M6 are connected with bias voltage VB2; the grid electrodes of the MOS tube M8 and the MOS tube M8 are connected with bias voltage VB3; the grid electrode of the MOS tube M2 is connected with a reference voltage signal VREF3; the grid electrode of the MOS tube M1 forms a sampling input end of the error amplifying circuit and is connected with a sampling output end of the analog power tube circuit; the drain electrode of the MOS tube MB1, the source electrode of the MOS tube M1 and the source electrode of the MOS tube M2 are connected; the drain electrode of the MOS tube M1, the source electrode of the MOS tube M5 and the drain electrode of the MOS tube M7 are connected; the drain electrode of the MOS tube M2 is connected with the source electrode of the MOS tube M6 and the drain electrode of the MOS tube M8; the grid electrode of the MOS tube M3 is connected with the drain electrode, the grid electrode of the MOS tube M3 and the drain electrode of the MOS tube M5; the drain electrode of the MOS tube M4 is connected with the drain electrode of the MOS tube M6, and an output end of the error amplifying circuit is formed and connected with the input end of the buffer stage circuit.

In the scheme, the buffer stage circuit comprises MOS tubes M9-M13, a MOS tube MB2, a compensation capacitor Cm and a feedback resistor Rz; the source electrode of the MOS tube M9, the source electrode of the MOS tube M10 and the source electrode of the MOS tube M12 are connected with a power supply voltage VDD; the source electrode of the MOS tube M11, the source electrode of the MOS tube M13 and the source electrode of the MOS tube MB2 are grounded to GND; the grid electrode of the MOS tube MB2 is connected with the bias voltage VB4; the grid electrode of the MOS tube M9, the grid electrode of the MOS tube M10 and one end of the compensation capacitor Cm form an input end of a buffer stage circuit and are connected with an output end of the error amplifying circuit; the other end of the compensation capacitor Cm is connected with the output VOUT of the LDO circuit; the drain electrode of the MOS tube M9, the grid electrode of the MOS tube M12, the drain electrode of the MOS tube MB2 and one end of the feedback resistor Rz are connected; the other end of the feedback resistor Rz, the grid electrode of the MOS tube M12 and the grid electrode of the MOS tube M13 are connected, and an output end of the buffer stage circuit is formed and connected with the input end of the analog power tube circuit and the input end of the current detection circuit; the gate of the MOS transistor M11 is connected with the drain and the gate of the MOS transistor M131.

In the scheme, the analog power tube circuit comprises an analog power tube MPA and resistors R1-R2; the source electrode of the analog power tube MPA is connected with the power supply voltage VDD; the grid electrode of the analog power tube MPA forms the input end of the analog power tube MPA and is connected with the output end of the buffer stage circuit; one end of the drain electrode of the analog power tube MPA and the resistor R1 is connected with the output VOUT of the LDO circuit; the other end of the resistor R1 is connected with one end of the resistor R2, and is formed, and the sampling output end of the analog power tube circuit is connected with the sampling input end of the error amplifying circuit; the other end of the resistor R2 is grounded GND.

In the scheme, the current detection circuit comprises MOS transistors M14-M15; the source electrode of the MOS tube M14 is connected with the power supply voltage VDD; the source electrode of the MOS tube M15 is grounded to GND; the grid electrode of the MOS tube M14 forms the input end of the current detection circuit and is connected with the output end of the buffer stage circuit; the drain electrode of the MOS tube M14 is connected with the grid electrode and the drain electrode of the MOS tube M15, and the output end of the current detection circuit is connected with the input end of the control circuit.

In the above scheme, the control circuit includes a schmitt trigger SCHFF, comparators COM1 to COM2, OR gates OR1 to OR2; the 2 input ends of the comparator COM1 are respectively connected with a reference voltage VREF1 and a power supply voltage VDD; the 2 input ends of the comparator COM2 respectively reference the voltage VREF2 and the power supply voltage VDD; the input end of the Schmitt trigger SCHFF forms the input end of the control circuit and is connected with the output end of the current detection circuit; the 2 input ends of the OR gate OR1 are respectively connected with the output end of the comparator COM1 and the output end of the Schmitt trigger SCHFF, and the output end of the OR gate OR1 forms a first output end of the control circuit and is connected with the first input end of the digital power tube circuit; the 2 input ends of the OR gate OR2 are respectively connected with the output end of the comparator COM2 and the output end of the Schmitt trigger SCHFF, and the output end of the OR gate OR2 forms a second output end of the control circuit and is connected with the second input end of the digital power tube circuit; the output of schmitt trigger SCHFF forms a third output of the control circuit and is connected to a third input of the digital power tube circuit.

In the scheme, the digital power tube circuit comprises 3 digital power tubes MPD 1-MPD 3; the source electrode of the digital power tube MPD1, the source electrode of the digital power tube MPD2 and the source electrode of the digital power tube MPD3 are connected with a power supply voltage VDD; the drain electrode of the digital power tube MPD1 forms a first input end of a digital power tube circuit and is connected with a first output end of a control circuit; the drain electrode of the digital power tube MPD2 forms a second input end of the digital power tube circuit and is connected with a second output end of the control circuit; the drain electrode of the digital power tube MPD3 forms a third input end of the digital power tube circuit and is connected with a third output end of the control circuit; the drain of the digital power tube MPD1, the drain of the digital power tube MPD2 and the drain of the digital power tube MPD3 are connected and form the output VOUT of the LDO circuit.

Compared with the traditional single analog loop LDO, the utility model adopts the form of a digital loop and an analog loop double loop, and the power tube is divided into an analog power tube and a digital power tube, so that the load current is larger under the condition of the same power tube size; in addition, as the digital power tube of the analog digital double-loop LDO bears a part of current, the load current of the analog power tube changes into a part of the total current, so that the size of the analog power tube of the analog digital double-loop LDO is smaller than that of a power tube bearing all load current in a single analog loop LDO, the parasitic capacitance of the grid electrode of the analog power tube is smaller, the charging and discharging speed is faster, the transient response of a circuit is effectively improved, the pole position at the grid electrode is higher, the loop is easy to compensate, meanwhile, the load current of the analog power tube changes into a part of the total current, the pole position change of the output end is smaller, and the loop is easier to compensate.

Drawings

FIG. 1 is a schematic diagram of an analog-to-digital dual-loop LDO circuit;

FIG. 2 is a diagram illustrating a simulation of an analog-to-digital dual-loop LDO circuit with or without digital loop load capability;

Fig. 3 is a light-load and heavy-load loop baud diagram of an analog-to-digital dual-loop LDO circuit.

Detailed Description

The utility model will be further described in detail below with reference to specific examples and with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the utility model more apparent.

Referring to fig. 1, an analog-to-digital dual loop LDO circuit includes an analog loop and a digital loop. The analog loop is composed of an error amplifying circuit, a buffer stage circuit and an analog power tube circuit. The digital loop is composed of a current detection circuit, a control circuit and a digital power tube circuit. The input of the error amplifying circuit is connected with bias voltages VB1 to VB3, reference voltage VREF3 and feedback voltage VFB. The error amplifying circuit is used for amplifying the difference value between the reference voltage VREF3 and the feedback voltage VFB of the output VOUT of the LDO circuit and outputting a corresponding error signal Vg. The input of the buffer stage circuit is connected with the bias voltage VB4 and the error signal Vg output by the error amplifying circuit. The buffer stage circuit is used for amplifying the error signal Vg and outputting the amplified error signal Vg to drive the analog power tube circuit, and meanwhile, the stability of the analog loop circuit is compensated. The input of the analog power tube circuit is connected with the output of the buffer stage circuit, and the analog power tube circuit is used for sampling the output VOUT of the LDO circuit as feedback voltage VFB of the input error amplifying circuit. The input of the current detection circuit is connected with the output of the analog power tube circuit. The current detection circuit is used for detecting the current of the analog power tube circuit and generating a corresponding voltage V1. The input of the control circuit is connected with reference voltages VREF 1-VREF 2 and the voltage V1 of the output of the current detection circuit. The control circuit generates a 3-bit digital code under the triggering of the voltage V1 so as to control the conduction number of the digital power tubes of the digital power tube circuit. The digital power tube circuit outputs the output VOUT of the LDO circuit.

The error amplifying circuit includes MOS transistors M1 to M8 and MOS transistor MB1. The source of the MOS transistor M3, the source of the MOS transistor M4 and the source of the MOS transistor MB1 are connected with the power supply voltage VDD. The source of the MOS transistor M7 and the source of the MOS transistor M8 are grounded to GND. The gate of the MOS transistor MB1 is connected with the bias voltage VB1. The grid electrode of the MOS tube M6 and the MOS tube M6 are connected with the bias voltage VB2. The gates of the MOS transistor M8 and the MOS transistor M8 are connected with bias voltage VB3. The gate of the MOS transistor M2 is connected with a reference voltage signal VREF3. The grid electrode of the MOS tube M1 forms a sampling input end of the error amplifying circuit and is connected with a sampling output end of the analog power tube circuit. The drain electrode of the MOS tube MB1, the source electrode of the MOS tube M1 and the source electrode of the MOS tube M2 are connected. The drain electrode of the MOS tube M1, the source electrode of the MOS tube M5 and the drain electrode of the MOS tube M7 are connected. The drain electrode of the MOS tube M2 is connected with the source electrode of the MOS tube M6 and the drain electrode of the MOS tube M8. The grid electrode of the MOS tube M3 is connected with the drain electrode, the grid electrode of the MOS tube M3 and the drain electrode of the MOS tube M5. The drain electrode of the MOS tube M4 is connected with the drain electrode of the MOS tube M6, and an output end of the error amplifying circuit is formed and connected with the input end of the buffer stage circuit.

The buffer stage circuit comprises MOS tubes M9-M13, a MOS tube MB2, a compensation capacitor Cm and a feedback resistor Rz. The source electrode of the MOS tube M9, the source electrode of the MOS tube M10 and the source electrode of the MOS tube M12 are connected with the power supply voltage VDD. The source of MOS transistor M11, the source of MOS transistor M13 and the source of MOS transistor MB2 are grounded to GND. The gate of the MOS transistor MB2 is connected with the bias voltage VB4. The grid electrode of the MOS tube M9, the grid electrode of the MOS tube M10 and one end of the compensation capacitor Cm form the input end of the buffer stage circuit and are connected with the output end of the error amplifying circuit. The other end of the compensation capacitor Cm is connected with the output VOUT of the LDO circuit. The drain electrode of the MOS tube M9, the grid electrode of the MOS tube M12, the drain electrode of the MOS tube MB2 and one end of the feedback resistor Rz are connected. The other end of the feedback resistor Rz, the grid electrode of the MOS tube M12 and the grid electrode of the MOS tube M13 are connected, and an output end of the buffer stage circuit is formed and connected with the input end of the analog power tube circuit and the input end of the current detection circuit. The gate of the MOS transistor M11 is connected with the drain and the gate of the MOS transistor M131.

The analog power tube circuit includes an analog power tube MPA and resistors R1 to R2. The source of the analog power tube MPA is connected with the power supply voltage VDD. The grid electrode of the analog power tube MPA forms the input end of the analog power tube MPA and is connected with the output end of the buffer stage circuit. The drain of the analog power tube MPA and one end of the resistor R1 are connected with the output VOUT of the LDO circuit. The other end of the resistor R1 is connected with one end of the resistor R2, and the sampling output end of the analog power tube circuit is connected with the sampling input end of the error amplifying circuit. The other end of the resistor R2 is grounded GND.

The current detection circuit comprises MOS transistors M14-M15. The source of the MOS transistor M14 is connected to the power supply voltage VDD. The source of the MOS transistor M15 is grounded GND. The grid electrode of the MOS tube M14 forms the input end of the current detection circuit and is connected with the output end of the buffer stage circuit. The drain electrode of the MOS tube M14 is connected with the grid electrode and the drain electrode of the MOS tube M15, and the output end of the current detection circuit is connected with the input end of the control circuit.

The control circuit includes a schmitt trigger SCHFF, comparators COM1 to COM2, and OR gates OR1 to OR2. The 2 input terminals of the comparator COM1 are respectively connected to the reference voltage VREF1 and the power supply voltage VDD. The 2 inputs of the comparator COM2 are referenced to the voltage VREF2 and the supply voltage VDD, respectively. Wherein reference voltage VREF1 > reference voltage VREF2. The input of the schmitt trigger SCHFF forms the input of the control circuit and is connected to the output of the current detection circuit. The 2 input ends of the OR gate OR1 are respectively connected with the output end of the comparator COM1 and the output end of the Schmitt trigger SCHFF, and the output end of the OR gate OR1 forms a first output end of the control circuit and is connected with the first input end of the digital power tube circuit. The 2 input ends of the OR gate OR2 are respectively connected with the output end of the comparator COM2 and the output end of the Schmitt trigger SCHFF, and the output end of the OR gate OR2 forms a second output end of the control circuit and is connected with the second input end of the digital power tube circuit. The output of schmitt trigger SCHFF forms a third output of the control circuit and is connected to a third input of the digital power tube circuit.

The digital power tube circuit comprises 3 digital power tubes MPD 1-MPD 3, wherein the sizes of the 3 digital power tubes MPD 1-MPD 3 are the same. The source of the digital power tube MPD1, the source of the digital power tube MPD2 and the source of the digital power tube MPD3 are connected with the power supply voltage VDD. The drain electrode of the digital power tube MPD1 forms a first input end of the digital power tube circuit and is connected with a first output end of the control circuit. The drain electrode of the digital power tube MPD2 forms a second input end of the digital power tube circuit and is connected with a second output end of the control circuit. The drain electrode of the digital power tube MPD3 forms a third input end of the digital power tube circuit and is connected with a third output end of the control circuit. The drain of the digital power tube MPD1, the drain of the digital power tube MPD2 and the drain of the digital power tube MPD3 are connected and form the output VOUT of the LDO circuit.

The specific operation principle and performance of the analog-digital dual-loop LDO circuit shown in fig. 1 will be described in detail by using an example.

When the total load current of the output end VOUT of the analog-digital double-loop LDO circuit is 1mA, the circuit only works in an analog loop, the analog power tube MPA receives all load current, at the moment, the current flowing through the MOS tube M14 is also small due to the mirror effect, the generated V1 voltage is low, so that V2 is high level, and the digital power tube MPD is completely closed.

When the total load current of the output end VOUT of the analog-digital double-loop LDO circuit jumps to 140mA, the current flowing through the analog power tube MPA is increased to 140mA, the current flowing through the MOS tube M14 is gradually increased due to the mirror effect, the voltage V1 generated at the moment is increased to the upper threshold voltage of the hysteresis comparison, the output of the hysteresis comparator is changed from low to high, V2 is changed to low level, the digital power tube MPD is conducted, 110mA of current is provided for the load, and meanwhile, the load current of the analog power tube MPA is reduced to 30mA from 140 mA.

When the total load current of the output end VOUT of the analog digital double-loop LDO circuit continues to increase to 250mA, the on state of the digital power tube MPD remains unchanged, and the load current of the analog power tube MPA continues to increase from 30mA to 140mA.

When the total load current of the output end VOUT of the analog digital double-loop LDO circuit jumps from 250mA to 115mA, the load current of the digital power tube MPD is 110mA, the load current of the analog power tube MPA is reduced to 5mA, the current flowing through the MOS tube M14 is gradually reduced due to the mirror effect, the voltage V1 generated at the moment is reduced to the lower threshold voltage of hysteresis comparison, V2 becomes high level, the digital power tube MPD is closed, the analog power tube MPA bears all load currents, and the load current of the analog power tube MPA is increased to 115mA from 5mA.

When the total load current of the output end VOUT of the analog digital double-loop LDO circuit is reduced to 1mA, the total load current is borne by the analog power tube MPA, and the load current of the analog power tube MPA is also gradually reduced to 1mA.

The control module is used for controlling the load current when the digital power tube MPD is conducted.

When VDD is smaller than VREF2, the grid voltages of the digital power transistors MPD1 to MPD3 are not limited, and the load current is not larger than 110mA when the digital power transistors are fully conducted.

When VREF2 is less than or equal to VDD and less than or equal to VREF1, the voltage of V2<0> is high, and the voltage of the grid electrode of the corresponding digital power tube MPD1 is limited to be high, so that the digital power tube cannot be started; the gate voltages of the other digital power tubes MPD2 and MPD3 are not limited, and the load current is not more than 110mA when the digital power tubes are fully conducted.

When the power supply voltage VDD is more than VREF1, the voltages of V2<0> and V2<1> are high, and the voltages of the grid electrodes of the corresponding digital power transistors MPD1 and MPD2 are limited to be high, so that the digital power transistors cannot be started; the gate voltage of the other digital power tubes MPD3 is not limited, and the load current is not more than 110mA when the digital power tubes MPD3 are fully conducted.

Fig. 2 is a simulation diagram of an analog-digital dual-loop LDO circuit with digital loop load capability, from which it can be seen that the load capability is up to 250mA in the case of digital loop, and the maximum load current is only 160mA in the case of no digital loop. The digital loop increases the load capacity from 160mA to 270mA, expanding 110mA. To leave a margin, the maximum load current was set to 250mA.

Fig. 3 is a light-load and heavy-load loop baud diagram of an analog-to-digital dual-loop LDO circuit. The loop circuit has better stability under light load and heavy load, the phase margin is about 60 degrees, and the change along with load current is smaller.

The analog power tube of the traditional single analog loop LDO circuit has the required size of 2500u/0.18u when carrying 250mA load current. The analog-digital double-loop LDO circuit provided by the utility model also has the advantages that when the load current is 250mA, the size of the analog power tube MPA is only 1400u/0.18u, the size of the digital power tube MPD is 800u/0.18u, the total size of the power tube is only 2200u/0.18u, and the total size is reduced by 13%. Therefore, the circuit provided by the utility model reduces the size of the analog power tube and the parasitic capacitance of the grid electrode of the analog power tube to a large extent, so that the analog loop frequency compensation is easier to realize, the design difficulty of the analog loop is reduced, and the total size is reduced to some extent.

It should be noted that, although the examples described above are illustrative, this is not a limitation of the present utility model, and thus the present utility model is not limited to the above-described specific embodiments. Other embodiments, which are apparent to those skilled in the art from consideration of the specification and practice of the utility model disclosed herein, are considered to be within the scope of the utility model as claimed.

Claims

1. An analog-digital double-loop LDO circuit is characterized by comprising an analog loop and a digital loop; the analog loop consists of an error amplifying circuit, a buffer stage circuit and an analog power tube circuit; the digital loop consists of a current detection circuit, a control circuit and a digital power tube circuit;

The input of the error amplifying circuit is connected with bias voltages VB1 to VB3, a reference voltage VREF3 and a feedback voltage VFB; the error amplifying circuit is used for amplifying the difference value of the reference voltage VREF3 and the feedback voltage VFB of the output VOUT of the LDO circuit and outputting a corresponding error signal Vg;

The input of the buffer stage circuit is connected with the bias voltage VB4 and the error signal Vg output by the error amplifying circuit; the buffer stage circuit is used for amplifying the error signal Vg and outputting the amplified error signal VG to drive the analog power tube circuit, and meanwhile, the stability of the analog loop is compensated;

The input of the analog power tube circuit is connected with the output of the buffer stage circuit, and the analog power tube circuit is used for sampling the output VOUT of the LDO circuit as feedback voltage VFB of the input error amplifying circuit;

the input of the current detection circuit is connected with the output of the analog power tube circuit; the current detection circuit is used for detecting the current of the analog power tube circuit and generating corresponding voltage V1;

The input of the control circuit is connected with reference voltages VREF 1-VREF 2 and the voltage V1 output by the current detection circuit; the control circuit generates a 3-bit digital code under the triggering of the voltage V1 so as to control the conduction number of the digital power tubes of the digital power tube circuit;

the digital power tube circuit outputs the output VOUT of the LDO circuit.

2. The analog-digital double-loop LDO circuit according to claim 1, wherein the error amplifying circuit comprises MOS transistors M1-M8 and MOS transistor MB1;

The source electrode of the MOS tube M3, the source electrode of the MOS tube M4 and the source electrode of the MOS tube MB1 are connected with a power supply voltage VDD; the source electrode of the MOS tube M7 and the source electrode of the MOS tube M8 are grounded to GND; the grid electrode of the MOS tube MB1 is connected with the bias voltage VB1; the grid electrode of the MOS tube M6 and the MOS tube M6 are connected with bias voltage VB2; the grid electrodes of the MOS tube M8 and the MOS tube M8 are connected with bias voltage VB3; the grid electrode of the MOS tube M2 is connected with a reference voltage signal VREF3; the grid electrode of the MOS tube M1 forms a sampling input end of the error amplifying circuit and is connected with a sampling output end of the analog power tube circuit; the drain electrode of the MOS tube MB1, the source electrode of the MOS tube M1 and the source electrode of the MOS tube M2 are connected; the drain electrode of the MOS tube M1, the source electrode of the MOS tube M5 and the drain electrode of the MOS tube M7 are connected; the drain electrode of the MOS tube M2 is connected with the source electrode of the MOS tube M6 and the drain electrode of the MOS tube M8; the grid electrode of the MOS tube M3 is connected with the drain electrode, the grid electrode of the MOS tube M3 and the drain electrode of the MOS tube M5; the drain electrode of the MOS tube M4 is connected with the drain electrode of the MOS tube M6, and an output end of the error amplifying circuit is formed and connected with the input end of the buffer stage circuit.

3. The analog-digital double-loop LDO circuit according to claim 1, wherein the buffer stage circuit comprises MOS transistors M9-M13, MOS transistor MB2, compensation capacitor Cm and feedback resistor Rz;

The source electrode of the MOS tube M9, the source electrode of the MOS tube M10 and the source electrode of the MOS tube M12 are connected with a power supply voltage VDD; the source electrode of the MOS tube M11, the source electrode of the MOS tube M13 and the source electrode of the MOS tube MB2 are grounded to GND; the grid electrode of the MOS tube MB2 is connected with the bias voltage VB4;

The grid electrode of the MOS tube M9, the grid electrode of the MOS tube M10 and one end of the compensation capacitor Cm form an input end of a buffer stage circuit and are connected with an output end of the error amplifying circuit; the other end of the compensation capacitor Cm is connected with the output VOUT of the LDO circuit; the drain electrode of the MOS tube M9, the grid electrode of the MOS tube M12, the drain electrode of the MOS tube MB2 and one end of the feedback resistor Rz are connected; the other end of the feedback resistor Rz, the grid electrode of the MOS tube M12 and the grid electrode of the MOS tube M13 are connected, and an output end of the buffer stage circuit is formed and connected with the input end of the analog power tube circuit and the input end of the current detection circuit; the gate of the MOS transistor M11 is connected with the drain and the gate of the MOS transistor M131.

4. The analog-digital double-loop LDO circuit according to claim 1, wherein the analog power tube circuit comprises an analog power tube MPA and resistors R1-R2;

The source electrode of the analog power tube MPA is connected with the power supply voltage VDD; the grid electrode of the analog power tube MPA forms the input end of the analog power tube MPA and is connected with the output end of the buffer stage circuit; one end of the drain electrode of the analog power tube MPA and the resistor R1 is connected with the output VOUT of the LDO circuit; the other end of the resistor R1 is connected with one end of the resistor R2, and is formed, and the sampling output end of the analog power tube circuit is connected with the sampling input end of the error amplifying circuit; the other end of the resistor R2 is grounded GND.

5. The analog-digital double-loop LDO circuit according to claim 1, wherein the current detection circuit comprises MOS transistors M14-M15;

The source electrode of the MOS tube M14 is connected with the power supply voltage VDD; the source electrode of the MOS tube M15 is grounded to GND; the grid electrode of the MOS tube M14 forms the input end of the current detection circuit and is connected with the output end of the buffer stage circuit; the drain electrode of the MOS tube M14 is connected with the grid electrode and the drain electrode of the MOS tube M15, and the output end of the current detection circuit is connected with the input end of the control circuit.

6. An analog digital dual loop LDO circuit according to claim 1, wherein the control circuit comprises a schmitt trigger SCHFF, comparators COM 1-COM 2, and OR gates OR 1-OR 2;

The 2 input ends of the comparator COM1 are respectively connected with a reference voltage VREF1 and a power supply voltage VDD; the 2 input ends of the comparator COM2 respectively reference the voltage VREF2 and the power supply voltage VDD; the input end of the Schmitt trigger SCHFF forms the input end of the control circuit and is connected with the output end of the current detection circuit; the 2 input ends of the OR gate OR1 are respectively connected with the output end of the comparator COM1 and the output end of the Schmitt trigger SCHFF, and the output end of the OR gate OR1 forms a first output end of the control circuit and is connected with the first input end of the digital power tube circuit; the 2 input ends of the OR gate OR2 are respectively connected with the output end of the comparator COM2 and the output end of the Schmitt trigger SCHFF, and the output end of the OR gate OR2 forms a second output end of the control circuit and is connected with the second input end of the digital power tube circuit; the output of schmitt trigger SCHFF forms a third output of the control circuit and is connected to a third input of the digital power tube circuit.

7. The analog-to-digital dual-loop LDO circuit of claim 1, wherein the digital power tube circuit comprises 3 digital power tubes MPD 1-MPD 3;

The source electrode of the digital power tube MPD1, the source electrode of the digital power tube MPD2 and the source electrode of the digital power tube MPD3 are connected with a power supply voltage VDD; the drain electrode of the digital power tube MPD1 forms a first input end of a digital power tube circuit and is connected with a first output end of a control circuit; the drain electrode of the digital power tube MPD2 forms a second input end of the digital power tube circuit and is connected with a second output end of the control circuit; the drain electrode of the digital power tube MPD3 forms a third input end of the digital power tube circuit and is connected with a third output end of the control circuit; the drain of the digital power tube MPD1, the drain of the digital power tube MPD2 and the drain of the digital power tube MPD3 are connected and form the output VOUT of the LDO circuit.