CN221202205U - Charging and discharging circuit of Farad capacitor - Google Patents
Charging and discharging circuit of Farad capacitor Download PDFInfo
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- CN221202205U CN221202205U CN202323165449.7U CN202323165449U CN221202205U CN 221202205 U CN221202205 U CN 221202205U CN 202323165449 U CN202323165449 U CN 202323165449U CN 221202205 U CN221202205 U CN 221202205U
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- 239000003990 capacitor Substances 0.000 title claims abstract description 91
- 238000007599 discharging Methods 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 description 5
- 230000007547 defect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- 238000005516 engineering process Methods 0.000 description 1
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- Charge And Discharge Circuits For Batteries Or The Like (AREA)
Abstract
The application relates to a charge-discharge circuit of a Farad capacitor, comprising: the DC power supply, the Faraday capacitor and the load, wherein an NMOS tube is connected between the DC power supply and the Faraday capacitor, the drain electrode of the NMOS tube is connected with the DC power supply, and the source electrode is connected with the anode of the Faraday capacitor; the load is connected between the direct current power supply and the NMOS tube; the charging and discharging circuit further comprises a voltage dividing resistor connected in parallel with two ends of the NMOS tube, one end of the voltage dividing resistor is connected with the direct-current power supply, the load and a first connection point between the drain electrodes of the NMOS tube, and the other end of the voltage dividing resistor is connected with a second connection point between the source electrode of the NMOS tube and the positive electrode of the Faraday capacitor. According to the technical scheme, the charging and discharging circuit of the Faraday capacitor can be simplified, and the charging efficiency of the Faraday capacitor can be improved.
Description
Technical Field
The application relates to the technical field of circuits, in particular to a charging and discharging circuit of a Farad capacitor.
Background
Various electric appliances are often used in daily work and life, and the energy sources used by the traditional electric appliances are mainly two, namely an alternating current power supply and a storage battery power supply. The alternating current power supply is most commonly used, and has the advantages of stable voltage and continuous use, but has the defects that the nearby alternating current power supply is needed in a use field, and the electric appliance is provided with a power line, so that the electric appliance is inconvenient to use in some environments and has certain potential safety hazards of electric shock. The battery power supply can overcome the defects of the alternating current power supply, but the battery needs to be fully charged before being used, and the charging time is long, generally, a plurality of hours are needed, and the use is inconvenient. Therefore, recently, electric appliances using a Faraday capacitor as an energy source appear in the market, the Faraday capacitor is a capacitor with larger capacitance, and can store certain electric energy after being charged, and the electric appliance is characterized in that: 1. the battery can be charged by using larger current, so that the charging time is short, and the charging can be completed in tens of seconds generally, thereby overcoming the defect of longer charging time of a storage battery power supply; 2. the method is particularly environment-friendly, and has no pollution from the manufacturing process to waste; 3. the service life is long, the charge and discharge times of the capacitor can reach hundreds of thousands, and the charge and discharge times of the storage battery are only hundreds. How to charge the Faraday capacitor is a brand new important technology, the Faraday capacitor is greatly different from the traditional electrolytic capacitor, and the single capacitor has a low rated voltage value, generally only 2.5-2.7V, and a plurality of capacitors are needed to be connected in series for use so as to improve the working voltage although the capacitance of the Faraday capacitor is larger; in addition, the Faraday capacitor inevitably has the difference in capacity, internal resistance and the like during manufacturing, and the capacity difference becomes larger during use; the farad capacitor with small capacity is fully charged first when the series charging is carried out, and if the series charging is continued, the farad capacitor is overcharged and breaks down to cause the farad capacitor to lose effectiveness.
In order to overcome the phenomenon of overcharging of the Faraday capacitor, the conventional charging method is to reduce the power supply voltage to be the same as the cutoff voltage of the Faraday capacitor through a DC-DC voltage reduction circuit, and stop charging when the cutoff voltage is reached. Or charging by using a constant current method through a constant current circuit, and stopping charging when the voltage of the capacitor reaches the cut-off voltage through detecting the voltage of the capacitor. The step-down circuit or the constant current circuit is introduced, so that the circuit complexity is increased, the charging current is limited by the step-down circuit and the constant current circuit, the charging time of the Faraday capacitor is prolonged, and the charging efficiency is reduced.
Disclosure of Invention
In order to solve the technical problems, the application provides a charging and discharging circuit of a Farad capacitor, which is used for simplifying the charging and discharging circuit of the Farad capacitor and improving the charging efficiency of the Farad capacitor.
The application provides a charge-discharge circuit of a Farad capacitor, which comprises: the DC power supply, the Faraday capacitor and the load, wherein an NMOS tube is connected between the DC power supply and the Faraday capacitor, the drain electrode of the NMOS tube is connected with the DC power supply, and the source electrode is connected with the anode of the Faraday capacitor; the load is connected between the direct current power supply and the NMOS tube; the charging and discharging circuit further comprises a voltage dividing resistor connected in parallel with two ends of the NMOS tube, one end of the voltage dividing resistor is connected with the direct-current power supply, the load and a first connection point between the drain electrodes of the NMOS tube, and the other end of the voltage dividing resistor is connected with a second connection point between the source electrode of the NMOS tube and the positive electrode of the Faraday capacitor.
In one embodiment, the voltage dividing resistor comprises a first voltage dividing resistor and a second voltage dividing resistor which are connected in series, one end of the first voltage dividing resistor is connected with the first connection point, one end of the second voltage dividing resistor is connected with the second connection point, and a third connection point of the other end of the first voltage dividing resistor and the other end of the second voltage dividing resistor is connected with the grid electrode of the NMOS tube.
In one embodiment, the charge-discharge circuit further comprises a current limiting resistor connected between the dc power supply and the NMOS transistor.
In one embodiment, the charge-discharge circuit further comprises a first voltage stabilizing diode connected in parallel across the second voltage dividing resistor.
In one embodiment, the charge-discharge circuit further comprises a second zener diode connected in parallel between the second connection point and the negative electrode of the faraday capacitor.
In one embodiment, the charge-discharge circuit further comprises an auxiliary power supply, the auxiliary power supply being connected at the second connection point.
The technical scheme of the application has the following beneficial technical effects:
According to the charge-discharge circuit of the Faraday capacitor, the Faraday capacitor is charged and stopped by the NMOS tube by utilizing the characteristics of the NMOS tube, and the source electrode of the NMOS tube is connected with the Faraday capacitor, so that when the voltage difference between the grid electrode and the source electrode of the NMOS tube is larger than the grid threshold voltage of the NMOS tube, the NMOS tube is conducted to charge the Faraday capacitor; when the Faraday capacitor is gradually charged and the capacitor voltage is gradually increased until the voltage reaches the cutoff voltage of the Faraday capacitor, the voltage difference between the grid electrode and the source electrode of the NMOS tube is equal to or smaller than the threshold voltage of the grid electrode of the NMOS tube, and the Faraday capacitor is stopped being charged. Because no voltage-reducing circuit or constant-current circuit is needed, the number of elements is small, components such as voltage reduction, constant current and voltage detection are omitted, the circuit structure is simplified, the circuit cost is reduced, the voltage-reducing circuit or constant-current circuit is not limited, large-current charging can be realized, current expansion is not needed, the charging time of a Farad capacitor is shortened, the charging speed is improved, and the charging efficiency is improved.
Drawings
The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present application will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. In the drawings, embodiments of the application are illustrated by way of example and not by way of limitation, and like reference numerals refer to similar or corresponding parts and in which:
fig. 1 is a schematic circuit diagram of a charge-discharge circuit of a faraday capacitor according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It should be understood that when the terms "first," "second," and the like are used in the claims, the specification and the drawings of the present application, they are used merely for distinguishing between different objects and not for describing a particular sequential order. The terms "comprises" and "comprising" when used in the specification and claims of the present application are taken to specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The application provides a charge-discharge circuit of a Faraday capacitor, which is used for charging and discharging the Faraday capacitor. The faraday capacitor can be a faraday capacitor group formed by connecting a plurality of faraday capacitors in series.
Fig. 1 is a schematic circuit diagram of a charge-discharge circuit of a faraday capacitor according to an embodiment of the present application. As shown in fig. 1, the charge-discharge circuit includes: a DC power supply, a Faraday capacitor and a load. The DC power supply is connected to the connection J1, the Faraday capacitor is connected to the connection J2, and the load is connected to the connection VCC_IN to supply power to the load. The NMOS tube Q1 is connected between the DC power supply and the Faraday capacitor, the drain electrode of the NMOS tube Q1 is connected with the DC power supply, and the source electrode is connected with the anode of the Faraday capacitor. The load is connected between the direct current power supply and the NMOS transistor Q1.
The charge-discharge circuit further comprises a voltage dividing resistor connected in parallel with two ends of the NMOS tube, one end of the voltage dividing resistor is connected with a first connection point between a direct-current power supply, a load and the drain electrode of the NMOS tube Q1, and the other end of the voltage dividing resistor is connected with a second connection point between the source electrode of the NMOS tube Q1 and the positive electrode of the Faraday capacitor. In the embodiment shown in fig. 1, the voltage dividing resistor includes a first voltage dividing resistor R2 and a second voltage dividing resistor R3 connected in series, one end of the first voltage dividing resistor R2 is connected to the first connection point, one end of the second voltage dividing resistor R3 is connected to the second connection point, and a third connection point between the other end of the first voltage dividing resistor R2 and the other end of the second voltage dividing resistor R3 is connected to the gate of the NMOS transistor Q1.
Optionally, as shown in fig. 1, the charge-discharge circuit further includes a current limiting resistor R1 connected between the dc power supply and the NMOS transistor Q1, so as to prevent the current passing through the NMOS transistor Q1 from being too large, and protect the NMOS transistor Q1.
Optionally, as shown in fig. 1, the charge-discharge circuit further includes a first zener diode D1 connected in parallel across the second voltage dividing resistor R3. After the first voltage stabilizing diode D1 breaks down in the reverse direction due to the too high voltage, the terminal voltage is kept unchanged within a certain range, so that the too high gate voltage of the NMOS tube Q1 is prevented.
Optionally, as shown in fig. 1, the charge-discharge circuit further includes a second zener diode D2 connected in parallel between the second connection point and the negative electrode of the faraday capacitor. The second zener diode D2 is used to prevent the positive plate voltage of the faraday capacitor from being too high.
Optionally, the charging and discharging circuit further includes an auxiliary power source, which is connected to the second connection point and is used for auxiliary power supply of the load, for example, the auxiliary power source may be a battery.
In the charge-discharge circuit, the NMOS transistor needs to be turned on when the voltage difference between the gate and the source is greater than the gate threshold voltage V GS and lower than V GS. In the charging process of the Faraday capacitor, when J1 is electrified normally, the direct current power supply supplies power to the load and charges the Faraday capacitor at the same time. The voltage of the faraday capacitor cannot be suddenly changed due to the capacitance characteristic, but can only be slowly increased. And when the voltage of the Faraday capacitor reaches the charging cut-off voltage, the Faraday capacitor is fully charged. In fig. 1, the voltage dividing resistors R2 and R3 are connected in series to divide voltage, and the appropriate resistance is set so that the voltage is satisfied when charging is completed:
V2-V1＝VGS
wherein V2 is the serial voltage division value of R2 and R3 when the Farad capacitor is fully charged, V1 is the charge cut-off voltage of the Farad capacitor, and V GS is the gate threshold voltage of the NMOS tube.
The maximum charge voltage of the faraday capacitor is v1=v0-V GS, where V0 is the supply voltage.
As an example, when the power supply voltage v0=24v, the capacitor charge cutoff voltage v1=18v, and the n_mos transistor gate threshold voltage V GS =4v (V GS does not exceed 20V), the R2, R3 resistances are calculated:
When the charging is stopped, let v2—v1=v GS =4v, the following formula is adopted:
V2-V1＝(V0-V1)*R3/(R2+R3)
＝(24-18)*R3/(R2+R3)＝4V
the resistance ratio can be obtained: r2/r3=1/2.
To reduce the power of the voltage-stabilizing tube and the power consumption of the circuit, R2=11kΩ and R3=22kΩ are adopted.
Substituting the R2 and R3 resistance values into the equation, assuming that the Farad capacitor is initially at 0V, the charging is started by:
V2-V1＝(V0-V1)*R3/(R2+R3)
＝(24-0)*R3/(R2+R3)＝16V
The N_MOS transistor is conducted above a threshold voltage V GS. And less than 20V (when V2-V1 approaches or exceeds 20V, the regulator D1 should be added to limit the gate-source voltage difference).
When the Faraday capacitor is fully charged, the voltage difference between the grid electrode and the source electrode of the NMOS tube is smaller than V GS, the NMOS tube Q1 is cut off, and meanwhile, the current of the branch where the divider resistors R2 and R3 are is located is extremely small, so that the Faraday capacitor finishes charging. In addition, the second zener diode D2 also prevents the voltage of the faraday capacitor from increasing further, thereby protecting the faraday capacitor from damage due to overvoltage.
In the discharging process of the Faraday capacitor, when the direct current power supply is in power failure, and when V1 is larger than V0, the NMOS tube Q1 is cut off, the Faraday capacitor discharges, and a backup power supply is provided for a load through the branches of the resistors R2 and R3.
The specific structure and technical principle of the charge-discharge circuit of the faraday capacitor of the present application are described above through specific embodiments. By the technical scheme provided by the application, the charging and discharging circuit of the Faraday capacitor can be simplified and the charging efficiency of the Faraday capacitor can be improved.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (6)
1. A charge-discharge circuit of a faraday capacitor, comprising: the DC power supply, the Faraday capacitor and the load, wherein an NMOS tube is connected between the DC power supply and the Faraday capacitor, the drain electrode of the NMOS tube is connected with the DC power supply, and the source electrode is connected with the anode of the Faraday capacitor; the load is connected between the direct current power supply and the NMOS tube;
The charging and discharging circuit further comprises a voltage dividing resistor connected in parallel with two ends of the NMOS tube, one end of the voltage dividing resistor is connected with the direct-current power supply, the load and a first connection point between the drain electrodes of the NMOS tube, and the other end of the voltage dividing resistor is connected with a second connection point between the source electrode of the NMOS tube and the positive electrode of the Faraday capacitor.
2. The charge-discharge circuit of a faraday capacitor according to claim 1, wherein the voltage dividing resistor comprises a first voltage dividing resistor and a second voltage dividing resistor connected in series, one end of the first voltage dividing resistor is connected to the first connection point, one end of the second voltage dividing resistor is connected to the second connection point, and a third connection point of the other end of the first voltage dividing resistor and the other end of the second voltage dividing resistor is connected to the gate of the NMOS tube.
3. The faraday capacitor charging and discharging circuit of claim 2, further comprising a current limiting resistor connected between the dc power supply and the NMOS tube.
4. A faraday capacitor charging and discharging circuit according to claim 3, further comprising a first zener diode connected in parallel across the second divider resistor.
5. The faraday capacitor charging and discharging circuit of claim 4, further comprising a second zener diode connected in parallel between the second connection point and the negative electrode of the faraday capacitor.
6. A faraday capacitor charging and discharging circuit according to claim 5, characterized in that the charging and discharging circuit further comprises an auxiliary power supply, which auxiliary power supply is connected at the second connection point.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202323165449.7U CN221202205U (en) | 2023-11-23 | 2023-11-23 | Charging and discharging circuit of Farad capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202323165449.7U CN221202205U (en) | 2023-11-23 | 2023-11-23 | Charging and discharging circuit of Farad capacitor |
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| CN221202205U true CN221202205U (en) | 2024-06-21 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202323165449.7U Active CN221202205U (en) | 2023-11-23 | 2023-11-23 | Charging and discharging circuit of Farad capacitor |
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- 2023-11-23 CN CN202323165449.7U patent/CN221202205U/en active Active
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