CN221177728U - Ethernet interface interconnection circuit - Google Patents
Ethernet interface interconnection circuit Download PDFInfo
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- CN221177728U CN221177728U CN202322930389.7U CN202322930389U CN221177728U CN 221177728 U CN221177728 U CN 221177728U CN 202322930389 U CN202322930389 U CN 202322930389U CN 221177728 U CN221177728 U CN 221177728U
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Abstract
The utility model discloses an Ethernet interface interconnection circuit, which comprises a first terminal, a second terminal, a first PHY module, a second PHY module and a coupling unit, wherein the first terminal is connected with the second terminal; the first terminal is connected with the coupling unit through a first PHY module; the second terminal is connected with the coupling unit through a second PHY module; the first PHY module and the second PHY module are connected with the coupling unit in pairs through differential lines of UTP ports. The utility model has simple structure, realizes the interconnection circuit of the Ethernet interface without a network transformer by the opposite connection of the differential line of the UTP port of the PHY chip and the capacitor based on the coupling mode, saves the PCB area and improves the adaptability of scene application.
Description
Technical Field
The utility model relates to the technical field of interface circuits, in particular to an Ethernet interface interconnection circuit.
Background
Ethernet is the most common communication protocol for existing local area networks today, following the IEEE802.3 protocol requirements. In a conventional ethernet interface circuit, in order to meet requirements of electrical isolation, common mode rejection, electromagnetic interference reduction, long-distance communication, and the like, a network transformer is generally arranged between a PHY and an RJ45, and has two main functions, namely, data transmission, filtering a differential signal sent out by the PHY by using a differential mode coupled coil coupling to enhance the signal, and coupling the differential signal to the other end of a connection network cable through electromagnetic field conversion, so as to isolate different levels between different network devices and prevent the transmission of different voltages through the network cable from damaging the devices. Besides, the network transformer can also play a role in lightning protection for equipment. And the network transformer is a magnetic device which occupies a large space of the equipment.
Disclosure of utility model
In order to solve the problems, the utility model provides an Ethernet interface interconnection circuit, wherein two processor terminals are connected with a capacitor in a coupling-based manner through a differential line of a UTP port of a PHY chip, so that the Ethernet interface interconnection circuit without a network transformer is realized, the cost of devices and the area of a PCB are reduced when the Ethernet is in short-distance communication, and the adaptability of scene application is improved.
The utility model provides an Ethernet interface interconnection circuit, which comprises the following specific technical scheme:
The system comprises a first terminal, a second terminal, a first PHY module, a second PHY module and a coupling unit;
The first terminal is connected with the coupling unit through the first PHY module;
the second terminal is connected with the coupling unit through the second PHY module;
The first PHY module and the second PHY module are connected with the coupling unit in pairs through differential lines of UTP ports.
And establishing interface interaction between the first terminal and the second terminal through the coupling unit, the first PHY module and the second PHY module.
The coupling unit adopts a coupling capacitor.
Further, the first PHY module and the second PHY module employ the same PHY chip.
Further, the MDIP [0] end of the PHY chip of the first PHY module is connected with the MDIP [0] end of the PHY chip of the first PHY module through capacitive coupling.
Further, the MDIN [0] end of the PHY chip of the first PHY module is connected with the MDIN [0] end of the PHY chip of the first PHY module through capacitive coupling.
Further, the MDIP [1] end of the PHY chip of the first PHY module is connected with the MDIP [1] end of the PHY chip of the first PHY module through capacitive coupling.
Further, the MDIN [1] end of the PHY chip of the first PHY module is connected with the MDIN [1] end of the PHY chip of the first PHY module through capacitive coupling.
Further, the MDIP [2] end of the PHY chip of the first PHY module is connected with the MDIP [2] end of the PHY chip of the first PHY module through capacitive coupling.
Further, the MDIN 2 end of the PHY chip of the first PHY module is connected with the MDIN 2 end of the PHY chip of the first PHY module through capacitive coupling.
Further, the MDIP [3] end of the PHY chip of the first PHY module is connected with the MDIP [3] end of the PHY chip of the first PHY module through capacitive coupling.
Further, the MDIN 3 end of the PHY chip of the first PHY module is connected with the MDIN 3 end of the PHY chip of the first PHY module through capacitive coupling.
The beneficial effects of the utility model are as follows:
The structural circuit of the utility model connects the two terminals in a butt joint way through the differential line of the UTP port of the PHY chip and the capacitive coupling way, does not need to design a network transformer and set an RJ45 interface, has simple circuit structure and convenient realization, reduces the number of devices used for realizing the circuit structure, and saves the area of a PCB.
Drawings
Fig. 1 is a schematic diagram of the overall module architecture of the circuit.
Fig. 2 is a schematic diagram of a circuit interface data line connection relationship.
Detailed Description
The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. The components of the embodiments of the present utility model generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
In the description of the embodiments of the present utility model, it should be noted that, the indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship conventionally put in use of the product of the present utility model as understood by those skilled in the art, merely for convenience of describing the present utility model and simplifying the description, and is not indicative or implying that the apparatus or element to be referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present utility model. Furthermore, the terms "first," "second," and the like, are used merely for distinguishing between descriptions and not for understanding as indicating or implying a relative importance.
In the description of the embodiments of the present utility model, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; may be directly connected or indirectly connected through an intermediate medium. The specific meaning of the above terms in the present utility model will be understood in specific cases by those of ordinary skill in the art.
Example 1
The embodiment 1 of the utility model discloses an Ethernet interface interconnection circuit, as shown in fig. 1, the specific architecture is as follows:
The circuit comprises a first terminal, a second terminal, a first PHY module, a second PHY module and a coupling unit;
The first terminal and the second terminal are processor terminals;
The first terminal is connected with the coupling unit through the first PHY module;
the second terminal is connected with the coupling unit through the second PHY module;
Specifically, the first PHY module and the second PHY module are connected with the coupling unit in pairs through differential lines of UTP ports; the common mode voltage is suppressed by transmitting the digital signal through capacitive coupling.
And establishing interface interaction between the first terminal and the second terminal through the coupling unit, the first PHY module and the second PHY module.
The coupling unit adopts a coupling capacitor.
There are two types of UTP port driving of PHY chips, voltage driving and current driving. The current driving needs to connect the tap to a power supply, and the voltage is the driving voltage of the UTP port; the voltage is driven to be grounded through a capacitor.
The connection of the center tap is germane to the PHY for different chips.
In this embodiment, the first PHY module and the second PHY module use the same PHY chip;
Specifically, the UTP port of the PHY chip is of a voltage type; the UTP port voltages of the two connected PHY chips are the same.
Referring to fig. 2, in this embodiment, the MDIP [0] end of the PHY chip of the first PHY module is connected to the MDIP [0] end of the PHY chip of the first PHY module through capacitive coupling;
the MDIN [0] end of the PHY chip of the first PHY module is connected with the MDIN [0] end of the PHY chip of the first PHY module through capacitive coupling.
The MDIP [1] end of the PHY chip of the first PHY module is connected with the MDIP [1] end of the PHY chip of the first PHY module through capacitive coupling;
the MDIN [1] end of the PHY chip of the first PHY module is connected with the MDIN [1] end of the PHY chip of the first PHY module through capacitive coupling.
The MDIP [2] end of the PHY chip of the first PHY module is connected with the MDIP [2] end of the PHY chip of the first PHY module through capacitive coupling;
The MDIN 2 end of the PHY chip of the first PHY module is connected with the MDIN 2 end of the PHY chip of the first PHY module through capacitive coupling.
The MDIP [3] end of the PHY chip of the first PHY module is connected with the MDIP [3] end of the PHY chip of the first PHY module through capacitive coupling;
The MDIN 3 end of the PHY chip of the first PHY module is connected with the MDIN 3 end of the PHY chip of the first PHY module through capacitive coupling.
The foregoing description is only illustrative of the present utility model and is not intended to limit the scope of the utility model, and all equivalent structures or equivalent processes or direct or indirect application in other related technical fields are included in the scope of the present utility model.
Claims (10)
1. An Ethernet interface interconnection circuit is characterized by comprising a first terminal, a second terminal, a first PHY module, a second PHY module and a coupling unit;
The first terminal is connected with the coupling unit through the first PHY module;
the second terminal is connected with the coupling unit through the second PHY module;
The first PHY module and the second PHY module are connected with the coupling unit in pairs through differential lines of UTP ports.
2. The ethernet interface interconnect circuit of claim 1, wherein the first PHY module and the second PHY module employ the same PHY chip.
3. The ethernet interface interconnect circuit of any of claims 1-2 wherein the MDIP [0] terminal of the PHY chip of the first PHY module is connected to the MDIP [0] terminal of the PHY chip of the first PHY module by capacitive coupling.
4. The ethernet interface interconnect circuit of any of claims 1-2 wherein the MDIN [0] terminal of the PHY chip of the first PHY module is coupled to the MDIN [0] terminal of the PHY chip of the first PHY module by capacitive coupling.
5. The ethernet interface interconnect circuit of any of claims 1-2 wherein the MDIP [1] terminal of the PHY chip of the first PHY module is connected to the MDIP [1] terminal of the PHY chip of the first PHY module by capacitive coupling.
6. The ethernet interface interconnect circuit of any of claims 1-2 wherein the MDIN [1] terminal of the PHY chip of the first PHY module is coupled to the MDIN [1] terminal of the PHY chip of the first PHY module by capacitive coupling.
7. The ethernet interface interconnect circuit of any of claims 1-2 wherein the MDIP [2] terminal of the PHY chip of the first PHY module is connected to the MDIP [2] terminal of the PHY chip of the first PHY module by capacitive coupling.
8. The ethernet interface interconnect circuit of any of claims 1-2 wherein the MDIN 2 terminal of the PHY chip of the first PHY module is coupled to the MDIN 2 terminal of the PHY chip of the first PHY module by capacitive coupling.
9. The ethernet interface interconnect circuit of any of claims 1-2 wherein the MDIP [3] terminal of the PHY chip of the first PHY module is coupled to the MDIP [3] terminal of the PHY chip of the first PHY module by capacitive coupling.
10. The ethernet interface interconnect circuit of any of claims 1-2 wherein the MDIN 3 terminal of the PHY chip of the first PHY module is coupled to the MDIN 3 terminal of the PHY chip of the first PHY module by capacitive coupling.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322930389.7U CN221177728U (en) | 2023-10-31 | 2023-10-31 | Ethernet interface interconnection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322930389.7U CN221177728U (en) | 2023-10-31 | 2023-10-31 | Ethernet interface interconnection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN221177728U true CN221177728U (en) | 2024-06-18 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202322930389.7U Active CN221177728U (en) | 2023-10-31 | 2023-10-31 | Ethernet interface interconnection circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN221177728U (en) |
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2023
- 2023-10-31 CN CN202322930389.7U patent/CN221177728U/en active Active
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