CN216700018U - Connection circuit between Ethernet port PHY chips - Google Patents
Connection circuit between Ethernet port PHY chips Download PDFInfo
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- CN216700018U CN216700018U CN202122957034.8U CN202122957034U CN216700018U CN 216700018 U CN216700018 U CN 216700018U CN 202122957034 U CN202122957034 U CN 202122957034U CN 216700018 U CN216700018 U CN 216700018U
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Abstract
The utility model provides a connection circuit between Ethernet port PHY chips, comprising: a first interface circuit of a first PHY chip and a second interface circuit of a second PHY chip; the first interface circuit of the first PHY chip and the second interface circuit of the second PHY chip are electrically connected through a coupling capacitor bank. According to the circuit provided by the scheme of the utility model, the PHY chip interface circuits are connected through the coupling capacitor group, so that the communication mode between the PHY chips between the polar plates is optimized, the polar plate space can be saved, and the design cost is reduced.
Description
Technical Field
The utility model relates to the technical field of PHY chip circuits, in particular to a connecting circuit between Ethernet port PHY chips.
Background
With the advent of the internet of things, everything is interconnected, and the ethernet communication is visible everywhere. People often encounter a connection of two net ports on the same board or a connection of net ports between several circuit boards of a device. The traditional mode for connecting the network ports needs to realize network port connection communication after being exchanged through a network transformer.
However, the network transformer is added in the traditional network port connection mode, so that the cost is extremely high; and often times circuit board space limitations are difficult to implement by putting down two pairs of network transformers.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide a connection circuit between Ethernet port PHY chips, which optimizes the connection mode of PHY chip interface circuits between polar plates, reduces the design cost of the polar plates and realizes the communication between the PHY chips with different voltage types and current types.
To solve the above technical problem, the present invention provides a connection circuit between PHY chips of an ethernet port, including:
a first interface circuit of a first PHY chip and a second interface circuit of a second PHY chip;
the first interface circuit of the first PHY chip and the second interface circuit of the second PHY chip are electrically connected through a coupling capacitor bank.
Optionally, the first interface circuit includes: a transmit differential circuit of the first PHY chip and a receive differential circuit of the first PHY chip;
the second interface circuit includes: a transmit differential circuit of the second PHY chip and a receive differential circuit of the second PHY chip;
the transmitting differential circuit of the first PHY chip is connected with the receiving differential circuit of the second PHY chip through a first coupling capacitor bank;
the receiving differential circuit of the first PHY chip is connected with the transmitting differential circuit of the second PHY chip through a second coupling capacitor bank;
the first coupling capacitor group and the second coupling capacitor group couple signals transmitted by the PHY chip.
Optionally, the differential transmitting circuit of the first PHY chip includes: the circuit comprises a third resistor and a second capacitor electrically connected with the third resistor, wherein the second capacitor is grounded.
Optionally, the differential receiving circuit of the second PHY chip includes: the third capacitor is electrically connected with the fourth resistor and grounded.
Optionally, the differential receiving circuit of the first PHY chip includes: the capacitor comprises a ninth resistor and a sixth capacitor electrically connected with the ninth resistor, and the sixth capacitor is grounded.
Optionally, the differential transmitting circuit of the second PHY chip includes: a tenth resistor, and a seventh capacitor electrically connected to the tenth resistor, the seventh capacitor being connected to ground.
Optionally, the differential transmitting circuit of the first PHY chip further includes: a first resistor and a fifth resistor;
the receive differential circuit of the second PHY chip further comprises: a second resistor and a sixth resistor;
the first coupling capacitance group includes: a first capacitor and a fourth capacitor;
the first end of the first resistor is electrically connected with the first end of the first capacitor, and the first end of the second resistor is electrically connected with the second end of the first capacitor;
a second end of the fifth resistor is electrically connected with a first end of the fourth capacitor, and a second end of the sixth resistor is electrically connected with a second end of the fourth capacitor;
the second end of the first resistor is electrically connected with the first end of the fifth resistor;
the second end of the second resistor is electrically connected with the first end of the sixth resistor.
Optionally, the differential receiving circuit of the first PHY chip further includes: a seventh resistor and an eleventh resistor;
the transmit differential circuit of the second PHY chip further comprises: an eighth resistor and a twelfth resistor;
the second coupling capacitance group includes: a fifth capacitor and an eighth capacitor;
a first end of the seventh resistor is electrically connected with a first end of the fifth capacitor, and a first end of the eighth resistor is electrically connected with a second end of the fifth capacitor;
a first end of the eleventh resistor is electrically connected with a first end of the eighth capacitor, and a first end of the twelfth resistor is electrically connected with a second end of the eighth capacitor;
a second end of the seventh resistor is electrically connected with a first end of the eleventh resistor;
the second end of the eighth resistor is electrically connected with the first end of the twelfth resistor.
The scheme of the utility model at least comprises the following beneficial effects:
according to the scheme, the first interface circuit of the first PHY chip and the second interface circuit of the second PHY chip are directly and electrically connected through the coupling capacitor group, so that the communication between the first PHY chip and the second PHY chip is realized, meanwhile, the connection mode between chip circuits is optimized, the design space of a polar plate is saved, and the design cost is reduced.
Drawings
FIG. 1 is a schematic diagram of a connection circuit between PHY chips according to the present invention;
fig. 2 is a schematic diagram of a connection circuit between PHY chips of an ethernet port according to the present invention.
The reference numbers illustrate: 1. a first interface circuit; 2. a second interface circuit; 3. a transmit differential circuit of the first PHY chip; 4. a receive differential circuit of the second PHY chip; 5. a receive differential circuit of the first PHY chip; 6. a transmit differential circuit of the second PHY chip; r1, a first resistor; r2, a second resistor;
r3, third resistor; r4, fourth resistor; r5, fifth resistor; r6, sixth resistor; r7, seventh resistor; r8, eighth resistor; r9, ninth resistor; r10, tenth resistor; r11, eleventh resistor; r12, twelfth resistor; c1, a first capacitance; c2, a second capacitor; c3, a third capacitance; c4, a fourth capacitance; c5, a fifth capacitance; c6, a sixth capacitor; c7, a seventh capacitance; c8, eighth capacitance.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
As shown in fig. 1 and fig. 2, an embodiment of the present invention provides a connection circuit between PHY chips of an ethernet port, including: a first interface circuit 1 of a first PHY chip and a second interface circuit 2 of a second PHY chip; the first interface circuit 1 of the first PHY chip and the second interface circuit 2 of the second PHY chip are electrically connected through a coupling capacitor bank.
In the embodiment, the interface circuits of the first PHY chip and the second PHY chip are connected through the coupling capacitor group, so that the communication between the first PHY chip and the second PHY chip is realized, and compared with the existing scheme, a network transformer and related circuits are omitted, the space of a circuit board is saved, and the design cost of the circuit board is reduced; the capacitors in the coupling capacitor bank are preferably 0.1UF capacitors; the first PHY chip and the second PHY chip may be the same type of PHY chip or different types of PHY chips.
In an optional embodiment of the present invention, the first interface circuit 1 includes: a transmission differential circuit 3 of the first PHY chip and a reception differential circuit 5 of the first PHY chip; the second interface circuit 2 includes: a transmission differential circuit 6 of the second PHY chip and a reception differential circuit 4 of the second PHY chip; the transmitting differential circuit 3 of the first PHY chip is connected with the receiving differential circuit 4 of the second PHY chip through a first coupling capacitor bank; the receiving differential circuit 5 of the first PHY chip is connected to the transmitting differential circuit 6 of the second PHY chip via a second coupling capacitor bank; the first coupling capacitor group and the second coupling capacitor group couple signals transmitted by the PHY chip.
In this embodiment, the first PHY chip transmits a signal to the second PHY chip through the transmission differential circuit 3 of the first PHY chip, and receives a signal transmitted by the second PHY chip through the reception differential circuit 5 of the first PHY chip; the second PHY chip transmits signals to the first PHY chip through the transmitting differential circuit 6 of the second PHY chip, and receives the signals transmitted by the first PHY chip through the receiving differential circuit 4 of the second PHY chip; the first coupling capacitor group and the second coupling capacitor group couple electric signals sent between chips to realize communication between the chips.
Further, the transmission differential circuit 3 of the first PHY chip includes: a third resistor R3, and a second capacitor C2 electrically connected to the third resistor R3, wherein the second capacitor C2 is grounded.
Further, the receiving differential circuit 4 of the second PHY chip includes: a fourth resistor R4, and a third capacitor C3 electrically connected to the fourth resistor R4, wherein the third capacitor C3 is grounded.
Further, the receiving differential circuit 5 of the first PHY chip includes: a ninth resistor R9, and a sixth capacitor C6 electrically connected to the ninth resistor R9, the sixth capacitor being grounded C6.
Further, the transmission differential circuit 6 of the second PHY chip includes: a tenth resistor R10, and a seventh capacitor C7 electrically connected to the tenth resistor R10, wherein the seventh capacitor C7 is connected to ground.
In this embodiment, the third resistor R3, the fourth resistor R4, the ninth resistor R9, and the tenth resistor R10 are arranged to implement current-mode PHY inter-chip communication, that is, the current-mode PHY inter-chip communication is: when the current mode PHY chips are disposed at both ends of the first and second sets of coupling capacitors, the third resistor R3 is soldered to the ninth resistor R9, and the fourth resistor R4 is soldered to the tenth resistor R10;
the second capacitor C2, the third capacitor C3, the sixth capacitor C6 and the seventh capacitor C7 are arranged to implement voltage type inter-chip communication, that is: when the two ends of the first group of coupling capacitors and the second group of coupling capacitors are both voltage type PHY chips, the second capacitor C2 is welded with the sixth capacitor C6, and the third capacitor C3 is welded with the seventh capacitor C7;
of course, the third resistor R3, the fourth resistor R4, the ninth resistor R9, the tenth resistor R10, the second capacitor C2, the third capacitor C3, the sixth capacitor C6, and the seventh capacitor C7 may also be arranged to implement different types of PHY inter-chip communication, that is to say: when the first ends of the first and second sets of coupling capacitors are voltage-type PHY chips and the second ends of the first and second sets of coupling capacitors are current-type PHY chips, the second capacitor C2 is soldered to the sixth capacitor C6 and the fourth resistor R4 is soldered to the tenth resistor R10; when the first ends of the first and second sets of coupling capacitors are current-type PHY chips and the second ends of the first and second sets of coupling capacitors are voltage-type PHY chips, the third resistor R3 is soldered to the ninth resistor R9, and the third capacitor C3 is soldered to the seventh capacitor C7.
Further, the differential transmitting circuit of the first PHY chip further includes: a first resistor R1 and a fifth resistor R5; the receive differential circuit of the second PHY chip further comprises: a second resistor R2 and a sixth resistor R6; the first coupling capacitance group includes: a first capacitor C1 and a fourth capacitor C4; a first end of the first resistor R1 is electrically connected with a first end of the first capacitor C1, and a first end of the second resistor R2 is electrically connected with a second end of the first capacitor C1; a second end of the fifth resistor R5 is electrically connected with a first end of the fourth capacitor C4, and a second end of the sixth resistor R6 is electrically connected with a second end of the fourth capacitor C4; a second end of the first resistor R1 is electrically connected with a first end of the fifth resistor R5; the second end of the second resistor R2 is electrically connected with the first end of the sixth resistor R6.
Further, the differential receiving circuit of the first PHY chip further includes: a seventh resistor R7 and an eleventh resistor R11; the transmit differential circuit of the second PHY chip further comprises: an eighth resistor R8 and a twelfth resistor R12; the second coupling capacitance group includes: a fifth capacitor C5 and an eighth capacitor C8; a first end of the seventh resistor R7 is electrically connected with a first end of the fifth capacitor C5, and a first end of the eighth resistor R8 is electrically connected with a second end of the fifth capacitor C5; a first end of the eleventh resistor R11 is electrically connected with a first end of the eighth capacitor C8, and a first end of the twelfth resistor R12 is electrically connected with a second end of the eighth capacitor C8; a second end of the seventh resistor R7 is electrically connected with a first end of the eleventh resistor R11; the second end of the eighth resistor R8 is electrically connected with the first end of the twelfth resistor R12.
In this embodiment, the first resistor R1, the second resistor R2, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8, the eleventh resistor R11, and the twelfth resistor R12 are provided, so that damage to the circuit board due to excessive current in the circuit is avoided, and the quality of communication between PHY chips is ensured.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the utility model as defined in the appended claims.
Claims (8)
1. A circuit for connecting ethernet ports PHY chips, comprising:
a first interface circuit (1) of a first PHY chip and a second interface circuit (2) of a second PHY chip;
the first interface circuit (1) of the first PHY chip and the second interface circuit (2) of the second PHY chip are electrically connected through a coupling capacitor bank.
2. The connection circuit between ethernet ports PHY chips according to claim 1, wherein said first interface circuit (1) comprises: a transmission differential circuit (3) of the first PHY chip and a reception differential circuit (5) of the first PHY chip;
the second interface circuit (2) comprises: a transmission differential circuit (6) of the second PHY chip and a reception differential circuit (4) of the second PHY chip;
the transmitting differential circuit (3) of the first PHY chip is connected with the receiving differential circuit (4) of the second PHY chip through a first coupling capacitor group;
the receiving differential circuit (5) of the first PHY chip is connected with the transmitting differential circuit (6) of the second PHY chip through a second coupling capacitor bank;
the first coupling capacitor group and the second coupling capacitor group isolate signals transmitted by the PHY chip.
3. The Ethernet port PHY chip connection circuit according to claim 2, wherein the first PHY chip transmit differential circuit (3) comprises: a third resistor (R3), and a second capacitor (C2) electrically connected to the third resistor (R3), the second capacitor (C2) being connected to ground.
4. The Ethernet port PHY chip connection circuit according to claim 3, wherein the second PHY chip receive differential circuit (4) comprises: a fourth resistor (R4), and a third capacitor (C3) electrically connected to the fourth resistor (R4), the third capacitor (C3) being connected to ground.
5. The Ethernet port PHY chip connection circuit according to claim 2, wherein the first PHY chip receive differential circuit (5) comprises: a ninth resistor (R9), and a sixth capacitor (C6) electrically connected to the ninth resistor (R9), the sixth capacitor being connected to ground (C6).
6. The Ethernet port PHY chip connection circuit according to claim 5, wherein the transmission differencing circuit (6) of the second PHY chip comprises: a tenth resistor (R10), and a seventh capacitor (C7) electrically connected to the tenth resistor (R10), the seventh capacitor (C7) being connected to ground.
7. The Ethernet port PHY chip connection circuit according to claim 2, wherein the first PHY chip transmit differential circuit (3) further comprises: a first resistor (R1), a fifth resistor (R5); the receive differential circuit (4) of the second PHY chip further comprises: a second resistor (R2), a sixth resistor (R6);
the first coupling capacitance group includes: a first capacitance (C1) and a fourth capacitance (C4);
a first terminal of the first resistor (R1) is electrically connected to a first terminal of the first capacitor (C1), and a first terminal of the second resistor (R2) is electrically connected to a second terminal of the first capacitor (C1);
a second end of the fifth resistor (R5) is electrically connected with a first end of the fourth capacitor (C4), and a second end of the sixth resistor (R6) is electrically connected with a second end of the fourth capacitor (C4);
a second end of the first resistor (R1) is electrically connected with a first end of the fifth resistor (R5);
a second end of the second resistor (R2) is electrically connected with a first end of the sixth resistor (R6).
8. The ethernet port PHY-chip connection circuit of claim 2, wherein the receive differential circuit (5) of the first PHY-chip further comprises: a seventh resistor (R7), an eleventh resistor (R11); the transmit differential circuit (6) of the second PHY chip further comprises: an eighth resistor (R8), a twelfth resistor (R12);
the second coupling capacitance group includes: a fifth capacitance (C5) and an eighth capacitance (C8);
a first end of the seventh resistor (R7) is electrically connected with a first end of the fifth capacitor (C5), and a first end of the eighth resistor (R8) is electrically connected with a second end of the fifth capacitor (C5);
a first end of the eleventh resistor (R11) is electrically connected with a first end of the eighth capacitor (C8), and a first end of the twelfth resistor (R12) is electrically connected with a second end of the eighth capacitor (C8);
a second end of the seventh resistor (R7) is electrically connected with a first end of the eleventh resistor (R11);
a second end of the eighth resistor (R8) is electrically connected with a first end of the twelfth resistor (R12).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122957034.8U CN216700018U (en) | 2021-11-29 | 2021-11-29 | Connection circuit between Ethernet port PHY chips |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122957034.8U CN216700018U (en) | 2021-11-29 | 2021-11-29 | Connection circuit between Ethernet port PHY chips |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216700018U true CN216700018U (en) | 2022-06-07 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202122957034.8U Active CN216700018U (en) | 2021-11-29 | 2021-11-29 | Connection circuit between Ethernet port PHY chips |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN216700018U (en) |
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2021
- 2021-11-29 CN CN202122957034.8U patent/CN216700018U/en active Active
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