CN221127254U

CN221127254U - Chip packaging structure

Info

Publication number: CN221127254U
Application number: CN202322653283.7U
Authority: CN
Inventors: 王蔚; 谢国梁
Original assignee: China Wafer Level CSP Co Ltd
Current assignee: China Wafer Level CSP Co Ltd
Filing date: 2023-09-28
Publication date: 2024-06-11
Anticipated expiration: 2033-09-28

Abstract

The utility model discloses a chip packaging structure which comprises a chip and a silicon substrate. The chip is provided with a first surface, and a functional area is formed on the first surface of the chip; the silicon substrate is provided with a first surface, a first insulating layer of a polymer material is formed on the first surface of the silicon substrate, the first surface of the silicon substrate is pressed on the first surface of the chip, a cavity is formed between the first surface of the chip and the first surface of the chip, and the functional area is located in the cavity. The chip packaging structure can reduce the packaging cost of the FBAR (film bulk acoustic resonator) chip and improve the packaging performance of the FBAR (film bulk acoustic resonator) chip.

Description

Chip packaging structure

Technical Field

The present utility model relates to the field of chip packaging technology, and in particular, to a chip packaging structure.

Background

At present, the main current international packaging scheme of an FBAR (film bulk acoustic resonator) chip is that the substrate material of the FBAR chip adopts high-resistance silicon, a Through Silicon Via (TSV) is formed on the high-resistance silicon, and metal-Au is used as a through hole filling material, a welding bulge material and a sealing material bonded with a high-resistance silicon cover plate.

It will be appreciated that very good hermetic packages can be produced by face-to-face bonding with high resistance silicon cover plates. But has a problem in that high-resistance silicon is relatively expensive; the 3D interconnection process for making Au filled through holes on the high-resistance silicon is complex and has high cost; the use of Jin Jinjian for the high-resistance silicon cover plate and high-resistance silicon substrate is also relatively expensive. Therefore, the cost of implementing the small chip, high density, high hermetic insulation level packaging scheme of the FBAR chip according to the above scheme is high. Currently, the industry is working to study low cost, high reliability schemes instead of such TSV schemes.

The information disclosed in this background section is only for enhancement of understanding of the general background of the utility model and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.

Disclosure of utility model

The utility model aims to provide a chip packaging structure which can reduce the packaging cost of an FBAR (film bulk acoustic resonator) chip and improve the packaging performance of the FBAR (film bulk acoustic resonator) chip.

In order to achieve the above object, an embodiment of the present utility model provides a chip package structure including a chip and a silicon substrate. The chip is provided with a first surface, and a functional area is formed on the first surface of the chip; the silicon substrate is provided with a first surface, a first insulating layer of a polymer material is formed on the first surface of the silicon substrate, the first surface of the silicon substrate is pressed on the first surface of the chip, a cavity is formed between the first surface of the chip and the first surface of the chip, and the functional area is located in the cavity.

In one or more embodiments of the utility model, the chip is a thin film bulk acoustic resonator.

In one or more embodiments of the present utility model, the silicon substrate has a resistivity of 1 Ω·cm to 3 Ω·cm.

In one or more embodiments of the present utility model, a dam is formed on the first insulating layer, the silicon substrate is bonded to the first surface of the chip through the dam, and the dam is disposed around the functional region.

In one or more embodiments of the utility model, the cofferdam material is a polymeric material.

In one or more embodiments of the utility model, the dam is integrally formed with the first insulating layer.

In one or more embodiments of the utility model, a bonding pad coupled to the functional region is formed on the first surface of the chip; the chip is provided with a second surface which is arranged opposite to the first surface, and a conductive structure which is electrically connected with the welding pad is formed on the second surface.

In one or more embodiments of the present utility model, a through hole is formed on the second surface of the chip, the through hole exposing the pad; the conductive structure includes: the second insulating layer is formed on the side wall of the through hole and extends to the second surface of the chip; the metal layer is formed on the surface of the second insulating layer and is electrically connected with the welding pad; the solder mask layer is formed on the surface of the metal layer and covers the metal layer, and is provided with an opening exposing the metal layer; and a solder bump filling the opening and exposed outside the surface of the solder resist layer.

The embodiment of the utility model provides a chip packaging method, which comprises the following steps: providing a chip, wherein the chip is provided with a first surface and a second surface which are oppositely arranged, and a functional area and a welding pad coupled with the functional area are formed on the first surface; providing a silicon substrate, and forming a first insulating layer of a polymer material on a first surface of the silicon substrate; and pressing the first surface of the silicon substrate on the first surface of the chip, forming a cavity between the first surface of the silicon substrate and the first surface of the chip, and positioning the functional area in the cavity.

In one or more embodiments of the present utility model, before the first surface of the silicon substrate is pressed onto the first surface of the chip, the chip packaging method further includes: forming a bank on the first insulating layer on the first surface of the silicon substrate; the silicon substrate is bonded with the first surface of the chip through the cofferdam, and the cofferdam is arranged around the functional area.

In one or more embodiments of the present utility model, the chip packaging method further includes: forming a through hole on the second surface of the chip, wherein the through hole exposes the welding pad; and forming a conductive structure electrically connected with the welding pad in the through hole and on the second surface of the chip.

Compared with the prior art, the chip packaging structure and the chip packaging method adopt the silicon substrate of common monocrystalline silicon, and the insulating layer of the polymer material is formed on the silicon substrate to replace the high-resistance silicon cover plate, so that the bonding with the chip is realized, the packaging cost is reduced, and meanwhile, the performance of the chip packaging structure is more stable and reliable.

Drawings

FIG. 1 is a process flow diagram of a method of chip packaging according to an embodiment of the utility model;

FIGS. 2 a-2 e are schematic views illustrating steps of a chip packaging method according to an embodiment of the present utility model;

Detailed Description

The following detailed description of embodiments of the utility model is, therefore, to be taken in conjunction with the accompanying drawings, and it is to be understood that the scope of the utility model is not limited to the specific embodiments.

Throughout the specification and claims, unless explicitly stated otherwise, the term "comprise" or variations thereof such as "comprises" or "comprising", etc. will be understood to include the stated element or component without excluding other elements or components.

As described in the background art, the current mainstream packaging scheme of the FBAR (film bulk acoustic resonator) chip in the world adopts a face-to-face bonding mode of the high-resistance silicon cover plate and the chip, so that a very good airtight package can be generated. But has a problem in that high-resistance silicon is relatively expensive; the 3D interconnection process for making Au filled through holes on the high-resistance silicon is complex and has high cost; the use of Jin Jinjian for the high-resistance silicon cover plate and high-resistance silicon substrate is also relatively expensive. Therefore, the cost of implementing the small chip, high density, high hermetic insulation level packaging scheme of the FBAR chip according to the above scheme is high.

It will be appreciated that the functional area of the surface of an FBAR (film bulk acoustic resonator) chip has a film layer a which receives RF signals during operation of the chip. If the high-resistance silicon cover plate and the high-resistance silicon substrate of the chip are replaced by optical silicon chips, the upper and lower resistances of the whole structure are insufficient, so that the high-resistance silicon is generally adopted.

In order to solve the technical problems, the utility model provides a chip packaging structure and a chip packaging method, wherein a common monocrystalline silicon substrate is adopted, and an insulating layer made of polymer material is formed on the silicon substrate to replace a high-resistance silicon cover plate, so that the bonding between the silicon substrate and a chip is realized, the packaging cost is reduced, and meanwhile, the performance of the chip packaging structure is more stable and reliable.

The chip package structure of the present utility model will be described in detail below with reference to the accompanying drawings.

As shown in fig. 2e, the chip package structure according to an embodiment of the utility model includes a chip 10 and a silicon substrate 20 bonded to a surface of the chip 10. Wherein, a first insulating layer 21 of polymer material is formed on a surface of the silicon substrate 20 near the chip 10.

The chip 10 is preferably an FBAR (film bulk acoustic resonator) chip. The chip 10 has a first surface 10a and a second surface 10b disposed opposite to each other. The first surface 10a of the chip 10 is formed with a functional region 11, and a pad 12 coupled to the functional region 11. A thin film layer a for receiving RF signals is provided in the functional region 11. A second surface 10b of the chip 10 is formed with conductive structures electrically connected to the pads 12.

Illustratively, the second surface 10b of the chip 10 is formed with a through hole 13 extending toward the first surface 10a, and the through hole 13 exposes the bonding pad 12 of the first surface 10 a. The conductive structures extend from within the through holes 13 onto the second surface 10b of the chip 10. The conductive structure includes a second insulating layer 31, a metal layer 32, a solder resist layer 33, and a solder bump 34. The second insulating layer 31 is formed on the second surface 10b of the chip 10 and the sidewall surface of the through hole 13, and openings exposing the pads 12 are formed on the second insulating layer 31 corresponding to the pads 12. In an embodiment, the material of the second insulating layer 31 may be silicon oxide, silicon nitride, silicon oxynitride, or insulating resin. The metal layer 32 is formed on the surface of the second insulating layer 31 and electrically connects to the bonding pad 12 through the opening. The solder mask layer 33 is formed on the surface of the metal layer 32 and is disposed to cover the metal layer 32, and the solder mask layer 33 has an opening exposing the metal layer 32. In one embodiment, the material of the solder mask layer 33 is an insulating dielectric material such as silicon oxide, silicon nitride, etc., for protecting the metal layer 32. The solder mask layer 33 has a solder bump 34 disposed in the opening, and the solder bump 34 is electrically connected to the metal layer 32 and protrudes beyond the surface of the solder mask layer 33. The bonding bumps 34 may be solder balls, metal pillars, or other connection structures, and the material may be copper, aluminum, gold, tin, or lead, or other metal materials.

The silicon substrate 20 is a silicon material substrate of ordinary single crystal silicon, and the resistivity of the silicon substrate 20 is 1 Ω·cm to 3 Ω·cm. The silicon substrate 20 has a first surface 20a and a second surface 20b disposed opposite to each other. A first insulating layer 21 of a polymeric material is formed on the first surface 20a of the silicon substrate 20. The first insulating layer 21 of polymeric material serves to block the exposure of electricity, which can be significantly less costly than high-resistance silicon covers, while more effectively blocking the exposure of electricity. The first insulating layer 21 has a bank 22 formed thereon, which is also a polymer material. In one embodiment, the first insulating layer 21 and the bank 22 may be integrally formed. In another embodiment, the first insulating layer 21 and the bank 22 may also be molded stepwise. The first surface 20a of the silicon substrate 20 is bonded to the first surface 10a of the chip 10 through the dam 22, and a cavity B is formed between the first surface 20a of the silicon substrate 20 and the first surface 10a of the chip 10. The dam 22 is disposed around the functional region 11 of the chip 10 and the functional region 11 of the chip 10 is located within the cavity B.

As shown in fig. 1, in an embodiment, the present utility model provides a chip packaging method of the above chip packaging structure, including: s1, providing a chip, wherein the chip is provided with a first surface and a second surface which are oppositely arranged, and a functional area and a bonding pad coupled with the functional area are formed on the first surface; s2, providing a silicon substrate, and forming a first insulating layer of a polymer material on a first surface of the silicon substrate; s3, forming a cofferdam on the first insulating layer of the first surface of the silicon substrate; s4, pressing the first surface of the silicon substrate on the first surface of the chip, and forming a cavity between the first surface of the silicon substrate and the first surface of the chip through the cofferdam, wherein the functional area is positioned in the cavity; s5, forming a through hole on the second surface of the chip, wherein the through hole exposes the welding pad; and s6, forming a conductive structure for electrically connecting the bonding pads in the through holes and on the second surface of the chip.

It is understood that the above-described packaging of the chip package structure may also be achieved by a wafer level packaging method. Namely, a wafer-level silicon substrate is provided, a first insulating layer of a polymer material is formed on a first surface of the wafer-level silicon substrate, and a plurality of banks are formed on the first insulating layer. The wafer is provided and comprises a plurality of chips, cutting channels are formed between the adjacent chips, each chip is provided with a first surface and a second surface which are oppositely arranged, and a functional area and a bonding pad coupled with the functional area are formed on the first surface. The first surface of the wafer-level silicon substrate is pressed on the surface of the wafer provided with the functional area, and a plurality of cavities are formed between the first surface of the silicon substrate and the surface of the wafer through the cofferdam, and each cavity accommodates one functional area. And forming a through hole on the other surface of the wafer, wherein the through hole exposes the bonding pad. Conductive structures electrically connecting the pads are formed within the vias and on the surface of the wafer. Cutting along the cutting path to obtain the chip packaging structure.

Fig. 2a to 2e are schematic views illustrating a process step of a chip packaging method according to an embodiment of the application.

As shown in fig. 2a, a chip 10 is provided. The chip 10 is preferably an FBAR (film bulk acoustic resonator) chip. The chip 10 has a first surface 10a and a second surface 10b disposed opposite to each other. The first surface 10a of the chip 10 is formed with a functional region 11, and a pad 12 coupled to the functional region 11. A thin film layer a for receiving RF signals is provided in the functional region 11.

As shown in fig. 2b and 2c, a silicon substrate 20 is provided. The silicon substrate 20 has a first surface 20a and a second surface 20b disposed opposite to each other. A first insulating layer 21 of a polymeric material is formed on the first surface 20a of the silicon substrate 20. The first insulating layer 21 of polymeric material serves to block the exposure of electricity, which can be significantly less costly than high-resistance silicon covers, while more effectively blocking the exposure of electricity. The thickness of the first insulating layer 21 is not constant, and can be adjusted as needed. A bank 22 of polymeric material is formed on the first insulating layer 21. In one embodiment, the first insulating layer 21 and the bank 22 may be integrally formed. In another embodiment, the first insulating layer 21 and the bank 22 may also be molded stepwise.

As shown in fig. 2d, the first surface 10a of the chip 10 and the first surface 20a of the silicon substrate 20 are aligned and pressed, the dam 22 is located between the chip 10 and the silicon substrate 20 to form a cavity B therebetween, and the functional area 11 is located in the cavity B formed by surrounding the dam 22.

As shown in fig. 2e, a through hole 13 extending toward the first surface 10a is formed in the second surface 10b of the chip 10, and the bottom of the through hole 13 exposes the pad 12.

It will be appreciated that after the through hole 13 is formed, a portion of the substrate of the chip 10 (i.e. the portion of the second surface 10b corresponding to the bonding pad 12) is removed, where one way is to form the second surface 10b into a stepped surface, so that the thickness of the substrate of the first portion (the portion corresponding to the bonding pad 12) of the package structure is smaller than that of the substrate of the second portion (the rest portion), that is, the thickness of the substrate at the periphery of the through hole 13 is greater than that of the substrate at the inner side of the through hole 13, so that the depth of the through hole 13 is correspondingly reduced, and further, the opening of the through hole 13 is prevented from being blocked by the insulating material or metal in the subsequent step, so that voids (void) or seams (sea) can be avoided, the reliability of the product is improved, and mass production is facilitated. In addition, as part of the matrix is removed, the overall dimension of the packaging structure is reduced, the signal delay of the chip can be reduced, the power consumption can be reduced, and the performance of the semiconductor device can be improved. In one embodiment of the present utility model, a portion of the substrate may be removed by mechanical cutting to ensure that the thickness of the substrate around the periphery of the through hole 13 is reduced.

As shown in fig. 2e, a second insulating layer 31 is formed on the second surface 10b of the chip 10 by vapor deposition technology, and the surface covered by the second insulating layer 31 is the second surface 10b of the chip 10 and the sidewall of the through hole 13. Next, a metal layer 32 is formed on the second surface 10b of the chip 10 at least for electrically connecting the chip 10, and the metal layer 32 is formed by a sequence of processes including metal deposition, photolithography, copper plating, stripping, and copper/titanium etching. A solder resist layer 33 is formed on the second surface 10b of the chip 10 and in the through hole 13, the solder resist layer 33 covering the metal layer 32. The solder mask layer 33 is formed on the surface of the metal layer 32 by adopting a spraying process and baked, so that the subsequent solder ball feeding process is convenient, and the effects of solder mask and chip protection are achieved.

After the above process is completed, the solder mask 33 of the formed package structure may be baked first, and then a portion of the solder mask between adjacent chips may be removed, or a portion of the solder mask 33 between adjacent chips may be removed first, and then the solder mask may be baked. Next, openings are made in the solder resist layer 33, the openings being used to expose a portion of the metal layer 32. Finally, a solder bump 34 is formed at the aperture.

The foregoing descriptions of specific exemplary embodiments of the present utility model are presented for purposes of illustration and description. It is not intended to limit the utility model to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain the specific principles of the utility model and its practical application to thereby enable one skilled in the art to make and utilize the utility model in various exemplary embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the utility model be defined by the claims and their equivalents.

Claims

1. A chip package structure, comprising:

A chip having a first surface, the first surface of the chip having a functional region formed thereon;

The silicon substrate is provided with a first surface, a first insulating layer of a polymer material is formed on the first surface of the silicon substrate, the first surface of the silicon substrate is pressed on the first surface of the chip, a cavity is formed between the first surface of the chip and the first surface of the chip, and the functional area is located in the cavity.

2. The chip package structure of claim 1, wherein the chip is a thin film bulk acoustic resonator.

3. The chip package structure of claim 1, wherein the silicon substrate has a resistivity of 1 Ω -cm-3 Ω -cm.

4. The chip package structure of claim 1, wherein the first insulating layer has a dam formed thereon, the silicon substrate is bonded to the first surface of the chip through the dam, and the dam is disposed around the functional region.

5. The chip package structure of claim 4, wherein the dam is made of a polymer material.

6. The chip package structure of claim 4, wherein the dam is integrally formed with the first insulating layer.

7. The chip package structure of claim 1, wherein a first surface of the chip has pads formed thereon that are coupled to the functional regions;

the chip is provided with a second surface which is arranged opposite to the first surface, and a conductive structure which is electrically connected with the welding pad is formed on the second surface.

8. The chip package structure of claim 7, wherein a through hole is formed on the second surface of the chip, the through hole exposing the bonding pad;

the conductive structure includes:

The second insulating layer is formed on the side wall of the through hole and extends to the second surface of the chip;

The metal layer is formed on the surface of the second insulating layer and is electrically connected with the welding pad;

the solder mask layer is formed on the surface of the metal layer and covers the metal layer, and is provided with an opening exposing the metal layer;

And a solder bump filling the opening and exposed outside the surface of the solder resist layer.