CN221103325U - Novel broadband fine stepping low-phase noise frequency synthesizer - Google Patents

Novel broadband fine stepping low-phase noise frequency synthesizer Download PDF

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CN221103325U
CN221103325U CN202323124109.XU CN202323124109U CN221103325U CN 221103325 U CN221103325 U CN 221103325U CN 202323124109 U CN202323124109 U CN 202323124109U CN 221103325 U CN221103325 U CN 221103325U
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pll
power divider
mixer
signal circuit
output end
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梁国林
高栋
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Chengdu Jiujin Technology Co ltd
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Chengdu Jiujin Technology Co ltd
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Abstract

The utility model relates to a novel broadband fine stepping low-phase noise frequency synthesizer, which comprises a crystal oscillator, NLTL, a first power divider, a first signal circuit, a second power divider, a first PLL, a first mixer and a second PLL; the crystal oscillator outputs a signal to NLTL, the NLTL is connected with a first power divider, and the first power divider is sequentially connected with a first signal circuit and a second signal circuit; the first signal circuit is connected with the second power divider, the second power divider is respectively connected with the first PLL and the second PLL, the first PLL and the second PLL are connected with the first mixer, the second signal circuit is connected with the first PLL, and the first mixer is connected with the second PLL. The utility model adopts NLTL frequency multiplication with better performance to obtain the broadband equidistant reference signal RF1 in one step, and adopts the integrated PLL chip, thereby having higher integration level and low VCO tuning zero degree of the integrated PLL and simplifying the scheme to the maximum extent.

Description

Novel broadband fine stepping low-phase noise frequency synthesizer
Technical Field
The utility model relates to the technical field of communication, in particular to a novel broadband fine stepping low-phase noise frequency synthesizer.
Background
The frequency synthesizer is an important component in electronic technology, space technology and communication technology, is widely applied to the fields of communication, radars, electronic countermeasure and instrument lamps as a time base signal and a local oscillator, and is required to have the characteristics of broadband, low phase noise and fine stepping at the same time in order to cope with the current increasingly complex electronic environment.
In the prior art, the crystal oscillator is passed for 4 times to a bit frequency, power is divided into two paths, one path is used as a reference, the other path is used for frequency doubling and power division, one path is mixed with a signal generated by the DDS, and the mixed signal is used as a reference of a PLL1 for a VCO 1; the other path of the frequency multiplication is mixed with the signal of the VCO1 to enter the PLL1, the VCO1 can obtain a better signal after phase discrimination, the signal output by the VCO1 is subjected to power division, one path of the frequency multiplication is mixed with the signal output by the VCO2 to obtain the IF1, and the other path of the frequency multiplication is subjected to frequency division and then is subjected to power division; one path after frequency division is mixed with the IF1 to obtain the IF2 to enter the PLL2, the other path after frequency division is directly entered into the PLL2, and the broadband signal with low phase noise is obtained through phase discrimination. In the prior art, the crystal oscillator is huge in volume and difficult to control after multiple frequency multiplication filtering, the VCO2 is a high-frequency broadband VCO, the tuning sensitivity is high, the linearity is poor, the design requirement on a loop filter is high, the loop stability is poor, and the cost of the scheme is high and difficult to miniaturize.
Disclosure of utility model
The utility model aims to overcome the defects of the prior art, provides a novel broadband fine stepping low-phase noise frequency synthesizer and solves the problems existing in the prior art.
The aim of the utility model is achieved by the following technical scheme: a novel broadband fine stepping low-phase noise frequency synthesizer comprises a crystal oscillator, NLTL, a first power divider, a first signal circuit, a second power divider, a first PLL, a first mixer and a second PLL;
The crystal oscillator outputs signals to NLTL, the output end of NLTL is connected with the input end of the first power divider, and the output end of the first power divider is respectively connected with the first signal circuit and the second signal circuit; the output end of the first signal circuit is connected with the input end of the second power divider, the output end of the second power divider is respectively connected with the input ends of the first PLL and the second PLL, the output ends of the first PLL and the second PLL are connected with the input end of the first mixer, the second signal circuit is connected with the first PLL, the output end of the first mixer is connected with the second PLL, and the second PLL outputs signals.
The first signal circuit comprises a first filter, a third power divider, a DDS and a second mixer;
The output end of the first filter is connected with the input end of the third power divider, the output end of the third power divider is respectively connected with the input ends of the DDS and the second mixer, and the output end of the DDS is connected with the input end of the second mixer.
The output end of the first power divider is connected with the input end of the first filter, and the output end of the second mixer is connected with the input end of the second power divider.
The first signal circuit comprises a second filter and a third mixer; the output end of the first power divider is connected with the input end of the second filter, the output end of the second filter is connected with the input end of the third mixer, and the third mixer is connected with the first PLL.
The utility model has the following advantages: a novel broadband fine stepping low-phase noise frequency synthesizer adopts NLTL frequency multiplication with better performance to obtain a broadband equidistant reference signal RF1 in one step, thereby simplifying the existing complex frequency multiplication filtering scheme; meanwhile, an integrated PLL (PLL 1 and PLL 2) chip is adopted, the integration level is higher, the VCO tuning zero degree of the integrated PLL is low, the linearity is good, the loop is more stable, and the cost is lower; the scheme is simplified to the greatest extent, the portable product is enabled to be applied to the portable product due to smaller volume, and the cost is lower.
Drawings
FIG. 1 is a schematic diagram of a prior art circuit schematic;
fig. 2 is a schematic circuit diagram of the present utility model.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present utility model more apparent, the technical solutions of the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model, and it is apparent that the described embodiments are only some embodiments of the present utility model, not all embodiments. The components of the embodiments of the present utility model generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Accordingly, the following detailed description of the embodiments of the utility model, as presented in conjunction with the accompanying drawings, is not intended to limit the scope of the utility model as claimed, but is merely representative of selected embodiments of the utility model. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present utility model. The utility model is further described below with reference to the accompanying drawings.
As shown in fig. 1, the present utility model specifically relates to a novel wideband fine stepping low phase noise frequency synthesizer, which comprises a crystal oscillator, an NLTL (nonlinear transmission line), a first power divider, a first signal circuit, a second power divider, a PPL (phase locked loop) 1, a first mixer and a PPL2;
The crystal oscillator outputs signals to NLTL, the output end of NLTL is connected with the input end of the first power divider, and the output end of the first power divider is respectively connected with the first signal circuit and the second signal circuit; the output end of the first signal circuit is connected with the input end of the second power divider, the output ends of the second power divider are respectively connected with the input ends of PPL1 and PPL2, the output ends of PPL1 and PPL2 are connected with the input end of the first mixer, the second signal circuit is connected with PPL1, the output end of the first mixer is connected with PPL2, and the PPL2 outputs signals.
Further, the first signal circuit includes a first filter, a third power divider, a DDS (direct digital synthesizer) and a second mixer; the output end of the first filter is connected with the input end of the third power divider, the output end of the third power divider is respectively connected with the input ends of the DDS and the second mixer, and the output end of the DDS is connected with the input end of the second mixer.
The output end of the first power divider is connected with the input end of the first filter, and the output end of the second mixer is connected with the input end of the second power divider.
Further, the first signal circuit includes a second filter and a third mixer; the output end of the first power divider is connected with the input end of the second filter, the output end of the second filter is connected with the input end of the third mixer, and the third mixer is connected with the PPL 1.
The working process of the utility model is as follows: the crystal oscillator generates CLK1, the CLK1 generates a broadband equidistant signal RF1 through NLTL frequency multiplication, the signal RF1 obtains a required frequency point RF2 through a first filter, the RF2 is used as a reference for the DDS, the DDS generates CLK2 and mixes with the RF2 to obtain CLK3, and the CLK3 is used as a reference for the PLL1 and the PLL2 after power division.
The signal RF1 is further processed by a second filter to obtain a required signal RF3, and the signal RF3 is mixed with the signal RF4 output by the PLL1 to obtain an IF1, and the IF1 is input into the PLL1 for phase discrimination. And mixing the RF4 with an output signal RF5 of the PLL2 to obtain an IF2, inputting the IF2 into the PLL2 for phase discrimination, and outputting an RF6 by the PLL2, wherein the RF6 is in a multiple relation with the RF 5.
Wherein DDS, PLL1 and PLL2 need to be externally connected with FPGA to perform register control, CLK 3/n=if1, CLK 3/m=if2, n and m each represent a multiple, if1+if2=rf1; PLL1 and PLL2 are phase discrimination ratios of 1 to 1, so that phase noise is not deteriorated. At this time, the integrated phase noise depends on the noise floor of the phase detectors of RF3 and PLL1 and PLL2, RF3 is directly multiplied by CLK1, the phase noise is subjected to frequency multiplication degradation calculation, RF 3/clk1=n, and the phase noise degradation value is 20×lgn; the phase detector in the PLL1 and the phase detector in the PLL2 are the same phase detector, and the normalized noise floor is-236 dBc/Hz. The phase noise is not deteriorated when the phase discrimination ratio of 1 to 1 is adopted, so the phase noise of RF3 is mainly determined; the phase noise of RF3 is mainly dependent on the phase noise of CLK1 and the additional phase noise due to frequency multiplication. According to the working process, a low-phase noise signal of 2-20 GHz can be obtained.
The foregoing is merely a preferred embodiment of the utility model, and it is to be understood that the utility model is not limited to the form disclosed herein but is not to be construed as excluding other embodiments, but is capable of numerous other combinations, modifications and adaptations, and of being modified within the scope of the inventive concept described herein, by the foregoing teachings or by the skilled person or knowledge of the relevant art. And that modifications and variations which do not depart from the spirit and scope of the utility model are intended to be within the scope of the appended claims.

Claims (4)

1. A novel broadband fine stepping low-phase noise frequency synthesizer is characterized in that: the power divider comprises a crystal oscillator, NLTL, a first power divider, a first signal circuit, a second power divider, a first PLL, a first mixer and a second PLL;
The crystal oscillator outputs signals to NLTL, the output end of NLTL is connected with the input end of the first power divider, and the output end of the first power divider is respectively connected with the first signal circuit and the second signal circuit; the output end of the first signal circuit is connected with the input end of the second power divider, the output end of the second power divider is respectively connected with the input ends of the first PLL and the second PLL, the output ends of the first PLL and the second PLL are connected with the input end of the first mixer, the second signal circuit is connected with the first PLL, the output end of the first mixer is connected with the second PLL, and the second PLL outputs signals.
2. The novel wideband fine stepping low phase noise frequency synthesizer of claim 1, wherein: the first signal circuit comprises a first filter, a third power divider, a DDS and a second mixer;
The output end of the first filter is connected with the input end of the third power divider, the output end of the third power divider is respectively connected with the input ends of the DDS and the second mixer, and the output end of the DDS is connected with the input end of the second mixer.
3. A novel wideband fine stepping low phase noise frequency synthesizer as claimed in claim 2, wherein: the output end of the first power divider is connected with the input end of the first filter, and the output end of the second mixer is connected with the input end of the second power divider.
4. The novel wideband fine stepping low phase noise frequency synthesizer of claim 1, wherein: the first signal circuit comprises a second filter and a third mixer; the output end of the first power divider is connected with the input end of the second filter, the output end of the second filter is connected with the input end of the third mixer, and the third mixer is connected with the first PLL.
CN202323124109.XU 2023-11-17 2023-11-17 Novel broadband fine stepping low-phase noise frequency synthesizer Active CN221103325U (en)

Priority Applications (1)

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CN202323124109.XU CN221103325U (en) 2023-11-17 2023-11-17 Novel broadband fine stepping low-phase noise frequency synthesizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202323124109.XU CN221103325U (en) 2023-11-17 2023-11-17 Novel broadband fine stepping low-phase noise frequency synthesizer

Publications (1)

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CN221103325U true CN221103325U (en) 2024-06-07

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