CN221043675U - Display panel and display device - Google Patents

Abstract

The utility model discloses a display panel and a display device, the display panel includes: a substrate; a cathode layer located at one side of the substrate, the cathode layer including a first cathode and a second cathode insulated from each other; the first cathode is positioned in the display area and the non-display area, the second cathode is positioned in the under-screen camera area and the non-display area, and the vertical projection of the first cathode on the substrate is not overlapped with the vertical projection of the second cathode on the substrate; the first cathode wire and the second cathode wire are mutually insulated, the first cathode wire is connected with the part of the first cathode, which is positioned in the non-display area, the second cathode wire is connected with the part of the second cathode, which is positioned in the non-display area, the first cathode wire is used for transmitting a first cathode voltage to the first cathode, and the second cathode wire is used for transmitting a second cathode voltage to the second cathode. The utility model can improve the consistency of the brightness of the under-screen shooting area and the display area.

Description

Display panel and display device

Technical Field

The present utility model relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

The camera can be installed on the existing display equipment to meet shooting requirements, in order to avoid sacrificing the display area, one mode is to set up the transparent display area on the display panel, and set up the under-screen camera below the position corresponding to the transparent display area, so that the area can take into account two functions of shooting and displaying, and user experience is improved.

However, in a panel with an under-screen image capturing function, in order to increase the transmittance of an under-screen image capturing area, the RGB aperture ratio of the image capturing area is designed to be smaller than that of the display area, so that the brightness of the under-screen image capturing area and the brightness of the display area are different under the condition that the cathode voltage ELVDD and the cathode voltage ELVSS of the same power supply are across.

Disclosure of utility model

The utility model provides a display panel and a display device, which can improve the consistency of brightness of an under-screen shooting area and a display area.

In a first aspect, the present utility model provides a display panel including a display area, a non-display area disposed around the display area, and an under-screen camera area; the display panel further includes: a substrate; a cathode layer located at one side of the substrate, the cathode layer including a first cathode and a second cathode insulated from each other; the first cathode is positioned in the display area and the non-display area, the second cathode is positioned in the under-screen camera area and the non-display area, and the vertical projection of the first cathode on the substrate is not overlapped with the vertical projection of the second cathode on the substrate; the first cathode wire and the second cathode wire are mutually insulated, the first cathode wire is connected with the part of the first cathode, which is positioned in the non-display area, the second cathode wire is connected with the part of the second cathode, which is positioned in the non-display area, the first cathode wire is used for transmitting a first cathode voltage to the first cathode, and the second cathode wire is used for transmitting a second cathode voltage to the second cathode.

Optionally, the absolute value of the second cathode voltage is greater than the absolute value of the first cathode voltage.

Optionally, the first cathode trace and the second cathode trace are both located in the non-display area and both extend around the display area, and the second cathode trace is located on a side of the first cathode trace near the display area.

Optionally, the display panel further includes a plurality of first connection portions, a plurality of second connection portions, a plurality of first signal terminals, and a plurality of second signal terminals; the first end of each first connecting part is connected with different positions of the first cathode wire, and the second end of each first connecting part is connected with a first signal end; the first end of each second connecting part is connected with different positions of the second cathode wire, and the second end of each second connecting part is connected with a second signal end; the second connecting portion and at least part of the first connecting portion are located on the same side of the non-display area.

Optionally, the first cathode trace and the second cathode trace are both located in a non-display area, and the first cathode trace extends around the display area; the second cathode wiring extends along the first direction and is positioned at one side of the first cathode wiring, which is close to the under-screen camera shooting area.

Optionally, the display panel further includes a plurality of first connection portions, a plurality of second connection portions, a plurality of first signal terminals, and a plurality of second signal terminals; the first end of each first connecting part is connected with different positions of the first cathode wire, and the second end of each first connecting part is connected with a first signal end; the first end of each second connecting part is connected with different positions of the second cathode wire, and the second end of each second connecting part is connected with a second signal end; the second connecting portion and at least part of the first connecting portion are located on different sides of the non-display area.

Optionally, the second connection portion extends along a second direction, and a vertical projection of the second connection portion on the substrate overlaps with a vertical projection of the first cathode trace on the substrate; the second connecting part comprises a first sub-section, a second sub-section and a connecting bridge, the first end of the first sub-section is connected with the second cathode wiring, the second end of the first sub-section is connected with the first end of the second sub-section through the connecting bridge, and the second end of the second sub-section is connected with the second signal end; the first direction and the second direction are mutually intersected and are perpendicular to the thickness direction of the display panel; the connecting bridge is arranged in different layers with the first subsection and the second subsection, and the first cathode wiring is arranged in the same layer with the first subsection and the second subsection.

Optionally, the display panel includes a first conductive layer and a second conductive layer, the first conductive layer is located on one side of the substrate, and the second conductive layer is located on one side of the first conductive layer away from the substrate; the first cathode wire and the second cathode wire are both positioned on the first conductive layer, and a first insulating layer is arranged between the first cathode wire and the second cathode wire; the first cathode and the second cathode are both positioned on the second conductive layer, and a second insulating layer is arranged between the first cathode and the second cathode.

Optionally, the display panel further includes a power module located in the non-display area, and the power module includes a first power unit and a second power unit; the first power supply unit is used for providing a first cathode voltage for the first cathode wiring; the second power supply unit is used for providing a second cathode voltage for the second cathode wiring.

In a second aspect, the present utility model provides a display device, including a display panel provided in any of the above embodiments.

In the display panel of the embodiment of the utility model, the cathodes of the under-screen image pickup area and the display area are respectively and independently arranged, when the panel displays pictures, the cathodes of the under-screen image pickup area and the display area are connected with different cathode signal lines under the condition that the power supply anode voltage ELVDD is fixed, the difference between the power supply anode voltage ELVDD applied to the pixels and the first cathode voltage ELVSS1 can be controlled by adjusting the voltage on the first cathode line, and the difference between the power supply anode voltage ELVDD applied to the pixels and the second cathode voltage ELVSS2 can be controlled by adjusting the voltage on the second cathode line so as to match the aperture ratio of the under-screen image pickup area and the display area, thereby realizing the consistent brightness display of the under-screen image pickup area and the display area.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the utility model or to delineate the scope of the utility model. Other features of the present utility model will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present utility model, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic top view of a display panel according to an embodiment of the present utility model;

FIG. 2 is a schematic cross-sectional view of the display panel of FIG. 1 along the section line F-F';

FIG. 3 is a schematic diagram of a first pixel circuit of a 7T1C architecture according to an embodiment of the present utility model;

FIG. 4 is a schematic diagram of a second pixel circuit of a 2T1C architecture according to an embodiment of the present utility model;

FIG. 5 is a schematic top view of another display panel according to an embodiment of the present utility model;

FIG. 6 is a schematic cross-sectional view of the display panel of FIGS. 1 and 5 along section line A-A';

FIG. 7 is a schematic cross-sectional view of the display panel of FIGS. 1 and 5 along section line B-B';

FIG. 8 is a schematic top view of another display panel according to an embodiment of the present utility model;

FIG. 9 is a schematic top view of another display panel according to an embodiment of the present utility model;

FIG. 10 is a schematic cross-sectional view of the display panel of FIGS. 8 and 9 along section line C-C';

FIG. 11 is a schematic cross-sectional view of the display panel of FIGS. 8 and 9 along the section line D-D';

FIG. 12 is a schematic cross-sectional view of the display panel of FIGS. 8 and 9 in the direction E-E' in the region 100;

FIG. 13 is a schematic top view of another display panel according to an embodiment of the present utility model;

fig. 14 is a schematic structural diagram of a display device according to an embodiment of the present utility model.

Detailed Description

In order that those skilled in the art will better understand the present utility model, a technical solution in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present utility model, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present utility model without making any inventive effort, shall fall within the scope of the present utility model.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present utility model and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the utility model described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.

The embodiment of the utility model is described by taking an Organic LIGHT EMITTING Diode (OLED) display panel as an example, but the utility model is also applicable to other display panels including liquid crystal display panels.

Fig. 1 is a schematic top view of a display panel according to an embodiment of the present utility model, and fig. 2 is a schematic cross-sectional structure of the display panel shown in fig. 1 along a cross-sectional line F-F', where, as shown in fig. 1 and fig. 2, an array substrate according to an embodiment of the present utility model may include a display area 101, a non-display area 102 disposed around the display area 101, and an under-screen image capturing area 103; the display panel further includes:

A substrate 10;

a cathode layer on one side of the substrate 10, the cathode layer including a first cathode 201 and a second cathode 202 insulated from each other; the first cathode is positioned in the display area 101 and the non-display area 102, the second cathode is positioned in the under-screen camera area 103 and the non-display area 102, and the vertical projection of the first cathode 201 on the substrate 10 is not overlapped with the vertical projection of the second cathode 202 on the substrate 10;

The first cathode trace 110 and the second cathode trace 120 are insulated from each other, the first cathode trace 110 is connected to a portion of the first cathode 201 located in the non-display area 102, the second cathode trace 120 is connected to a portion of the second cathode 202 located in the non-display area 102, the first cathode trace 110 is used for transmitting a first cathode voltage ELVSS1 to the first cathode 201, and the second cathode trace 120 is used for transmitting a second cathode voltage ELVSS2 to the second cathode 202.

The substrate 10 may provide buffering, protection, or support for the display panel, among other functions. The substrate 10 may be a flexible substrate, and the material of the flexible substrate may be Polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), or the like, or may be a mixture of the above materials. The substrate 10 may be a hard substrate made of a material such as glass. The material of the cathode layer may be a metal material such as aluminum (Al), gold (Au), and silver.

The under-screen camera shooting area 103 comprises a light transmission area 11 and a transition area 12, and the light transmission area 11 is opposite to the under-screen camera. The light-transmitting area 11 is disposed opposite to the under-screen camera, which means that the light-transmitting area 11 overlaps with the area of the under-screen camera projected on the back surface of the display panel.

According to an embodiment of the utility model, referring to fig. 1, the transition zone 12 is arranged at the outer edge of the light transmission zone 11, i.e. it means that the transition zone 12 is arranged outside the light transmission zone 11, or that the transition zone 12 is arranged at the periphery of the light transmission zone 11. In addition, the specific location of the light-transmitting area 11 is not particularly limited, and those skilled in the art can flexibly select the light-transmitting area according to the actual design requirement of the functional area under the screen, for example, the light-transmitting area 11 may be the center of the display panel, or may be a corner of the display panel, or may be located in a position where the display panel is close to the border and centered as shown in fig. 1.

Moreover, the specific shape of the light-transmitting area 11 is not particularly limited, and a person skilled in the art can flexibly select the specific shape according to practical situations such as the specific shape of the under-screen camera, for example, the shape of the light-transmitting area 11 includes, but is not limited to, a circle, an ellipse, a quadrilateral, a pentagon, a hexagon, and other polygons or irregular patterns.

Referring to fig. 2, according to an embodiment of the present utility model, the display panel further includes: a plurality of first pixel units and a plurality of second pixel units, the plurality of first pixel units being arranged in the display area 101, the plurality of second pixel units being arranged in the transition area 12. The first pixel unit comprises a first sub-pixel and a first pixel circuit for driving the first sub-pixel, the second pixel unit comprises a second sub-pixel and a second pixel circuit for driving the second sub-pixel, and the aperture opening ratio of the first sub-pixel is larger than that of the second sub-pixel.

Referring to fig. 2, the display panel includes a first active layer 211, a first gate electrode 212, a first source electrode 213, and a first drain electrode 214, the first active layer 211, the first gate electrode 212, the first source electrode 213, and the first drain electrode 214 constitute a first transistor 21, and the first transistor 21 and other transistors, capacitors, and the like (not shown in the drawing) constitute a first pixel circuit. Wherein the first active layer 211 is disposed on a side of the substrate 10, the gate insulating layer 61 covers the first active layer 211, the first gate 212 is disposed on a side of the gate insulating layer 61 away from the substrate 10, the interlayer dielectric layer 62 is disposed on a side of the gate insulating layer 61 away from the substrate 10 and covers the first gate 212, the first source 213 and the first drain 214 are disposed on a side of the interlayer dielectric layer 62 away from the substrate 10, wherein the first source 213 and the first drain 214 are electrically connected to the first active layer 211 through vias penetrating the gate insulating layer 61 and the interlayer dielectric layer 62.

The first light emitting unit corresponding to the first sub-pixel includes a first anode layer 14, a first OLED functional layer 15 and a first cathode layer 201.

Referring to fig. 2, the display panel further includes a second active layer 221, a second gate electrode 222, and a second source/drain electrode layer 223, wherein the second active layer 221, the second gate electrode 222, and the second source/drain electrode layer 223 form a second transistor 22, and the second transistor 22, and other transistors, capacitors, and the like form a second pixel circuit. The second active layer 221 may be disposed on the same layer as the first active layer 211, the gate insulating layer 61 covers the second active layer 221, the second gate 222 is disposed on a side of the gate insulating layer 61 away from the substrate, the interlayer dielectric layer 62 is disposed on a side of the gate insulating layer 61 away from the substrate and covers the second gate 222, and the source drain electrode layer 223 is disposed on a side of the interlayer dielectric layer 62 away from the substrate 10, wherein the source drain electrode layer 223 is electrically connected to the second active layer 221 through a via hole penetrating through the gate insulating layer 61 and the interlayer dielectric layer 62.

The second light emitting unit corresponding to the second sub-pixel includes a second anode layer 16, a second OLED functional layer 17 and a second cathode layer 202. Referring to fig. 2, the display panel further includes a planarization layer 63, where the planarization layer 63 is disposed on a side of the interlayer dielectric layer 62 away from the substrate 10; the display panel further comprises a pixel defining layer 64, the pixel defining layer 64 being arranged on a side of the planarization layer 63 remote from the substrate 10 and defining a plurality of openings, wherein all light emitting devices in the display panel are arranged in the openings.

Fig. 3 is a schematic diagram of a first pixel circuit of a 7T1C architecture according to an embodiment of the present utility model. 7T1C means that each first sub-pixel is driven by a first pixel circuit formed of 7 thin film transistors and 1 capacitor. Referring to fig. 3, optionally, the first pixel circuit includes a driving module, a storage module, a data writing module, a compensation module, a light emission control module, and an initialization module; the driving module comprises a first thin film transistor T1, and the first thin film transistor T1 is the driving thin film transistor in the pixel circuit; the storage module comprises a storage capacitor C; the data writing module comprises a second thin film transistor T2, and the compensation module comprises a third thin film transistor T3; the light-emitting control module comprises a fifth thin film transistor T5 and a sixth thin film transistor T6; the initialization module includes a fourth thin film transistor T4 and a seventh thin film transistor T7.

The control terminal of the first thin film transistor T1 is connected to the second terminal of the storage capacitor C, the second terminal of the third thin film transistor T3, and the second terminal of the fourth thin film transistor T4. The first terminal of the first thin film transistor T1 is connected to the second terminal of the second thin film transistor T2. The second end of the first thin film transistor T1 is connected to the first end of the third thin film transistor T3 and the first end of the sixth thin film transistor T6. The first end of the first thin film transistor T1 is an input end of the driving module, the second end of the first thin film transistor T1 is an output end of the driving module, the first end of the first thin film transistor T1 is a source electrode of the driving thin film transistor, the second end of the first thin film transistor T1 is a drain electrode of the driving thin film transistor, and the control end of the first thin film transistor T1 is a gate electrode of the driving thin film transistor.

The control terminal of the second thin film transistor T2 is connected to the second scan signal terminal S2. The first end of the second thin film transistor T2 is connected to the data signal line VDATA. The second terminal of the second thin film transistor T2 is connected to the first terminal of the first thin film transistor T1.

The control terminal of the third thin film transistor T3 is connected to the second scan signal terminal S2. The first terminal of the third thin film transistor T3 is connected to the first terminal of the sixth thin film transistor T6. The second end of the third thin film transistor T3 is connected to the second end of the storage capacitor C and the second end of the fourth thin film transistor T4.

The control terminal of the fourth thin film transistor T4 is connected to the first scan signal terminal S1. The first terminal of the fourth thin film transistor T4 is connected to the first reference voltage signal terminal VREF 1. The second terminal of the fourth thin film transistor T4 is connected to the second terminal of the storage capacitor C.

The control terminal of the fifth thin film transistor T5 is connected to the emission control signal terminal EM. The first end of the fifth thin film transistor T5 is connected to the first end of the storage capacitor C, and the second end of the fifth thin film transistor T5 is connected to the first end of the first thin film transistor T1.

The control terminal of the sixth thin film transistor T6 is connected to the emission control signal terminal EM. The first terminal of the sixth thin film transistor T6 is connected to the second terminal of the first thin film transistor T1. A second terminal of the sixth thin film transistor T6 is connected to the anode of the light emitting element.

The control terminal of the seventh thin film transistor T7 is connected to the third scan signal terminal S3. The first terminal of the seventh thin film transistor T7 is connected to the second reference voltage signal terminal VREF 2. The second terminal of the seventh thin film transistor T7 is connected to the anode of the first light emitting element D1. The second terminal of the seventh thin film transistor T7 is the first output terminal of the initialization module.

The first terminal of the storage capacitor C is connected to a first power supply voltage input terminal for receiving a power supply positive voltage ELVDD, which is typically generated and supplied by a power supply generator (not shown) of the display device. The cathode of the first light emitting element D1 is connected to the second power supply voltage input terminal. The second power supply voltage input terminal is for receiving a first cathode voltage ELVSS1, which is typically generated and supplied by a power generator (not shown) of the display device.

Fig. 4 is a schematic diagram of a second pixel circuit of a 2T1C architecture according to an embodiment of the present utility model. 2T1C means that each of the second sub-pixels is driven by a second pixel circuit formed of 2 thin film transistors and 1 capacitor.

Referring to fig. 4, the second pixel circuit includes a second light emitting element D2, a first thin film transistor T1, a second thin film transistor T2, and a capacitor Cs. The source of the first thin film transistor T1 and the first terminal of the capacitor Cs are electrically connected to the point a, and the power supply positive voltage ELVDD (which is generally generated and provided by a power generator (not shown) of the display device), the gate of the first thin film transistor T1, the drain of the second thin film transistor T2 and the second terminal of the capacitor Cs are electrically connected to the point b, the source of the second thin film transistor T2 is electrically connected to the DATA voltage DATA, the gate is electrically connected to the point c, and the scan signal scan.

The first to seventh thin film transistors T1 to T7 may also have a first terminal as a drain electrode, a second terminal as a source electrode, and the first and second light emitting elements D1 and D2 as organic light emitting diodes.

The number of active switches of the second sub-pixel driven by the second pixel circuit is less than the number of active switches of the first sub-pixel driven by the first pixel circuit. Since the display area 101 of the OLED display panel adopts the organic light emitting diode, the light emitting luminance thereof is attenuated with the lapse of time, the OLED display panel generally requires a plurality of thin film transistors for driving, and the organic light emitting diode is compensated for luminance. To form the light-transmitting region in the transition region 12, the thin film transistor of the transition region 12 may be omitted, and the space of the light-transmitting region may be increased by simplifying the circuit architecture.

According to the embodiment of the utility model, the specific structures of the first pixel circuit and the second pixel circuit are not particularly required, and a person skilled in the art can flexibly select the first pixel circuit and the second pixel circuit according to actual situations, so long as the number of corresponding active switches of the second pixel circuit is ensured to be smaller than that of the first pixel circuit. The first pixel circuit and the second pixel circuit may also take other circuit architecture forms such as 6T1C, 5T2C, and the like.

In the display panel of the embodiment of the utility model, the cathodes of the under-screen image pickup area and the display area are respectively and independently arranged, when the panel displays pictures, the cathodes of the under-screen image pickup area and the display area are connected with different cathode signal lines under the condition that the power supply anode voltage ELVDD is fixed, the difference between the power supply anode voltage ELVDD applied to the pixels and the first cathode voltage ELVSS1 can be controlled by adjusting the voltage on the first cathode line, and the difference between the power supply anode voltage ELVDD applied to the pixels and the second cathode voltage ELVSS2 can be controlled by adjusting the voltage on the second cathode line so as to match the aperture ratio of the under-screen image pickup area and the display area, thereby realizing the consistent brightness display of the under-screen image pickup area and the display area.

With continued reference to fig. 1, the absolute value of the second cathode voltage is greater than the absolute value of the first cathode voltage, i.e., |elvss2| > |elvss1|.

Since the smaller the aperture ratio is, under the same brightness, the larger the voltage across between the power supply positive electrode voltage ELVDD and the cathode voltage ELVSS is; the larger the aperture ratio is, the smaller the voltage across the power supply positive electrode voltage ELVDD and the cathode voltage ELVSS is under the same brightness condition; therefore, in the case where the power supply positive electrode voltage ELVDD is fixed, by setting the absolute value of the second cathode voltage to be larger than the absolute value of the first cathode voltage, that is, increasing the voltage across the power supply positive electrode voltage ELVDD and the second cathode voltage ELVSS2, decreasing the voltage across the power supply positive electrode voltage ELVDD and the first cathode voltage ELVSS1 to match the aperture ratio of the under-screen image pickup area and the display area, the brightness uniformity of the display area 101 and the under-screen image pickup area 103 is achieved.

Optionally, the first cathode trace 110 and the second cathode trace 120 are both located in the non-display area and each extend around the display area, and the second cathode trace 120 is located on a side of the first cathode trace 110 near the display area 101.

The first cathode trace 110 and the second cathode trace 120 may be disposed on the same layer, and may be manufactured by the same process when the first cathode trace 110 and the second cathode trace 120 are manufactured, without requiring an additional manufacturing process or a mask process, so as to ensure that the manufacturing process of the first cathode trace 110 and the second cathode trace 120 is simple.

Fig. 5 is a schematic top view of another display panel according to an embodiment of the present utility model, fig. 6 is a schematic cross-sectional structure of the display panel shown in fig. 5 along a section line A-A ', fig. 7 is a schematic cross-sectional structure of the display panel shown in fig. 5 along a section line B-B', and, in combination with fig. 5, fig. 6 and fig. 7, the display panel further includes a plurality of first connection portions 41, a plurality of second connection portions 42, a plurality of first signal terminals S1 and a plurality of second signal terminals S2.

The first end of each first connecting portion 41 is connected to different positions of the first cathode trace 110, and the second end of each first connecting portion 41 is connected to a first signal end S1; the first end of each second connection portion 42 is connected to different positions of the second cathode trace 120, and the second end of each second connection portion 42 is connected to a second signal end S2; the second connection portion 42 is located on the same side of the non-display area 102 as at least part of the first connection portion 41. By connecting the first end of each first connection portion 41 to a different position of the first cathode trace 110 and connecting the first end of each second connection portion 42 to a different position of the second cathode trace 120, IR Drop problems caused by the first cathode trace 110 and the second cathode trace 120 can be reduced. That is, the pattern of the display area reduces the voltage drop of the first cathode voltage signal and the second cathode voltage signal on the transmission line by the multi-terminal common driving method, so that the driving current in the display area is more balanced, and the uniformity of the display brightness of the display area 12 can be improved, so as to improve the display effect of the display panel.

Referring to fig. 6, the display panel includes a first conductive layer 20 and a second conductive layer 30, the first conductive layer 20 being located at one side of the substrate 10, the second conductive layer 30 being located at one side of the first conductive layer 20 remote from the substrate 10; the first cathode wire 110 and the second cathode wire 120 are both positioned on the first conductive layer 20, and a first insulating layer 40 is arranged between the first cathode wire 110 and the second cathode wire 120; the first cathode 201 and the second cathode 202 are both positioned on the second conductive layer 30, and the second insulating layer 50 is disposed between the first cathode 201 and the second cathode 202.

Fig. 8 is a schematic top view of another display panel according to an embodiment of the present utility model, fig. 9 is a schematic top view of another display panel according to an embodiment of the present utility model, fig. 10 is a schematic cross-sectional structure of the display panel shown in fig. 8 and 9 along a section line C-C ', fig. 11 is a schematic cross-sectional structure of the display panel shown in fig. 8 and 9 along a section line D-D', and fig. 8, 9, 10 and 11 are combined, optionally, the first cathode trace 110 and the second cathode trace 120 are both located in the non-display area 102, and the first cathode trace 110 extends around the display area 101; the second cathode trace 120 extends along the first direction X, and is located on a side of the first cathode trace 110 near the under-screen image capturing area 103.

The display panel further includes a plurality of first connection parts 41, a plurality of second connection parts 42, a plurality of first signal terminals S1 and a plurality of second signal terminals S2; the first end of each first connecting portion 41 is connected to different positions of the first cathode trace 110, and the second end of each first connecting portion 41 is connected to a first signal end S1; the first end of each second connection portion 42 is connected to different positions of the second cathode trace 120, and the second end of each second connection portion 42 is connected to a second signal end S2; the second connection portion 42 is located at a different side of the non-display area 102 than at least part of the first connection portion 41.

Referring to fig. 10, the display panel includes a first conductive layer 20 and a second conductive layer 30, the first conductive layer 20 being located at one side of the substrate 10, the second conductive layer 30 being located at one side of the first conductive layer 20 remote from the substrate 10; the first cathode wire 110 and the second cathode wire 120 are both positioned on the first conductive layer 20, and a first insulating layer 40 is arranged between the first cathode wire 110 and the second cathode wire 120; the first cathode 201 and the second cathode 202 are both positioned on the second conductive layer 30, and the second insulating layer 50 is disposed between the first cathode 201 and the second cathode 202.

Fig. 12 is a schematic cross-sectional structure of the display panel shown in fig. 8 and 9 along the direction E-E' in the region 100, and in combination with fig. 8 and 12, the second connection portion 42 extends along the second direction Y, and a vertical projection of the second connection portion 42 on the substrate 10 overlaps a vertical projection of the first cathode trace 110 on the substrate 10; the second connection portion 42 includes a first sub-segment 420, a second sub-segment 421 and a connection bridge 422, wherein a first end of the first sub-segment 420 is connected to the second cathode trace 120, a second end of the first sub-segment 420 is connected to a first end of the second sub-segment 421 through the connection bridge 422, and a second end of the second sub-segment 421 is connected to the second signal end S2; the first direction X and the second direction Y are mutually intersected and are perpendicular to the thickness direction of the display panel; the connection bridge 422 is arranged in different layers from the first subsection 420 and the second subsection 421, and the first cathode wire 110 is arranged in the same layer as the first subsection 420 and the second subsection 421.

Fig. 13 is a schematic top view of another display panel according to an embodiment of the present utility model, as shown in fig. 13, where the display panel further includes a power module 60 located in the non-display area 102, and the power module 60 includes a first power unit 601 and a second power unit 602.

The first power supply unit 601 is configured to provide a first cathode voltage to the first cathode trace 110; the second power supply unit 602 is configured to provide a second cathode voltage to the second cathode trace 120.

Based on the same inventive concept, an embodiment of the present utility model further provides a display device, and fig. 14 is a schematic structural diagram of the display device provided in the embodiment of the present utility model, and referring to fig. 14, the display device may include a display panel provided in any embodiment of the present utility model. The display device may be a mobile phone as shown in fig. 14, or may be a computer, a television, an intelligent wearable display device, etc., which is not particularly limited in the embodiment of the present utility model.

The above embodiments do not limit the scope of the present utility model. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present utility model should be included in the scope of the present utility model.

Claims (10)

1. A display panel, comprising a display area, a non-display area arranged around the display area and an under-screen camera area; the display panel further includes:

A substrate;

A cathode layer located at one side of the substrate, the cathode layer including a first cathode and a second cathode insulated from each other; the first cathode is positioned in the display area and the non-display area, the second cathode is positioned in the under-screen camera area and the non-display area, and the vertical projection of the first cathode on the substrate is not overlapped with the vertical projection of the second cathode on the substrate;

The first cathode wire and the second cathode wire are mutually insulated, the first cathode wire is connected with the part of the first cathode, which is positioned in the non-display area, the second cathode wire is connected with the part of the second cathode, which is positioned in the non-display area, the first cathode wire is used for transmitting a first cathode voltage to the first cathode, and the second cathode wire is used for transmitting a second cathode voltage to the second cathode.

2. The display panel of claim 1, wherein an absolute value of the second cathode voltage is greater than an absolute value of the first cathode voltage.

3. The display panel of claim 1, wherein the first cathode trace and the second cathode trace are both located in the non-display region and both extend around the display region, the second cathode trace being located on a side of the first cathode trace adjacent the display region.

4. The display panel of claim 3, further comprising a plurality of first connection portions, a plurality of second connection portions, a plurality of first signal terminals, and a plurality of second signal terminals;

The first end of each first connecting part is connected with different positions of the first cathode wire, and the second end of each first connecting part is connected with one first signal end;

The first end of each second connecting part is connected with different positions of the second cathode wire, and the second end of each second connecting part is connected with one second signal end;

The second connection part and at least part of the first connection part are positioned on the same side of the non-display area.

5. The display panel of claim 1, wherein the first cathode trace and the second cathode trace are both located in the non-display region, the first cathode trace extending around the display region;

The second cathode wiring extends along the first direction and is positioned at one side of the first cathode wiring, which is close to the under-screen camera shooting area.

6. The display panel of claim 5, further comprising a plurality of first connection portions, a plurality of second connection portions, a plurality of first signal terminals, and a plurality of second signal terminals;

The first end of each first connecting part is connected with different positions of the first cathode wire, and the second end of each first connecting part is connected with one first signal end;

The first end of each second connecting part is connected with different positions of the second cathode wire, and the second end of each second connecting part is connected with one second signal end;

the second connection part and at least part of the first connection part are positioned on different sides of the non-display area.

7. The display panel of claim 6, wherein the second connection extends in a second direction, a perpendicular projection of the second connection onto the substrate overlapping a perpendicular projection of the first cathode trace onto the substrate;

The second connecting part comprises a first sub-section, a second sub-section and a connecting bridge, wherein the first end of the first sub-section is connected with the second cathode wiring, the second end of the first sub-section is connected with the first end of the second sub-section through the connecting bridge, and the second end of the second sub-section is connected with the second signal end; the first direction and the second direction are mutually intersected and are perpendicular to the thickness direction of the display panel;

The connecting bridge is arranged in different layers with the first subsection and the second subsection, and the first cathode wiring is arranged in the same layer with the first subsection and the second subsection.

8. The display panel of claim 4 or 6, wherein the display panel comprises a first conductive layer and a second conductive layer, the first conductive layer being located on a side of the substrate, the second conductive layer being located on a side of the first conductive layer remote from the substrate;

The first cathode wire and the second cathode wire are both positioned on the first conductive layer, and a first insulating layer is arranged between the first cathode wire and the second cathode wire;

The first cathode and the second cathode are both positioned on the second conductive layer, and a second insulating layer is arranged between the first cathode and the second cathode.

9. The display panel of claim 1, further comprising a power module located in the non-display area, the power module comprising a first power unit and a second power unit;

The first power supply unit is used for providing the first cathode voltage for the first cathode wire;

The second power supply unit is used for providing the second cathode voltage for the second cathode wiring.

10. A display device comprising the display panel of any one of claims 1-9.