CN221043359U

CN221043359U - PCB jointed board

Info

Publication number: CN221043359U
Application number: CN202322705757.8U
Authority: CN
Inventors: 李立勇; 马银芳
Original assignee: Wuxi Meike Microelectronics Technology Co ltd
Current assignee: Wuxi Meike Microelectronics Technology Co ltd
Priority date: 2023-10-10
Filing date: 2023-10-10
Publication date: 2024-05-28
Anticipated expiration: 2033-10-10

Abstract

The application discloses a PCB jointed board, and relates to the technical field of PCB boards. The filling layer used for solving the problem that the filling layer arranged in the nonfunctional area in the prior art can cause uneven thermal expansion of the PCB jointed board, thereby causing the warpage of the PCB jointed board and further influencing the quality of the PCB jointed board. The PCB panel includes at least one sub panel including a functional area and a non-functional area surrounding the functional area: the functional area comprises a plurality of sub-PCB boards which are connected with each other, the non-functional area is provided with a filling layer, and a plurality of stress release holes are formed in the filling layer along the thickness direction of the filling layer. According to the application, the stress release holes are formed in the filling layer, so that the stress of the filling layer can be released by the stress release holes, the thermal expansion of the PCB jointed board is more uniform, the warpage phenomenon of the PCB jointed board is not easy to occur, and the quality of the PCB jointed board can be improved.

Description

PCB jointed board

Technical Field

The application relates to the technical field of PCB boards, in particular to a PCB jointed board.

Background

A silicon-based OLED (Organic LIGHT EMITTING Diode) micro-display is a micro-display based on a silicon-based substrate and Organic Light Emitting Diode (OLED) technology. The PCB (Printed Circuit Board) back plate used by the heat conductive plate needs to have the characteristics of good heat conductivity, low thermal expansion coefficient, good electrical performance, mechanical strength, size adaptation and the like.

In the process of pasting the PCB, the size of the single PCB is too small, so that the PCB is difficult to be installed on a chip mounter, the efficiency of pasting and packaging is reduced, and the production efficiency is further reduced, so that the single PCB is designed and spliced together to form a PCB spliced plate with a larger size. Referring to fig. 1, a PCB panel in the prior art includes a functional area 3 and a non-functional area 1, the functional area 3 includes a plurality of sub-PCBs 4 spliced together, and the non-functional area 1 is provided with a filling layer 2.

However, the filling layer 2 disposed in the non-functional area 1 is a monolithic filling layer, and the filling layer 2 may cause uneven thermal expansion of the PCB panel, thereby causing warpage of the PCB panel and further affecting the quality of the PCB panel.

Disclosure of utility model

The application mainly aims to provide a PCB jointed board, and aims to solve the technical problems that a filling layer arranged in a nonfunctional area in the prior art can cause uneven thermal expansion of the PCB jointed board, so that the PCB jointed board is warped, and the quality of the PCB jointed board is affected.

In order to solve the technical problems, the application provides a PCB jointed board, which comprises at least one sub jointed board, wherein the sub jointed board comprises a functional area and a non-functional area surrounding the functional area;

the functional area comprises a plurality of sub-PCB boards which are connected with each other, the non-functional area is provided with a filling layer, and a plurality of stress release holes are formed in the filling layer along the thickness direction of the filling layer.

In one possible embodiment, a plurality of the stress relief holes form a grid-like group of holes, and the filler layer comprises a grid-like copper layer.

In one possible embodiment, the depth of the stress relief holes is equal to the thickness of the filler layer.

In one possible embodiment, a plurality of the stress relief holes are uniformly provided on the filler layer.

In one possible embodiment, the stress relief holes have a side length in the range of 6mil to 15mil, and/or the spacing between adjacent stress relief holes is in the range of 6mil to 15mil, and/or the filler layer has a thickness in the range of 18 μm to 35 μm.

In one possible implementation manner, a first cutting groove is arranged between adjacent sub-PCB boards, and the first cutting groove extends to the nonfunctional area.

In one possible embodiment, the non-functional area is further provided with a marking groove communicated with the first cutting groove, and the marking groove is internally provided with a marking protrusion.

In one possible embodiment, the front projection of the identification projection is T-shaped.

In one possible embodiment, the number of the sub-panels is two, and the nonfunctional areas of the two sub-panels are connected to each other.

In one possible embodiment, the non-functional areas of two of the sub-panels are provided with a second cut-out groove, said second cut-out groove being located between two of the sub-panels.

Compared with the prior art, the application has the following beneficial effects:

According to the PCB jointed board provided by the embodiment of the application, the stress release holes are formed in the filling layer, so that the stress of the filling layer can be released by the stress release holes, the thermal expansion of the PCB jointed board can be more uniform, the warpage phenomenon of the PCB jointed board is not easy to occur, and the quality of the PCB jointed board can be improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic top view of a prior art PCB panel according to an embodiment of the present application;

Fig. 2 is a schematic top view of a PCB panel according to an embodiment of the present application;

FIG. 3 is a schematic top view of a PCB panel including identification protrusions according to an embodiment of the present application;

Fig. 4 is a schematic cross-sectional view of a PCB panel according to an embodiment of the present application.

Reference numerals: 1. a nonfunctional area; 2. a filling layer; 21. a stress relief hole; 3. a functional area; 4. a sub-PCB board; 5. sub-jointed boards; 6. a first cutting groove; 7. a marking groove; 8. a marking protrusion; 9. a second cutting groove; 10. a substrate; 11. a first functional layer; 12. a second functional layer; 13. a third functional layer; 14. and a fourth functional layer.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.

In the description of the present application, it should be noted that the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.

Referring to fig. 2, the present application provides a PCB panel, which includes at least one sub panel 5, the sub panel 5 includes a functional area 3 and a non-functional area 1 surrounding the functional area 3, the functional area 3 includes a plurality of sub PCB boards 4 connected to each other, the non-functional area 1 is provided with a filling layer 2, and the filling layer 2 is provided with a plurality of stress release holes 21 along a thickness direction of the filling layer 2.

The PCB jointed boards are mainly used for the silicon-based OLED micro-display screen, the sub jointed boards 5 in the PCB jointed boards are connected with the sub jointed boards 5 in a conventional mode, for example, the PCB jointed boards can be integrally formed, and the sub PCB 4 in one sub jointed board 5 is also connected with the sub PCB 4 in a conventional mode, for example, the sub jointed boards can be integrally formed. The thickness of the sub-PCB 4 is typically 1.6mm, 1.2mm, 1.0mm and 0.8mm, and in the field of silicon-based OLED microdisplay, a thinner sub-PCB 4 is required to be used as a back-plane, for example, a PCB with a thickness of 0.5 mm.

The functional area 3 of the sub-jointed board 5 comprises a plurality of sub-PCB boards 4 which are arranged in an array manner, and the sub-PCB boards 4 are provided with electronic components and pin areas according to the design requirements of the silicon-based display screen. The electronic components include, but are not limited to, resistors, driver chips, capacitors, connectors, and the like. As an exemplary illustration, resistors, capacitors, connectors are electrically connected to the driver chip and the lead area is used to connect the OLED driver circuit to the OLED display panel.

The non-functional area 1 of the sub-jointed board 5 is provided with a filling layer 2, the filling layer 2 comprises a copper layer, a plurality of stress release holes 21 are formed in the copper layer, when the PCB jointed board is in a high-temperature environment, the PCB jointed board can be thermally expanded and generate stress, and when the stress is transferred to the stress release holes 21, at least part of the stress can be released by the stress release holes 21, so that the stress suffered by the PCB jointed board can be reduced, and the bending or deformation problem of the PCB jointed board can be improved.

Based on the above design, in this embodiment, the stress release hole 21 is formed on the filling layer 2, so that the stress of the filling layer 2 can be released by the stress release hole 21, and the thermal expansion of the PCB panel is more uniform, so that the PCB panel is not easy to warp, and the quality of the PCB panel can be improved.

In some embodiments, referring again to fig. 2, the plurality of stress relief holes 21 form a grid-like group of holes, and the filler layer 2 comprises a grid-like copper layer. The latticed copper layers form latticed copper sheets, and the latticed copper sheets connect the copper sheets on the process edges together in a latticed mode. Therefore, the toughness of the PCB jointed board can be enhanced, and more stress can be released, so that the warping problem of the PCB jointed board in the process of sticking and packaging can be further improved.

In some embodiments, the depth of the stress relief holes 21 is equal to the thickness of the filler layer 2, and the stress relief holes 21 extend through the filler layer 2. In this way, the stress release holes 21 can release more stress, so that the warpage problem caused by the PCB jointed board in the process of pasting and packaging can be further improved.

In some embodiments, referring again to fig. 2, a plurality of stress relief holes 21 are uniformly provided on the filler layer 2. Thus, the stress of the PCB splice can be more uniformly released by the plurality of uniformly arranged stress release holes 21, so that the thermal expansion of the PCB splice can be more uniform.

In some embodiments, the stress relief holes 21 may have a side length in the range of 6 mils to 15 mils, e.g., the stress relief holes 21 may have a side length of 6 mils, 7 mils, 8 mils, 10 mils, 12 mils, 13 mils, 14 mils, 15 mils, etc. If the side length of the stress release hole 21 is set too large, the flatness of the functional area of the sub-panel 5 is affected, and if the side length of the stress release hole 21 is set too small, the effect of releasing the stress by the stress release hole 21 is affected. Therefore, the reasonable side length of the stress release hole 21 can not influence the flatness of the functional area of the sub-jointed board 5, but also the effect of releasing the stress of the stress release hole 21.

Preferably, the spacing between adjacent stress relief holes 21 is in the range of 6mil to 15mil, i.e., the line width of the mesh copper is in the range of 6mil to 15mil. For example, the spacing of the stress relief holes 21 may be 6mil, 7mil, 8mil, 10mil, 12mil, 13mil, 14mil, 15mil, or the like. If the spacing between adjacent stress relief holes 21 is set too large, the density of the stress relief holes 21 is reduced, thereby reducing the effect of the stress relief holes 21 to relieve stress. If the spacing between adjacent stress relief holes 21 is set too small, the strength of the grid copper and thus the quality of the PCB panel is affected. Therefore, the spacing between the adjacent stress release holes 21 is set reasonably, so that the effect of releasing the stress by the stress release holes 21 is not affected, and the strength of the grid copper is not affected.

Preferably, the thickness of the filler layer 2 ranges from 18 μm to 35 μm, for example, the thickness of the filler layer 2 may be 18 μm, 20 μm, 22 μm, 25 μm, 30 μm, 32 μm, 34 μm, 35 μm, or the like. The filling layer 2 is mainly used for filling up the nonfunctional area 1, so that the functional area and the nonfunctional area 1 of the PCB jointed board are flush, and the flatness of the PCB jointed board can be influenced by too thick or too thin filling layer 2. Therefore, the thickness of the filling layer 2 is reasonably set, so that the flatness of the PCB jointed board is better, and the effect of releasing stress by the stress release holes 21 of the filling layer 2 is not affected.

In some embodiments, referring to fig. 3, first cutting grooves 6 are disposed between adjacent sub-PCB boards 4, and the first cutting grooves 6 extend to the non-functional area 1. Grid copper at the first cutting groove 6 is disconnected, and the packaged sub-PCB 4 is cut into a single independent PCB more easily through the first cutting groove 6, namely, later-stage board separation is facilitated.

In some embodiments, referring again to fig. 3, the non-functional area 1 is further provided with a marking groove 7 in communication with the first cutting groove 6, and the marking groove 7 is provided with a marking protrusion 8. Grid copper disconnection of sign groove 7 department, the bellied 8 material of sign can be copper, through set up sign protruding 8 in sign groove 7, when cutting to sub PCB board 4, can play the marking effect to can find the cutting groove more easily, and then can cut sub PCB board 4 into independent PCB board more accurately.

Preferably, the orthographic projection shape of the identification projection 8 is T-shaped. The T-shaped identification bulge 8 comprises a right angle, a corner angle and the like, so that the center point of the identification bulge 8 can be found more easily, and the position where the sub PCB 4 needs to be cut can be found more accurately.

In some embodiments, referring again to fig. 3, the number of sub-panels 5 is two, and the nonfunctional areas 1 of the two sub-panels 5 are interconnected. The two sub-jointed boards 5 can be integrally formed to form a rectangular structure, so that the PCB jointed boards can comprise more sub-PCB boards 4, and therefore the more sub-PCB boards 4 can be subjected to surface mounting and packaging at one time, and the surface mounting and packaging efficiency of the sub-PCB boards 4 can be improved.

Preferably, more sub-jointed boards 5 can be connected to form a PCB jointed board according to the corresponding jig, so that the sticking and packaging efficiency of the sub-PCB 4 can be further improved.

In some embodiments, referring again to fig. 3, the non-functional areas 1 of the two sub-panels 5 are provided with second cut grooves 9, the second cut grooves 9 being located between the two sub-panels 5. The grid copper at the second cutting groove 9 is disconnected, and after the PCB jointed board is packaged, the PCB jointed board can be cut off along the second cutting groove 9. Thus, the plurality of sub-panels 5 after encapsulation are cut apart more easily by the second cutting groove 9.

Preferably, referring to fig. 4, in the longitudinal direction, the sub-panel 5 includes a substrate 10, a first functional layer 11 located on one side of the substrate 10, a second functional layer 12 located on one side of the first functional layer 11 away from the substrate 10, a third functional layer 13 located on one side of the second functional layer 12 away from the substrate 10, and a fourth functional layer 14 located on one side of the third functional layer 13 away from the substrate 10.

The first functional layer 11 is typically used for laying out and wiring ground circuits to provide ground connections, and electronic components, connection lines, and other necessary circuit elements may be provided on the first functional layer 11. The primary function of the second functional layer 12 is to provide a power connection, and the second functional layer 12 is typically used to lay a power plane to provide a power connection for the circuit, while also providing shielding and noise filtering functions. The main function of the third functional layer 13 is to provide a ground connection, the third functional layer 13 typically being used to lay a large area of ground plane to provide a ground connection for the circuit, while also providing shielding and interference rejection functions. The fourth functional layer 14 is typically used for laying out and wiring signal circuits, and electronic components, connection lines, and other necessary circuit elements may be provided on the fourth functional layer 14.

In summary, the stress release holes 21 are formed in the filling layer 2, so that the stress of the filling layer 2 can be released by the stress release holes 21, the thermal expansion of the PCB jointed board can be more uniform, the warpage phenomenon of the PCB jointed board is not easy to occur, and the quality of the PCB jointed board can be improved. Meanwhile, since the stress relief holes 21 are provided on the filler layer 2, the weight of the PCB panel is reduced, the load of the production equipment is reduced, and the cost of manufacturing the PCB panel is reduced.

The above is merely various embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. -A PCB panel, characterized in that it comprises at least one sub-panel (5), said sub-panel (5) comprising a functional area (3) and a non-functional area (1) surrounding said functional area (3);

the functional area (3) comprises a plurality of sub-PCB boards (4) which are connected with each other, the nonfunctional area (1) is provided with a filling layer (2), and a plurality of stress release holes (21) are formed in the filling layer (2) along the thickness direction of the filling layer (2).

2. -PCB panel according to claim 1, characterized in that a plurality of said stress relief holes (21) form a grid-like group of holes, said filling layer (2) comprising a grid-like copper layer.

3. -PCB panel according to claim 1, characterized in that the depth of the stress relief holes (21) is equal to the thickness of the filling layer (2).

4. -PCB panel according to claim 1, characterized in that a plurality of said stress relief holes (21) are uniformly provided on said filling layer (2).

5. The PCB panel of claim 1, wherein the stress relief holes (21) have a side length in the range of 6mil to 15mil and/or the spacing between adjacent stress relief holes (21) is in the range of 6mil to 15mil and/or the thickness of the filler layer (2) is in the range of 18 μm to 35 μm.

6. The PCB panel of claim 1, wherein a first cut groove (6) is provided between adjacent sub-PCB boards (4), the first cut groove (6) extending to the non-functional area (1).

7. The PCB jigsaw according to claim 6, wherein the non-functional area (1) is further provided with a marking groove (7) communicating with the first cutting groove (6), and a marking protrusion (8) is arranged in the marking groove (7).

8. -PCB panel according to claim 7, characterized in that the orthographic projection of the identification protuberance (8) is T-shaped.

9. The PCB panel according to any of the claims 1 to 8, characterized in that the number of sub-panels (5) is two, the non-functional areas (1) of two sub-panels (5) being interconnected.

10. The PCB panel according to claim 9, characterized in that the nonfunctional area (1) of both of the sub-panels (5) is provided with a second cut-out groove (9), said second cut-out groove (9) being located between both of the sub-panels (5).