CN221042829U

CN221042829U - Isolation circuit and integrated circuit

Info

Publication number: CN221042829U
Application number: CN202323076503.0U
Authority: CN
Inventors: 梁锦兴; 谭晓亮; 李伟明
Original assignee: Ambulanc Shenzhen Tech Co Ltd
Current assignee: Ambulanc Shenzhen Tech Co Ltd
Priority date: 2023-11-13
Filing date: 2023-11-13
Publication date: 2024-05-28
Anticipated expiration: 2033-11-13

Abstract

The application relates to an isolation circuit and an integrated circuit, which comprise an output circuit, an input circuit and an isolation element, wherein the output circuit is connected with the isolation element and a processor; the output circuit and the input circuit are connected to the same port of the processor. The output circuit receives the output signal sent by the processor and transmits the output signal to the isolation element; the input circuit receives the input signal transmitted by the isolation element and transmits the input signal to the processor. According to the application, the isolation element is arranged to isolate the input circuit and the output circuit of the single IO port, so that the output signal and the input signal of the processor are isolated through the isolation element, and communication isolation is realized. Therefore, signal isolation in single IO port communication is realized, and the stability of signal transmission is improved.

Description

Isolation circuit and integrated circuit

Technical Field

The application relates to the technical field of communication, in particular to an isolation circuit and an integrated circuit.

Background

In electrical or electronic circuits, multiple communications between a single chip or chip may be involved. In order to avoid the influence of external environments such as magnetic fields and the like between multi-path communication, an isolation circuit is generally arranged to avoid interference between signals, so that communication quality is ensured. Among them, dual Input/Output ports (i.e., one IO port is used for receiving signals and one IO port is used for transmitting signals) are generally adopted between the singlechips.

In order to relieve the load of an IO port of the singlechip, a single IO port communication mode is provided, and the singlechip realizes signal receiving and transmitting through one IO port. When the singlechip adopts single IO port communication, how to isolate signals is still a problem to be solved.

Disclosure of utility model

In view of the foregoing, it is desirable to provide an isolation circuit and an integrated circuit that can isolate single IO port communications.

In a first aspect, the present application provides an isolation circuit comprising an output circuit, an input circuit, and an isolation element, the output circuit connecting the isolation element and a processor, the input circuit connecting the isolation element and the processor; the output circuit and the input circuit are connected to the same port of the processor;

The output circuit receives an output signal sent by the processor and transmits the output signal to the isolation element; the input circuit receives an input signal transmitted by the isolation element and transmits the input signal to the processor.

In one embodiment, the isolation element includes a first isolator connected to the output circuit and a second isolator connected to the input circuit.

In one embodiment, the isolation element comprises an optocoupler.

In one embodiment, the isolation element further comprises an isolated drive power supply coupled to the optocoupler.

In one embodiment, the output circuit comprises a driving switch tube, a control end of the driving switch tube is connected with the processor, an input end of the driving switch tube is connected with the isolation element, and an output end of the driving switch tube is grounded.

In one embodiment, the output circuit further includes a filter circuit, and the filter circuit is connected to the processor, the control end of the driving switch tube, and the input circuit.

In one embodiment, the input circuit includes a receiving switch tube, a control end of the receiving switch tube is connected with the isolation element and the signal voltage source, an input end of the receiving switch tube is connected with the signal voltage source, and an output end of the receiving switch tube is connected with the processor.

In one embodiment, the input circuit further comprises a voltage stabilizing circuit, and the voltage stabilizing circuit is connected with the isolation element, the control end of the receiving switch tube and the signal voltage source.

In a second aspect, the application also provides an integrated circuit comprising a processor and an isolation circuit as described above, the isolation circuit being connected to the processor.

In one embodiment, the processor is a single-chip microcomputer.

The isolation circuit and the integrated circuit comprise an output circuit, an input circuit and an isolation element, wherein the output circuit is connected with the isolation element and the processor, and the input circuit is connected with the isolation element and the processor; the output circuit and the input circuit are connected to the same port of the processor. The output circuit receives the output signal sent by the processor and transmits the output signal to the isolation element; the input circuit receives the input signal transmitted by the isolation element and transmits the input signal to the processor. According to the application, the isolation element is arranged to isolate the input circuit and the output circuit of the single IO port, so that the output signal and the input signal of the processor are isolated through the isolation element, and communication isolation is realized. Therefore, signal isolation in single IO port communication is realized, and the stability of signal transmission is improved.

Drawings

FIG. 1 is a diagram of an application environment for a isolation circuit in one embodiment;

FIG. 2 is a schematic diagram of a isolation circuit in one embodiment;

FIG. 3 is a schematic diagram of a isolation circuit in another embodiment;

FIG. 4 is a schematic diagram of an output circuit in one embodiment;

FIG. 5 is a schematic circuit diagram of an output circuit in one embodiment;

FIG. 6 is a schematic diagram of an input circuit in one embodiment;

FIG. 7 is a schematic circuit diagram of an input circuit in one embodiment;

fig. 8 is a schematic circuit diagram of a further embodiment isolation circuit.

Detailed Description

The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.

It will be understood that the terms first, second, etc. as used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. For example, a first resistance may be referred to as a second resistance, and similarly, a second resistance may be referred to as a first resistance, without departing from the scope of the application. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

It is to be understood that in the following embodiments, "connected" is understood to mean "electrically connected", "communicatively connected", etc., if the connected circuits, modules, units, etc., have electrical or data transfer between them.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

The isolation circuit provided by the embodiment of the application can be applied to an application environment shown in figure 1. The processor 102 is connected to the isolation circuit 104, specifically, the same port of the processor 102 is connected to the isolation circuit 104, and the isolation circuit 104 may transmit the isolated input signal to the processor 102, or may isolate the output signal of the processor 102 and output the isolated input signal. The isolation circuit 104 according to the embodiments of the present application can realize an isolated input and an isolated output of a single port of the processor 102.

Optionally, the processor 102 is a single-chip microcomputer, the single-chip microcomputer has pins, and the isolation circuit 104 is connected with one pin (one I/O port) of the single-chip microcomputer, so as to realize isolated signal transceiving.

In one embodiment, as shown in FIG. 2, an isolation circuit 104 is provided, the isolation circuit 104 comprising an output circuit 202, an input circuit 204, and an isolation element 206, the output circuit 202 connecting the isolation element 206 and the processor 102, the input circuit 204 connecting the isolation element 206 and the processor 102. The output circuit 202 and the input circuit 204 are connected to the same port of the processor 102, so as to implement single I/O port communication of the processor 102.

Specifically, the output circuit 202 is connected to the processor 102, receives an output signal sent by the processor 102, and transmits the output signal to the isolation element 206. The isolation element 206 isolates the output signal for output to a processing device (e.g., a device other than the processor 102 having a processing function, such as another single-chip microcomputer). The input circuit 204 is connected to the processor 102 and to a processing device via the isolation element 206, the processing device outputting an input signal to the isolation element 206, the input circuit 204 being connected to the isolation element 206, receiving the input signal transmitted by the isolation element 206 and transmitting the input signal to the processor 102. It should be noted that the processing device that receives the output signal from the output circuit 202 and the processing device that sends the input signal to the input circuit 204 may be different processing devices or the same processing device.

Alternatively, the composition of the isolation element 206 is not limited, and may be a circuit and an isolation device capable of achieving bidirectional isolation of a signal, for example, a device having an isolation function such as a digital isolator. More than two unidirectional isolation devices or circuits may also be included to isolate the input signal from the output signal, respectively.

In one embodiment, as shown in FIG. 3, the isolation element 206 includes a first isolator 302 and a second isolator 304, the first isolator 302 coupled to the output circuit 202 and the second isolator 304 coupled to the input circuit 204.

Specifically, the processor 102 sends an output signal to the output circuit 202, and the output circuit 202 transmits the output signal to the connected processing device through the first separator 302. The processing device outputs an input signal to the second separator 304, and the input circuit 204 is coupled to the second separator 304, receives the input signal transmitted by the second separator 304, and transmits the input signal to the processor 102. Through setting up independent barrier to input signal and output signal respectively, the rethread barrier (first barrier 302 or second barrier 304) keeps apart the transmission of signal, has both realized the isolation of the transmission process of signal, has kept apart between input signal and the output signal again, has ensured the stability and the reliability of isolation, makes the transmission of input signal and output signal not mutually interfere.

To achieve stable signal isolation, in one embodiment, isolation element 206 comprises an optocoupler. Illustratively, the optocoupler may be of the type EL357. The optical coupler has the advantages that when signals are transmitted unidirectionally, the input end and the output end of the optical coupler are completely electrically isolated, and the optical coupler has the characteristics of strong anti-interference capability, long service life and high transmission efficiency.

When the isolation element 206 includes the first isolation member 302 and the second isolation member 304, the first isolation member 302 and the second isolation member 304 may be optical couplers, and the type of the optical couplers is not limited, and the first isolation member 302 and the second isolation member 304 may be the same type of optical coupler.

In this embodiment, by selecting the optical coupler as the isolation element 206, the input signal and the output signal of the processor 102 can be reliably isolated, which is beneficial to improving the stability of the isolation circuit 104.

In one embodiment, the isolation element 206 further includes an isolation driving power source connected to the optocoupler, where the isolation driving power source is used to provide an operating voltage of the optocoupler, and the optocoupler can output the output signal in an optical signal manner according to the power supply of the isolation driving power source, so as to implement isolation output of the output signal.

When the isolation element 206 includes the first isolator 302 and the second isolator 304, and the first isolator 302 and the second isolator 304 are both optocouplers, the isolation driving power source is connected to the first isolator 302, and the isolated output of the output signal is achieved by supplying power to the first isolator 302.

In the above embodiment, the isolation circuit 104 includes the output circuit 202, the input circuit 204, and the isolation element 206, the output circuit 202 connects the isolation element 206 and the processor 102, and the input circuit 204 connects the isolation element 206 and the processor 102; the output circuit 202 and the input circuit 204 are connected to the same port of the processor 102. Output circuit 202 receives the output signal from processor 102 and transmits the output signal to isolation element 206; the input circuit 204 receives the input signal transmitted by the isolation element 206 and transmits the input signal to the processor 102. According to the application, the isolation element 206 is arranged to isolate the input circuit 204 and the output circuit 202 of the single IO port, so that the output signal and the input signal of the processor 102 are isolated through the isolation element 206, and communication isolation is realized. Therefore, signal isolation in single IO port communication is realized, and the stability of signal transmission is improved.

In one embodiment, as shown in fig. 4, the output circuit 202 includes a driving switch tube 402, a control terminal of the driving switch tube 402 is connected to the processor 102, an input terminal of the driving switch tube 402 is connected to the isolation element 206, and an output terminal of the driving switch tube 402 is grounded.

Specifically, the control end of the driving switch tube 402 is connected to the processor 102, so that an output signal of the processor 102 can be collected, and an output signal expression form of the processor 102 can be a level change of a port. The output signal of the processor 102 controls the operating state of the driving switching tube 402, thereby changing the operating state of the isolation element 206. For example, if the driving switch tube 402 is an NMOS tube, the NMOS tube is turned off when the port of the processor 102 outputs a low level; when the port of the processor 102 outputs a high level, the NMOS transistor is turned on. And when the NMOS transistor is turned on, the isolation element 206 is controlled to be in a corresponding operating state, for example, the optocoupler emits light.

To ensure more stable transmission of the output signal, in one embodiment, the output circuit 202 further includes a filter circuit 404, where the filter circuit 404 is connected to the processor 102, the control terminal of the driving switch tube 402, and the input circuit 204.

Specifically, the filter circuit 404 receives the output signal sent by the processor 102, filters the output signal, and transmits the filtered output signal to the control terminal of the driving switch tube 402. Meanwhile, since the input circuit 204 and the output circuit 202 are connected to the same port of the processor 102, the filter circuit 404 is also connected to the input circuit 204. Referring to fig. 5, an example of the output circuit 202 in an embodiment is shown, in which the driving switch tube 402 is a switch tube Q2, and the filtering circuit 404 includes a resistor R5 and a capacitor C1, which form an RC circuit, and filters an output signal. MCU1-IO is the port (I/O port) of processor 102, and filter circuit 404 passes through resistance R6 to be connected input circuit 204, and filter circuit 404 passes through resistance R4 ground (MCU 1-GND), and filter circuit 404 connects the control end of switch tube Q2. The input end of the switching tube Q2 is connected with the isolation element 206, and the output end of the switching tube Q2 is grounded.

The switching tube Q2 is an NMOS tube, and is exemplified by Si2318DS. The resistances of the resistor R5, the resistor R6 and the resistor R4 are all 1KΩ, and the capacitance value of the capacitor C1 is 100nF.

In this embodiment, the filtering circuit 404 filters the output signal, and transmits the filtered output signal to the driving switch tube 402, and the driving switch tube 402 controls the isolation element 206, so as to realize isolated output of the output signal, and ensure stable and reliable output process of the output signal.

In one embodiment, as shown in fig. 6, the input circuit 204 includes a receiving switch tube 602, a control terminal of the receiving switch tube 602 is connected to the isolation element 206 and the signal voltage source, an input terminal of the receiving switch tube 602 is connected to the signal voltage source, and an output terminal of the receiving switch tube 602 is connected to the processor 102. The signal voltage source can output a constant voltage as a signal voltage, and the signal voltage source transmits a voltage change to the processor 102 under the control of the receiving switch tube 602 along with a change of an input signal, which is equivalent to generating the input signal.

Specifically, the control terminal of the receiving switch tube 602 is connected to the isolation element 206, so as to collect the input signal transmitted by the isolation element 206, where the input signal may represent a level change of the isolation element 206. The input signal transmitted by the isolation element 206 controls the working state of the receiving switch tube 602, so as to change the on-off state between the signal voltage source and the processor 102, thereby realizing the transmission of the input signal. For example, if the receiving switch tube 602 is a PMOS tube, the isolation element 206 turns on when the control terminal of the receiving switch tube 602 transmits a low level; when the isolation element 206 delivers a high level to the control terminal of the receiving switching tube 602, the PMOS tube is turned off. When the PMOS transistor is turned on, the signal voltage source is turned on to the processor 102, and the processor 102 receives the input signal.

To ensure more stable transmission of the input signal, in one embodiment, the input circuit 204 further includes a voltage stabilizing circuit 604, where the voltage stabilizing circuit 604 is connected to the isolation element 206, the control terminal of the receiving switch 602, and the signal voltage source.

Specifically, the voltage stabilizing circuit 604 receives the input signal transmitted by the isolation element 206, stabilizes the input signal, and transmits the stabilized input signal to the control terminal of the receiving switching tube 602 and the signal voltage source. Referring to fig. 7, an example of an input circuit 204 in an embodiment is shown, in which the receiving switch tube 602 is a switch tube Q3, the voltage stabilizing circuit 604 includes a resistor R9 and a capacitor R10, and the resistor R9 and the resistor R10 stabilize an input signal and then transmit the stabilized input signal to the switch tube Q3 and a signal voltage source (MCU 1-3.3V). A resistor R9 in the voltage stabilizing circuit 604 is connected to the isolation element 206 and the control end of the switching tube Q3, and a resistor R10 in the voltage stabilizing circuit 604 is connected to the common end of the resistor R9 and the switching tube Q3 and the signal voltage source. The input end of the switching tube Q3 is connected with the processor 102, and the output end of the switching tube Q3 is connected with a signal voltage source.

The switch tube Q3 is a PMOS tube, and the model is SI2343DS. The resistance of the resistor R9 is 1KΩ, the resistance of the resistor R10 is 10KΩ, and the voltage of the signal voltage source is 3.3V.

In this embodiment, the isolation element 206 is used to transmit an input signal, and the voltage stabilizing circuit 604 stabilizes the input signal and transmits the stabilized input signal to the receiving switch tube 602, so as to realize isolated input of the input signal, and ensure stable and reliable input process of the input signal.

Based on the same technical concept, in one embodiment, as shown in fig. 1, the application further provides an integrated circuit, where the integrated circuit includes a processor 102 and an isolation circuit 104 as described in the above embodiments, and the isolation circuit 104 is connected to the processor 102.

In one embodiment, the processor 102 is a single-chip microcomputer that communicates with other single-chip microcomputers through a single I/O port. The single-chip microcomputer is provided with an open-drain input mode and an output mode, and when the single-chip microcomputer is in the open-drain input mode, an I/O port of the single-chip microcomputer only receives an input signal and does not send an output signal; when the singlechip is in an output mode, the I/O port of the singlechip only transmits output signals and does not receive input signals. The mode configuration of the singlechip is as follows: when the singlechip is in the output mode and transmits the output signal, the singlechip is switched to the open-drain input mode, and the singlechip is switched back to the output mode and retransmits the output signal under the condition that the input signal is not received within a set time.

In order to better understand the above solution, the following detailed explanation is made in connection with a specific embodiment in connection with the application scenario shown in fig. 8.

In one embodiment, as shown in fig. 8, an integrated circuit is provided, which comprises a processor and an isolation circuit, wherein the number of singlechips is two, and the singlechips are marked as a singlechip 1 and a singlechip 2, correspondingly, the ports of the singlechip 1 are marked as MCU1-IO, and the ports of the singlechip 2 are marked as MCU2-IO. There are also two isolation circuits, labeled isolation circuit 1 and isolation circuit 2, wherein the isolation elements of isolation circuit 1 and isolation circuit 2 may be shared.

The isolation circuit 1 comprises an output circuit, an input circuit and an isolation element, wherein the output circuit comprises a driving switch tube and a filter circuit, the driving switch tube is a switch tube Q2, and the filter circuit comprises a resistor R5 and a capacitor C1. The input circuit comprises a receiving switch tube and a voltage stabilizing circuit, wherein the receiving switch tube is a switch tube Q3, and the voltage stabilizing circuit comprises a resistor R9 and a resistor R10. The isolation element comprises an optocoupler U1, an optocoupler U2 and a first isolation driving power supply (MCU 1-24V) for driving the optocoupler U1, wherein a transmitting end of the optocoupler U1 is connected with the MCU1-24V and the switching tube Q2, and a receiving end of the optocoupler U1 is connected with the isolation circuit 2. The receiving end of the optical coupler U2 is connected with the resistor R9 and grounded, and the transmitting end of the optical coupler U2 is connected with the isolation circuit 2.

The isolation circuit 2 comprises an output circuit, an input circuit and an isolation element, wherein the output circuit comprises a driving switch tube and a filter circuit, the driving switch tube is a switch tube Q4, and the filter circuit comprises a resistor R11 and a capacitor C2. The input circuit comprises a receiving switch tube and a voltage stabilizing circuit, wherein the receiving switch tube is a switch tube Q1, and the voltage stabilizing circuit comprises a resistor R2 and a resistor R3. The isolation element comprises an optocoupler U1, an optocoupler U2 and a second isolation driving power supply (MCU 2-24V) for driving the optocoupler U2, wherein the transmitting end of the optocoupler U2 is connected with the MCU2-24V and the switching tube Q4, and the receiving end of the optocoupler U2 is connected with the isolation circuit 1. The receiving end of the optical coupler U1 is connected with the resistor R3 and grounded, and the transmitting end of the optical coupler U1 is connected with the isolation circuit 1.

When the singlechip 1 sends data to the singlechip 2, the singlechip 1 sets the MCU1-IO as an output mode, the singlechip 2 sets the MCU2-IO as an open-drain input mode, and signals are transmitted between IO ports by sending high and low levels. When the MCU1-IO is at a high level, the switching tube Q2 and the switching tube Q1 are conducted, and the MCU2-IO receives a high level signal sent by the MCU 1-IO. The singlechip 2 acquires information sent by the singlechip 1 by reading the high and low levels of the MCU 2-IO. After the singlechip 1 sends out a signal, the MCU1-IO of the singlechip 1 is switched from an output mode to an open-drain input mode, and waits for information sent back by the singlechip 2. If the signal sent by the singlechip 2 is not received after the set waiting time is exceeded, the MCU1-IO of the singlechip 1 is switched to the output mode again, and the signal is sent again. After the singlechip 2 receives the signal sent by the singlechip 1, the MCU2-IO is switched from the open-drain input module to an output mode, and the signal sent by the singlechip 1 is responded.

In the embodiment, the optical coupler is adopted to realize signal isolation between input and output, single IO port communication between the two singlechips is isolated, data transmission is performed in a crossing manner, isolated communication of the two singlechips in the single IO communication is realized, and the reliability of communication is enhanced.

The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples illustrate only a few embodiments of the utility model, which are described in detail and are not to be construed as limiting the scope of the utility model. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the utility model, which are all within the scope of the utility model. Accordingly, the scope of protection of the present utility model is to be determined by the appended claims.

Claims

1. An isolation circuit is characterized by comprising an output circuit, an input circuit and an isolation element, wherein the output circuit is connected with the isolation element and a processor, and the input circuit is connected with the isolation element and the processor; the output circuit and the input circuit are connected to the same port of the processor;

2. The isolation circuit of claim 1, wherein the isolation element comprises a first isolation member and a second isolation member, the first isolation member connecting the output circuit and the second isolation member connecting the input circuit.

3. The isolation circuit of claim 1, wherein the isolation element comprises an optocoupler.

4. The isolation circuit of claim 3, wherein the isolation element further comprises an isolation drive power supply coupled to the optocoupler.

5. The isolation circuit of claim 1, wherein the output circuit comprises a drive switching tube, a control end of the drive switching tube is connected with the processor, an input end of the drive switching tube is connected with the isolation element, and an output end of the drive switching tube is grounded.

6. The isolation circuit of claim 5, wherein the output circuit further comprises a filter circuit connecting the processor, the control terminal of the drive switch tube, and the input circuit.

7. The isolation circuit of claim 1, wherein the input circuit comprises a receiving switching tube, a control terminal of the receiving switching tube is connected to the isolation element and a signal voltage source, an input terminal of the receiving switching tube is connected to the signal voltage source, and an output terminal of the receiving switching tube is connected to the processor.

8. The isolation circuit of claim 7, wherein the input circuit further comprises a voltage regulator circuit connecting the isolation element, the control terminal of the receiving switching tube, and the signal voltage source.

9. An integrated circuit comprising a processor and an isolation circuit as claimed in any one of claims 1 to 8, the isolation circuit being connected to the processor.

10. The integrated circuit of claim 9, wherein the processor is a single-chip microcomputer.