CN113849437B - Communication interface device - Google Patents
Communication interface device Download PDFInfo
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- CN113849437B CN113849437B CN202111010276.4A CN202111010276A CN113849437B CN 113849437 B CN113849437 B CN 113849437B CN 202111010276 A CN202111010276 A CN 202111010276A CN 113849437 B CN113849437 B CN 113849437B
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- 238000004891 communication Methods 0.000 title claims abstract description 153
- 238000002955 isolation Methods 0.000 claims abstract description 92
- 230000000087 stabilizing effect Effects 0.000 claims description 38
- 239000003990 capacitor Substances 0.000 claims description 11
- 101100489713 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) GND1 gene Proteins 0.000 claims description 6
- 101100489717 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) GND2 gene Proteins 0.000 claims description 6
- 230000009977 dual effect Effects 0.000 claims description 2
- 230000005540 biological transmission Effects 0.000 abstract description 25
- 102100036285 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Human genes 0.000 description 4
- 101000875403 Homo sapiens 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Proteins 0.000 description 4
- 230000002457 bidirectional effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 206010033799 Paralysis Diseases 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0042—Universal serial bus [USB]
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Abstract
The application relates to a communication interface device, which comprises an isolation chip and a communication circuit, wherein the communication circuit comprises a communication chip and a switch circuit. When the isolating chip sends data to the singlechip, the isolating chip outputs low level to the switch circuit, and the switch circuit is cut off when receiving the low level, so that the communication chip receives and outputs the data sent by the singlechip through the isolating chip; when the single chip microcomputer does not send data, the isolation chip outputs high level to the switch circuit, and the switch circuit is conducted when receiving the high level, so that the communication chip transmits the received data to the single chip microcomputer through the isolation chip. The data transmission is carried out through the isolation chip, the automatic switching of the receiving and transmitting directions is realized by utilizing the switch circuit, the anti-interference performance can be improved, the automatic flow direction control function is realized, the control is enabled without an additional IO port, the use resources of the singlechip are reduced, and the receiving and transmitting directions are automatically switched.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a communications interface device.
Background
At present, in the industrial control industry, the RS-485 anti-noise anti-interference capability is strong, the transmission distance is long, multi-point communication is supported, and the serial interface is the preferred serial interface in the industry. The electrical characteristic specified by RS-485 is 2 wires, which is half-duplex multipoint communication. Therefore, when the RS-485 bus for multi-node long-distance communication is used as a communication network, the nodes are easy to interfere with each other, and the two forms are mainly represented, namely, reflection increases the distortion degree of signals; external disturbances are destroyed by the balanced condition and the common mode disturbance becomes a serial mode signal into the transmission line.
The traditional communication interface is only used for connecting the communication chip with the main control chip to carry out data transmission, has poor anti-interference performance, and because some communication chips (such as an RS-485 chip) are in a half-duplex mode, the receiving and transmitting states need to be switched through an additional interface during communication.
Disclosure of Invention
Based on this, it is necessary to provide a communication interface device, which can achieve the effect of improving the anti-interference performance and having the function of automatic flow direction control, aiming at the problems that the traditional communication interface has poor anti-interference performance and needs to switch the receiving and transmitting states through an additional interface.
A communication interface device, comprising:
The VOA pin of the isolation chip is used for being connected with the RX pin of the singlechip, and the VIB pin of the isolation chip is used for being connected with the TX pin of the singlechip;
The communication circuit comprises a communication chip and a switch circuit, wherein an RO pin of the communication chip is connected with a VIA pin of the isolation chip, and the communication chip The pin and the DE pin are connected with the switch circuit, and the switch circuit is connected with the VOB pin of the isolation chip;
The isolation chip outputs low level to the switch circuit when the singlechip sends data, and the switch circuit is cut off when receiving the low level, so that the communication chip receives and outputs the data sent by the singlechip through the isolation chip; when the single chip microcomputer does not send data, the isolation chip outputs high level to the switch circuit, and the switch circuit is conducted when receiving the high level, so that the communication chip transmits the received data to the single chip microcomputer through the isolation chip.
In one embodiment, the GND1 pin of the isolation chip is connected to the GND terminal, the GND2 pin of the isolation chip is connected to the PGND terminal, and the GND terminal and the PGND terminal are isolated from each other.
In one embodiment, the switching circuit includes a resistor R13, a resistor R14, a resistor R15, and a switching tube Q3, where the resistor R14 and the resistor R15 are connected in series and a common terminal is connected to the VOB pin of the isolation chip, the other end of the resistor R14 is connected to the control terminal of the switching tube Q3, the other end of the resistor R15 is connected to the power terminal, and the first end of the switching tube Q3 is connected to the communication chipThe second end of the switch tube Q3 is grounded; one end of the resistor R13 is connected with a power supply end, and the other end of the resistor R13 is connected with the first end of the switching tube Q3.
In one embodiment, the communication circuit further includes a resistor R16 and a capacitor C2, wherein one end of the resistor R16 is connected to a power supply terminal, and the other end of the resistor R16 is connected to an RO pin of the communication chip; one end of the capacitor C2 is connected with the VCC end and the power end of the communication chip, and the other end of the capacitor C2 is grounded.
In one embodiment, the communication circuit further includes a resistor R17, a resistor R18, and a resistor R19, where the resistor R18, the resistor R17, and the resistor R19 are sequentially connected in series, a common terminal of the resistor R18 and the resistor R17 is connected to a B pin of the communication chip, another terminal of the resistor R18 is grounded, a common terminal of the resistor R17 and the resistor R19 is connected to an a pin of the communication chip, and another terminal of the resistor R19 is connected to a power supply terminal.
In one embodiment, the communication circuit further includes a voltage stabilizing tube D6, a voltage stabilizing tube D7 and a voltage stabilizing tube D8, the voltage stabilizing tube D7, the voltage stabilizing tube D6 and the voltage stabilizing tube D8 are sequentially connected in series, the common end of the voltage stabilizing tube D7 and the common end of the voltage stabilizing tube D6 are connected with the pin B of the communication chip, the other end of the voltage stabilizing tube D7 is grounded, the common end of the voltage stabilizing tube D6 and the voltage stabilizing tube D8 is connected with the pin a of the communication chip, and the other end of the voltage stabilizing tube D8 is connected with the end AGND.
In one embodiment, the regulator tube D6, the regulator tube D7, and the regulator tube D8 are bidirectional regulator tubes.
In one embodiment, the communication chip is a 485 communication chip.
In one embodiment, the isolation chip is a dual channel digital isolator.
In one embodiment, the isolation chip is an ADuM3201 isolation chip.
The communication interface device comprises an isolation chip and a communication circuit, wherein the communication circuit comprises a communication chip and a switch circuit. When the isolating chip sends data to the singlechip, the isolating chip outputs low level to the switch circuit, and the switch circuit is cut off when receiving the low level, so that the communication chip receives and outputs the data sent by the singlechip through the isolating chip; when the single chip microcomputer does not send data, the isolation chip outputs high level to the switch circuit, and the switch circuit is conducted when receiving the high level, so that the communication chip transmits the received data to the single chip microcomputer through the isolation chip. The data transmission is carried out through the isolation chip, the automatic switching of the receiving and transmitting directions is realized by utilizing the switch circuit, the anti-interference performance can be improved, the automatic flow direction control function is realized, the control is enabled without an additional IO port, the use resources of the singlechip are reduced, and the receiving and transmitting directions are automatically switched.
Drawings
FIG. 1 is a schematic diagram of a structure of a separation chip according to an embodiment;
fig. 2 is a schematic diagram of a communication circuit in an embodiment.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or be connected to the other element through intervening elements. In the following embodiments, "connected" is understood to mean "electrically connected", "communicatively connected", and the like, if the connected circuits, modules, units, and the like have electrical or data transferred therebetween.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Meanwhile, the term used in the present specification includes any and all combinations of the items listed in association.
In one embodiment, as shown in fig. 1 and 2, there is provided a communication interface apparatus comprising:
the isolation chip U1, the VOA pin of the isolation chip U1 is used for connecting with the RX pin of the singlechip, and the VIB pin of the isolation chip U1 is used for connecting with the TX pin of the singlechip.
Communication circuit, communication circuit includes communication chip U2 and switch circuit 110, and the RO pin of communication chip U2 is connected the VIA pin of isolation chip U1, communication chip U2The pin and the DE pin are connected with the switch circuit 110, and the switch circuit 110 is connected with the VOB pin of the isolation chip U1.
When the single chip microcomputer sends data, the isolation chip U1 outputs low level to the switch circuit 110, and the switch circuit 110 is cut off when receiving the low level, so that the communication chip U2 receives and outputs the data sent by the single chip microcomputer through the isolation chip U1; when the single chip microcomputer does not send data, the isolation chip U1 outputs a high level to the switch circuit 110, and the switch circuit 110 is conducted when receiving the high level, so that the communication chip U2 transmits the received data to the single chip microcomputer through the isolation chip U1.
Specifically, pins 1 and 8 of the isolation chip U1 are a VDD1 pin and a VDD2 pin, which are both voltage pins used as a connection power supply, and pins 4 and 5 of the isolation chip U1 are a GND1 pin and a GND2 pin, which are both ground pins. The 2 pin is a VOA pin, is connected with a receiving pin RX of the singlechip, and the 3 pin of the isolation chip U1 is a VIB pin and is connected with a transmitting pin TX of the singlechip. The 7 pins of the isolation chip U1 are VIA pins, the RO pins of the communication chip U2 are connected, the 6 pins of the isolation chip U1 are VOB pins, and the switch circuit 110 is connected. Pins 1, 2, 3 and 4 of the communication chip U2 are RO pins respectively,Pin, DE pin and DI pin,/>The pin is connected to the switch circuit 110 with the DE pin and the DI pin is grounded. The 5 pin of the communication chip U2 is a GND pin and is grounded. Pins 6 and 7 of the communication chip U2 are pins A and pins B, and are respectively connected with external equipment through terminals A+ and B-for data transmission. And the pin 8 of the communication chip U2 is a VCC pin and is used for connecting a power supply.
The isolation chip U1 can be an ADuM3201 isolation chip or a same type chip. In this embodiment, the isolation chip U1 is a dual-channel digital isolator, and specifically an ADuM3201 isolation chip is adopted, which has enhanced reliability of system-level ESD (Electro-STATIC DISCHARGE, electrostatic discharge). The communication chip U2 can be a 485 communication chip, and can also be other types of communication chips. In this embodiment, the communication chip U2 is a 485 communication chip, and correspondingly, the communication circuit is a 485 communication circuit.
The VDD1 pin of the isolation chip U1 is connected with a 3.3V power supply, and the VDD2 pin of the isolation chip U1 is connected with a 5V power supply. The RO pin of the communication chip U2 is connected with a 3.3V power supply through a pull-up resistor, and the VCC pin of the communication chip U2 is connected with a 5V power supply. Further, in one embodiment, the GND1 pin of the isolation chip is connected to the GND terminal, the GND2 pin of the isolation chip is connected to the PGND terminal, and the ground is isolated between the GND terminal and the PGND terminal.
In one embodiment, the communication circuit further comprises a resistor R16 and a capacitor C2, wherein one end of the resistor R16 is connected with a power end, particularly connected with a 3.3V power end, and the other end of the resistor R16 is connected with an RO pin of the communication chip U2; one end of the capacitor C2 is connected with the VCC end and the power end (specifically, the 5V power end) of the communication chip U2, and the other end of the capacitor C2 is grounded.
The specific structure of the switch circuit 110 is not unique, and in one embodiment, as shown in fig. 2, the switch circuit 110 includes a resistor R13, a resistor R14, a resistor R15, and a switch tube Q3, where the resistor R14 and the resistor R15 are connected in series, and a common terminal is connected to the VOB pin of the isolation chip U1, the other end of the resistor R14 is connected to the control terminal of the switch tube Q3, and the other end of the resistor R15 is connected to the power terminal, and specifically connected to the 3.3V power terminal. A first end of the switch tube Q3 is connected with the communication chip U2The second end of the switch tube Q3 is grounded; one end of the resistor R13 is connected with the power end, and is specifically connected with the 3.3V power end, and the other end of the resistor R13 is connected with the first end of the switching tube Q3. The switching tube Q3 may be a triode or a MOS tube, in this embodiment, the switching tube Q3 is an NPN triode, the base is used as the control end, the collector is used as the first end, and the emitter is used as the second end.
In one embodiment, the communication circuit further includes a resistor R17, a resistor R18, and a resistor R19, where the resistor R18, the resistor R17, and the resistor R19 are sequentially connected in series, and a common terminal of the resistor R18 and the resistor R17 is connected to a B pin of the communication chip U2, another terminal of the resistor R18 is grounded, a common terminal of the resistor R17 and the resistor R19 is connected to an a pin of the communication chip U2, and another terminal of the resistor R19 is connected to a power supply terminal, specifically connected to a 5V power supply terminal.
Specifically, when the default singlechip does not send data, the VOB pin of the isolation chip U1 is at high level, the switch tube Q3 is conducted, and the communication chip U2The pins are enabled at low level, the RO pins receive data enabling, at this time, what data received from A, B pins of the communication chip U2 is transmitted to the MCU (Micro Control Unit, a micro control unit, also called a singlechip) through the isolating chip U1 by an RO channel, and the data receiving process is completed.
When the singlechip transmits data, the VOB of the isolation chip U1 has a pull-down level to indicate that the data transmission is started, the switching tube Q3 is cut off, and the DE pin of the communication chip U2 is enabled by high-level transmission. When the data '0' is sent, the data '0' is transmitted to the A, B port of the communication chip U2 because the DI pin of the communication chip U2 is connected to the ground, and the a-B <0, and the transmission of '0' completes the low level transmission. When '1' is sent, the switch tube Q3 is conducted, the RO pin is enabled, and the A, B pin of the communication chip U2 is in a high-resistance state in the state because the RO pin is still in the data sending state, the state at the moment pulls up the level of the A pin through the resistor R19, and the resistor R18 pulls down the B pin to determine. At this time, A-B >0 transmits '1', and the high level transmission is completed.
In addition, in one embodiment, with continued reference to fig. 2, the communication circuit further includes a voltage regulator tube D6, a voltage regulator tube D7, and a voltage regulator tube D8, where the voltage regulator tube D7, the voltage regulator tube D6, and the voltage regulator tube D8 are sequentially connected in series, a common end of the voltage regulator tube D7 and the voltage regulator tube D6 is connected to a B pin of the communication chip U2, another end of the voltage regulator tube D7 is grounded, a common end of the voltage regulator tube D6 and the voltage regulator tube D8 is connected to an a pin of the communication chip U2, and another end of the voltage regulator tube D8 is connected to an AGND end. The specific types of the voltage stabilizing tube D6, the voltage stabilizing tube D7 and the voltage stabilizing tube D8 are not unique, and in this embodiment, the voltage stabilizing tube D6, the voltage stabilizing tube D7 and the voltage stabilizing tube D8 are all bidirectional voltage stabilizing tubes.
In the communication interface device, when the isolation chip U1 sends data to the switch circuit 110, the switch circuit 110 is turned off when receiving the low level, so that the communication chip U2 receives the data sent by the single chip through the isolation chip U1 and outputs the data; when the single chip microcomputer does not send data, the isolation chip U1 outputs a high level to the switch circuit 110, and the switch circuit 110 is conducted when receiving the high level, so that the communication chip U2 transmits the received data to the single chip microcomputer through the isolation chip U1. The data transmission is carried out through the isolation chip U1, the automatic switching of the receiving and transmitting directions is realized by utilizing the switch circuit 110, the anti-interference performance can be improved, the automatic flow direction control function is realized, the control is enabled without an additional IO port, the use resources of the singlechip are reduced, and the receiving and transmitting directions are automatically switched.
In order to better understand the above communication interface device, a detailed explanation will be given below taking 485 communication interface device as an example.
As described in the background art, when the RS-485 bus of multi-node long-distance communication is used as a communication network, the nodes are easy to interfere with each other, and the reflection increases the signal distortion degree; external disturbances are destroyed by the balanced condition and the common mode disturbance becomes a serial mode signal into the transmission line. Further, since the half duplex mode is adopted, the transmission/reception state needs to be switched during communication. Therefore, the RS-485 communication needs to be isolated and has the function of automatic flow direction control. The existing RS-485 communication is either isolated by an optical coupler, limited in transmission rate and the like, or is transmitted and received under the control of an additional single-chip microcomputer IO port, rather than automatic transmission and receiving. Based on the above, the application provides a novel communication mode of the RS-485 interface device, which can isolate and receive and dispatch automatically and has an automatic flow direction control function.
The RS-485 communication interface device is a circuit consisting of a 485 communication circuit and an ADuM3201 isolation chip, the power supply is completely isolated from the signals, the device has very high EMI (Electromagnetic Interference and electromagnetic interference) performance, the data transmission rate is high, and the problem of an optical coupler is effectively solved. The device realizes the automatic flow direction control of the RS-485 signal, does not need an additional IO port to enable control, reduces the use resources of the singlechip and automatically switches the receiving and transmitting directions. In addition, the power supply of the 1 st pin VDD1 of the isolation chip is different from the power supply of the 8 th pin VDD2, the power supply of the subsequent 485 communication chip is homologous to the power supply of the VDD2, the GND1 of the 4 th pin and the GND2 of the 5 th pin of the isolation chip are not grounded together, a common loop is not formed, and the isolation effect is achieved.
When the single chip microcomputer sends data, the isolation chip U1 outputs low level to the switch circuit 110, and the switch circuit 110 is cut off when receiving the low level, so that the communication chip U2 receives and outputs the data sent by the single chip microcomputer through the isolation chip U1; when the single chip microcomputer does not send data, the isolation chip U1 outputs a high level to the switch circuit 110, and the switch circuit 110 is conducted when receiving the high level, so that the communication chip U2 transmits the received data to the single chip microcomputer through the isolation chip U1. The data transmission is carried out through the isolation chip U1, the automatic switching of the receiving and transmitting directions is realized by utilizing the switch circuit 110, the anti-interference performance can be improved, the automatic flow direction control function is realized, the control is enabled without an additional IO port, the use resources of the singlechip are reduced, and the receiving and transmitting directions are automatically switched.
Specifically, as shown in fig. 1 and 2, U1 is an ADuM3201 isolation chip, or may be a similar chip, U2 is a 485 communication chip, RO of the 1 st pin of the communication chip U2 is pulled up to 3.3V through a10 k resistor and connected to a 7 th pin VIA of the isolation chip U1, and the 2 nd pin of the communication chip U2The DE of the 3 rd pin is pulled up to 3.3V through a 10k resistor and is connected with a collector of the switching tube Q3, the 4 th pin DI and the 5 th pin GND of the communication chip U2 are connected with PGND, the 6 th pin A and the 7 th pin B of the communication chip U2 are output, and the 8 th pin of the communication chip U2 is connected with 5V. The 1 st pin VDD1 of the isolation chip U1 is 3.3V, the 2 nd pin VOA of the isolation chip U1 is connected with the singlechip RX, the 3 rd pin VIB of the isolation chip U1 is connected with the singlechip TX, the 4 th pin GND1 of the isolation chip U1 is connected with GND, the 5 th pin GND2 of the isolation chip U1 is connected with PGND, the isolation chip U1 is isolated between the 6 th pin VOB of the isolation chip U1 and the resistor R14, the 7 th pin VIA of the isolation chip U1 is connected with the 1 st pin of the communication chip U2, and the 8 th pin VDD2 of the isolation chip U1 is connected with 5V. One end of the resistor R16 is connected with a 3.3V power end, and the other end of the resistor R16 is connected with an RO pin of the communication chip U2; one end of the capacitor C2 is connected with the VCC end of the communication chip U2 and the 3.3V power end, and the other end of the capacitor C2 is grounded. The ADuM3201 isolation chip is adopted, so that the problems that the conversion speed of an optical coupler, the matching of current-limiting resistors, the baud rate of communication is difficult to reach more than 1M and the like can be solved.
Resistor R14 and resistor R15 establish ties and the VOB pin of public end connection isolation chip U1, and the control end of switch tube Q3 is connected to the other end of resistor R14, and the other end of resistor R15 is connected 3.3V power end. A first end of the switch tube Q3 is connected with the communication chip U2The second end of the switch tube Q3 is grounded; one end of the resistor R13 is connected with a 3.3V power end, and the other end of the resistor R13 is connected with a first end of the switching tube Q3. The switching tube Q3 may be a triode or a MOS tube, in this embodiment, the switching tube Q3 is an NPN triode, the base is used as the control terminal, the collector is used as the first terminal, and the emitter is used as the second terminal. The resistor R13, the resistor R14 and the Q3-NPN triode form a typical triode switch circuit which is used for automatic flow direction control.
The ADuM3201 isolation chip is a dual-channel digital isolator, and has enhanced system-level ESD reliability. The optocoupler circuit formed by LEDs (LIGHT EMITTING diodes) and photodiodes is not used, the signal data transmission rate is high, and the problems of uncertain current transmission ratio, nonlinear transfer function, influence of temperature and service life and the like of the optocoupler can be eliminated. And the physical isolation of the RS-485 bus signals achieves the purposes of reducing the common impedance coupling area and the mutual interference degree between nodes, and can prevent the comprehensive paralysis of the RS-485 bus caused by the faults of overlarge static induction voltage of the nodes, transient pulse strong voltage, differential short circuit of signal lines and the like.
485 Communication circuit still includes resistance R17, resistance R18 and resistance R19, and resistance R18, resistance R17 and resistance R19 establish ties in proper order, and the B pin of communication chip U2 is connected to the public end of resistance R18 and resistance R17, and the other end ground connection of resistance R18, the A pin of communication chip U2 is connected to the public end of resistance R17 and resistance R19, and the power end is connected to the other end of resistance R19, concretely 5V power end.
485 Communication circuit still includes voltage regulator tube D6, voltage regulator tube D7 and voltage regulator tube D8, voltage regulator tube D7, voltage regulator tube D6 and voltage regulator tube D8 establish ties in proper order, and the B pin of communication chip U2 is connected to the public end of voltage regulator tube D7 and voltage regulator tube D6, and the other end ground connection of voltage regulator tube D7, the A pin of communication chip U2 is connected to the public end of voltage regulator tube D6 and voltage regulator tube D8, and the AGND end is connected to the other end of voltage regulator tube D8. The specific types of the voltage stabilizing tube D6, the voltage stabilizing tube D7 and the voltage stabilizing tube D8 are not unique, and in this embodiment, the voltage stabilizing tube D6, the voltage stabilizing tube D7 and the voltage stabilizing tube D8 are all bidirectional voltage stabilizing tubes. The pins 2 and 3 of the communication chip U2 do not need to be controlled by an additional IO port, so that the resources used by the singlechip are reduced, and the flow direction is controlled automatically.
The working principle of the RS-485 communication interface device is as follows:
And (3) receiving: when no data is defaulted, the VOB pin of the isolation chip U1 is high level, the switch tube Q3 is conducted, and the communication chip U2 The pins are enabled at low level, the RO pins receive data enabling, at the moment, what data received from the AB port of the communication chip U2 is transmitted to the MCU through the RO channel, and the data receiving process is completed.
And (3) transmitting: when data is transmitted, the VOB pin of the isolation chip U1 has a pull-down level to indicate that the data is transmitted, the switching tube Q3 is cut off, and the DE pin of the communication chip U2 is enabled for high-level transmission. When the data '0' is sent, the data '0' is transmitted to A, B ports at this time because the DI pin of the communication chip U2 is connected to the ground, the A-B is <0, and the transmission of the data '0' is completed. When '1' is sent, the switch tube Q3 is turned on and enabled according to the RO pin, and at the moment, the A, B pin of the communication chip U2 is in a high-resistance state under the state of being still in the data transmission state, and the state at the moment pulls up A through the resistor R19 and the resistor R18 pulls down B to determine. At this time, A-B >0 transmits '1', and the high level transmission is completed.
The RS-485 communication interface device has the beneficial effects that: the power supply is completely isolated from the signal, and has very high electromagnetic interference (EMI) performance; the automatic flow direction control of the RS-485 signal is realized, and the receiving and transmitting directions are automatically switched; the signal data transmission rate is high; the industrial-level design has strong anti-interference capability, and meanwhile, a stronger RS-485 lightning protection design is adopted, so that the grounding end of the module is connected into the ground to have good anti-interference and lightning protection effects when the module is transported in a long distance in the field, and the RS-485 bus is safer.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (10)
1. A communication interface device, comprising:
The VOA pin of the isolation chip is used for being connected with the RX pin of the singlechip, and the VIB pin of the isolation chip is used for being connected with the TX pin of the singlechip;
The communication circuit comprises a communication chip and a switch circuit, wherein an RO pin of the communication chip is connected with a VIA pin of the isolation chip, and the communication chip The pin and the DE pin are connected with the switch circuit, and the switch circuit is connected with the VOB pin of the isolation chip;
The isolation chip outputs low level to the switch circuit when the singlechip sends data, and the switch circuit is cut off when receiving the low level, so that the communication chip receives and outputs the data sent by the singlechip through the isolation chip; when the single chip microcomputer does not send data, the isolation chip outputs high level to the switch circuit, and the switch circuit is conducted when receiving the high level, so that the communication chip transmits the received data to the single chip microcomputer through the isolation chip.
2. The communication interface device according to claim 1, wherein a GND1 pin of the isolation chip is connected to a GND terminal, a GND2 pin of the isolation chip is connected to a PGND terminal, and a ground is isolated between the GND terminal and the PGND terminal.
3. The communication interface device according to claim 1, wherein the switching circuit comprises a resistor R13, a resistor R14, a resistor R15, and a switching tube Q3, one end of the resistor R14 is connected to one end of the resistor R15 and the VOB pin of the isolation chip, the other end of the resistor R14 is connected to the control end of the switching tube Q3, the other end of the resistor R15 is connected to the power supply end, and the first end of the switching tube Q3 is connected to the communication chipThe second end of the switch tube Q3 is grounded; one end of the resistor R13 is connected with a power supply end, and the other end of the resistor R13 is connected with the first end of the switching tube Q3.
4. The communication interface device according to claim 1, wherein the communication circuit further comprises a resistor R16 and a capacitor C2, one end of the resistor R16 is connected to a power supply terminal, and the other end of the resistor R16 is connected to an RO pin of the communication chip; one end of the capacitor C2 is connected with the VCC end and the power end of the communication chip, and the other end of the capacitor C2 is grounded.
5. The communication interface device according to claim 1, wherein the communication circuit further comprises a resistor R17, a resistor R18 and a resistor R19, the resistor R18, the resistor R17 and the resistor R19 are sequentially connected in series, a common terminal of the resistor R18 and the resistor R17 is connected to a B pin of the communication chip, the other terminal of the resistor R18 is grounded, a common terminal of the resistor R17 and the resistor R19 is connected to an a pin of the communication chip, and the other terminal of the resistor R19 is connected to a power supply terminal.
6. The communication interface device according to claim 5, wherein the communication circuit further comprises a voltage stabilizing tube D6, a voltage stabilizing tube D7 and a voltage stabilizing tube D8, the voltage stabilizing tube D7, the voltage stabilizing tube D6 and the voltage stabilizing tube D8 are sequentially connected in series, a common end of the voltage stabilizing tube D7 and the voltage stabilizing tube D6 is connected with a B pin of the communication chip, the other end of the voltage stabilizing tube D7 is grounded, the common end of the voltage stabilizing tube D6 and the voltage stabilizing tube D8 is connected with an a pin of the communication chip, and the other end of the voltage stabilizing tube D8 is connected with an AGND end.
7. The communication interface device of claim 6, wherein the regulator D6, the regulator D7, and the regulator D8 are all bi-directional regulators.
8. The communication interface device of any one of claims 1-7, wherein the communication chip is a 485 communication chip.
9. The communication interface device of any one of claims 1-7, wherein the isolation chip is a dual channel digital isolator.
10. The communication interface device of claim 9, wherein the isolation chip is an ADuM3201 isolation chip.
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| CN202111010276.4A CN113849437B (en) | 2021-08-31 | 2021-08-31 | Communication interface device |
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| CN202111010276.4A CN113849437B (en) | 2021-08-31 | 2021-08-31 | Communication interface device |
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| CN113849437B true CN113849437B (en) | 2024-04-26 |
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| JP2007019648A (en) * | 2005-07-05 | 2007-01-25 | Seiko Epson Corp | Data transfer controller and electronic equipment |
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| CN208298176U (en) * | 2018-06-28 | 2018-12-28 | 河南思维轨道交通技术研究院有限公司 | A kind of multi-functional multi-interface communication board |
| CN109194322A (en) * | 2018-08-20 | 2019-01-11 | 华立科技股份有限公司 | RS485 high speed communication condenser type isolation circuit and its performance test methods |
| CN210092870U (en) * | 2018-08-20 | 2020-02-18 | 深圳市格瑞普智能电子有限公司 | Communication interface control circuit and communication equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3992442B2 (en) * | 2001-02-05 | 2007-10-17 | 株式会社日立製作所 | Interface device and interface system |
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|---|---|---|---|---|
| JP2007019648A (en) * | 2005-07-05 | 2007-01-25 | Seiko Epson Corp | Data transfer controller and electronic equipment |
| CN101763332A (en) * | 2010-02-24 | 2010-06-30 | 浙江中控技术股份有限公司 | Parallel communication bus interface |
| CN208298176U (en) * | 2018-06-28 | 2018-12-28 | 河南思维轨道交通技术研究院有限公司 | A kind of multi-functional multi-interface communication board |
| CN109194322A (en) * | 2018-08-20 | 2019-01-11 | 华立科技股份有限公司 | RS485 high speed communication condenser type isolation circuit and its performance test methods |
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| CN113849437A (en) | 2021-12-28 |
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