CN221010091U

CN221010091U - MOS tube redundant driving circuit

Info

Publication number: CN221010091U
Application number: CN202322878399.0U
Authority: CN
Inventors: 蔡云枝; 王海波; 赵晓佳
Original assignee: Taicang Haiyun Testing Co ltd; Taicang T&W Electronics Co Ltd; Shanghai Gongjin Communication Technology Co Ltd
Current assignee: Taicang Haiyun Testing Co ltd; Taicang T&W Electronics Co Ltd; Shanghai Gongjin Communication Technology Co Ltd
Priority date: 2023-10-25
Filing date: 2023-10-25
Publication date: 2024-05-24
Anticipated expiration: 2033-10-25

Abstract

The utility model relates to the field of MOS redundant driving circuits, in particular to a MOS tube redundant driving circuit, which comprises: MOS tube protection circuit, discrete drive circuit and redundant drive circuit; the MOS tube protection circuit comprises ferrite magnetic beads and a grid resistor which are sequentially connected in series with the grid electrode of the MOS tube, and a constant voltage diode connected in series between the source electrode and the grid electrode of the MOS tube; the utility model firstly effectively protects the gate source and the source drain of the MOS tube, and effectively reduces the damage probability of the MOS; based on the totem pole circuit structure, effective optimization and improvement are carried out on weak links of the totem pole circuit structure, a low-cost isolated gate driver is constructed by using discrete devices, the cost of a MOS (metal oxide semiconductor) tube redundant driving circuit is reduced, the system can be ensured to isolate faults under any single-point faults of MOS, and the normal power supply function of the system is ensured, so that the reliability is effectively ensured.

Description

MOS tube redundant driving circuit

Technical Field

The utility model relates to the field of MOS redundant driving circuits, in particular to a MOS tube redundant driving circuit.

Background

The MOS transistor (metal oxide semiconductor field effect transistor) has the most remarkable characteristic of good switching characteristics, so that the MOS transistor is widely applied to circuits requiring electronic switching, such as switching power supplies and motor driving, and lighting dimming.

In power and motor drive applications, the power MOS tube can realize corresponding energy conversion functions in different modulation modes, and a PWM modulation mode is generally used.

PWM (Pulse Width Modulation) control is a technique of modulating the width of a pulse, i.e. by modulating the width of a series of pulses, to equivalently obtain the desired waveform.

Consider a digital logic system with a microcontroller that can output a PWM signal of 0V to 5V on one of its I/O pins, which PWM would not be sufficient to fully turn on the power devices used in the power supply system, since their overdrive voltage would typically exceed the standard CMOS/TTL logic voltage.

The structure of the power MOS tube enables the grid electrode to form a nonlinear capacitor, the charging of the grid electrode capacitor enables the power device to be conducted and allows current to flow between the drain electrode and the source electrode pin of the power device, and the discharging enables the device to be turned off, so that the drain electrode and the source electrode pin can block large voltage; the minimum voltage when the gate capacitance is charged and the device can just turn on is the threshold voltage (Vth), and to use the IGBT/power MOS as a switch, a voltage substantially greater than Vth should be applied between the gate and source/emitter pins.

The structure of single MOS drive is as shown in FIG. 8, the PWM module of MCU adjusts the duty ratio to control the on-off of power MOS, to achieve the corresponding function, however the problem faced is: the dedicated gate driver is more fully functional but more expensive.

Disclosure of utility model

Aiming at the technical problems in the prior art, the utility model provides the MOS tube redundancy driving circuit for solving the problem of higher cost of the MOS tube redundancy driving circuit.

The technical scheme for solving the technical problems is as follows:

Provided is a MOS transistor redundant driving circuit, the circuit includes:

MOS tube protection circuit, discrete drive circuit and redundant drive circuit;

The MOS tube protection circuit comprises ferrite magnetic beads and a grid resistor which are sequentially connected in series with the grid electrode of the MOS tube, and a constant voltage diode connected in series between the source electrode and the grid electrode of the MOS tube;

The redundant driving circuit comprises a P-type MOS isolation type grid driver, an N-type MOS isolation type grid driver and two power MOS tubes, wherein the P-type MOS isolation type grid driver is connected with one power MOS tube in series, the N-type MOS isolation type grid driver is connected with the other power MOS tube in series, the P-type MOS isolation type grid driver and the N-type MOS isolation type grid driver are respectively connected with the PWM circuit in parallel, and the two power MOS tubes are indirectly loaded on the drain electrode of the power MOS tube.

Further, the MOS tube is an NMOS tube, and the discrete driving circuit comprises:

A PWM circuit;

a NAND gate logic circuit connected with the PWM circuit;

N-MOS transistor Q1, N-MOS transistor Q4 and N-MOS transistor Q5;

P-MOS transistor Q2, P-MOS transistor Q3; and

Resistor R1, resistor R2, resistor R3, resistor R4, resistor R5 and resistor R6;

The N-MOS transistor Q1 is connected with the source electrode of the P-MOS transistor Q2, the grid electrode is also connected, the resistor R1 is connected between the NAND gate logic circuit and the source electrode of the N-MOS transistor Q1 in series, the grid electrode of the P-MOS transistor Q3 is connected with the drain electrode of the N-MOS transistor Q1, the source electrode of the P-MOS transistor Q3 is connected with the high-end voltage Vh, the grid electrode of the P-MOS transistor Q4 is connected with the drain electrode of the P-MOS transistor Q2, the drain electrode of the P-MOS transistor Q4 is connected with the drain electrode of the P-MOS transistor Q3, the source electrode of the P-MOS transistor Q4 is grounded, the resistor R2 is grounded after being connected with the resistor R3 in series, the grid electrode of the N-MOS transistor Q1 is connected between the resistor R2 and the resistor R3, the grid electrode of the N-MOS transistor Q1 is connected with the drain electrode of the N-MOS transistor Q5, the source electrode of the N-MOS transistor Q5 is grounded, the resistor R6 is connected with the drain electrode of the resistor R5, and the resistor R5 is sequentially connected with the resistor R5 in series.

Further, the resistor R4 is connected in parallel with an accelerating capacitor.

Further, the MOS tube is a PMOS tube, and the discrete driving circuit comprises:

A PWM circuit;

a NAND gate logic circuit connected with the PWM circuit;

N-MOS transistor Q1 and N-MOS transistor Q4;

P-MOS transistor Q2, P-MOS transistor Q3 and P-MOS transistor Q5; and

The N-MOS transistor Q1 is connected with the source electrode of the P-MOS transistor Q2, the grid electrode is also connected, the resistor R1 is connected between the NAND gate logic circuit and the source electrode of the N-MOS transistor Q1 in series, the grid electrode of the P-MOS transistor Q3 is connected with the drain electrode of the N-MOS transistor Q1, the source electrode of the P-MOS transistor Q3 is connected with the high-end voltage Vh, the grid electrode of the N-MOS transistor Q4 is connected with the drain electrode of the P-MOS transistor Q2, the drain electrode of the N-MOS transistor Q4 is connected with the drain electrode of the P-MOS transistor Q3, the source electrode of the N-MOS transistor Q4 is grounded, the resistor R2 is connected with the resistor R3 in series and then grounded, the grid electrode of the N-MOS transistor Q1 is connected between the resistor R2 and the resistor R3, the grid electrode of the N-MOS transistor Q1 is connected with the drain electrode of the P-MOS transistor Q5, the grid electrode of the P-MOS transistor Q5 is connected with the high-end voltage Vh, the resistor R4 is connected with the grid electrode of the resistor R5, and the resistor R5 is connected with the resistor R5 in series in sequence, and the resistor R5 is connected with the resistor R5.

Further, the front end of the discrete driving circuit is additionally connected with a signal level transformer.

Further, the low-side voltage V1 does not exceed the high-side voltage Vh.

The beneficial effects of the utility model are as follows:

The utility model firstly effectively protects the gate source and the source drain of the MOS tube, and effectively reduces the damage probability of the MOS; based on the totem pole circuit structure, effective optimization and improvement are carried out on weak links of the totem pole circuit structure, a low-cost isolated gate driver is constructed by using discrete devices, the cost of a MOS (metal oxide semiconductor) tube redundant driving circuit is reduced, the system can be ensured to isolate faults under any single-point faults of MOS, and the normal power supply function of the system is ensured, so that the reliability is effectively ensured.

Drawings

Fig. 1 is a circuit diagram of a MOS transistor protection of the present utility model;

FIG. 2 is a diagram of a non-isolated drive circuit for NMOS according to the present utility model;

FIG. 3 is a diagram of a non-isolated drive circuit for PMOS of the present utility model;

FIG. 4 is a circuit diagram of an isolated PWM driving NMOS according to the present utility model;

FIG. 5 is a circuit diagram of an isolated PWM driving PMOS of the present utility model;

FIG. 6 is a schematic circuit diagram of a dual-ended redundant drive scheme of the present utility model;

FIG. 7 is a schematic diagram of a two-way high-low side redundant drive scheme of the present utility model;

FIG. 8 is a schematic diagram of a MOS driving circuit according to the present utility model;

Fig. 9 is a totem pole circuit diagram;

FIG. 10 is a diagram of a power MOS transistor overvoltage protection circuit;

FIG. 11 is a second power MOS transistor overvoltage protection circuit diagram;

fig. 12 is a third power MOS transistor overvoltage protection circuit diagram;

fig. 13 is a circuit diagram of noise reduction in a gate driving circuit using ferrite beads.

Detailed Description

The present utility model will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present utility model more apparent. Examples of the embodiments are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements throughout or elements having like or similar functionality. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the utility model. Furthermore, it should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the present utility model.

In the description of the present utility model, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present utility model can be understood by those of ordinary skill in the art according to the specific circumstances.

The following preferred embodiments are provided for the convenience of understanding the technical solution of the present utility model, in which related terms and circuits are described together:

the driving of the MOS tube plays a decisive role in the working effect, and a good MOS tube driving circuit has the following requirements:

1. The switching tube is switched on instantly, the driving circuit can provide enough charging current to enable the voltage between the grid and the source of the MOS tube to rise to a required value rapidly, and the switching tube can be switched on rapidly without high-frequency oscillation of rising edges;

2. The drive circuit can ensure that the voltage between the gate and the source of the MOS tube is kept stable and reliably conducted during the switch conduction period;

3. The switching-off instant driving circuit can provide a path with the lowest impedance as possible for the rapid discharge of the capacitor voltage between the grid and the source of the MOS tube, so that the switching tube can be switched off rapidly;

4. The driving circuit has simple and reliable structure and small loss.

The direct drive of power supply I C is the most common drive mode and is also the simplest drive mode.

In power supply design, engineers are usually faced with the problem of insufficient driving current of the control IC or excessive power consumption of the control IC due to gate driving loss, and to alleviate this problem, engineers usually use external drivers, and semiconductor manufacturers have existing MOS transistor integrated circuit driver solutions, which is not usually the lowest cost solution.

The driving of the MOS tube is to charge and discharge the grid capacitor. If the parasitic capacitance of the selected MOS transistor is relatively large, and the driving capability in the power supply I C is insufficient, the driving capability needs to be enhanced on the driving circuit, and a totem pole circuit is often used to increase the driving capability of the power supply IC.

The basic circuit of the totem pole is shown in fig. 9, the totem pole is a transistor which is respectively arranged on the upper side and the lower side, the upper pipe is NPN, the c pole is connected with a positive power supply, the lower pipe is PNP, and the c pole is connected with the negative end of the power supply. The two poles b are connected together, the input is connected, the e of the upper tube and the e of the lower tube are connected together, the output is connected, and the totem pole is used for matching voltage or improving the driving capability of an IO port.

The special gate driver is more fully functional but more expensive, and compared with the special gate driver IC, the BJT totem pole allows the MOS transistor to generate voltage drop, but the drain current can rise significantly. The current rise may cause excessive power consumption and may damage the MOS transistor. The parasitic bipolar transistor connected in parallel with the MOS transistor exists in the MOS, the amplitude of the MOS drain-source breakdown voltage is reduced along with the conduction of the internal parasitic bipolar transistor, and the conduction of the internal parasitic bipolar transistor leads to the continuous increase of drain current, so that the breakdown voltage is further reduced, and a positive feedback structure is formed. At this point, if the current cannot be limited from increasing further, the device will eventually self-destruct due to overheating.

Therefore, as shown in fig. 10, a simple overvoltage protection structure of the power MOS transistor can be adopted, and a reverse bias diode is connected in parallel beside the power MOS transistor, so that when the voltage of Vds becomes larger than the reverse breakdown voltage of diode D, the diode is reversely conducted, and current flows through the diode, thereby limiting the size of the power MOS transistor Vds and protecting the MOS transistor.

Alternatively, as shown in fig. 11, in addition, in an application where the driver is not close to the MOS transistor that needs to be driven, there will be a trace inductance between the output of the driver and the gate of the MOS transistor, which may cause ringing on the gate voltage of the MOS transistor, and if the peak voltage exceeds the maximum rated gate voltage of the MOS transistor, the MOS transistor may be damaged, thereby causing a fault, and this voltage may be clamped by adding a zener diode to the gate and source of the MOS transistor, as shown in fig. 12.

Ferrite beads are most useful in gate drive applications for reducing ringing and noise on the switching gate node, and resistors have traditionally been used to reduce such gate noise, but using resistors reduces the maximum drive current, slows the switching speed and increases the switching losses. Ferrite beads can be selected to remove noise without significantly reducing peak drive strength, so that the switching behavior of the power transistor is relatively unchanged, as shown with reference to fig. 13, the addition of ferrite beads can significantly reduce the amplitude of gate oscillations, use ferrite beads on the gates of the power switch to improve the reliability of the drive circuit, especially when switching noise field effect transistors, such as field effect transistors with fast rise times or low internal gate resistance, can be used in series with the gate resistance to obtain the greatest benefit, and should be as close as possible to the power MOS transistor.

There are several particular requirements for current MOS drives:

1. low pressure applications

When a 5V power supply is used, if a traditional totem pole structure is used, the voltage applied to gate is only 4.3V due to the voltage drop of about 0.7V of the triode be. At this time, a certain risk exists by selecting a MOS tube with a nominal gate voltage of 4.5V.

The same problem occurs where 3V or other low voltage power is used.

2. Wide voltage application

The input voltage is not a fixed value and may vary over time or other factors. This variation causes the driving voltage provided by the PWM circuit to the MOS transistor to be unstable. In order to ensure that the MOS transistors are safe under high gate voltage, a voltage stabilizing tube is arranged in many MOS transistors to forcibly limit the amplitude of the gate voltage. In this case, when the supplied driving voltage exceeds the voltage of the regulator tube, a large static power consumption is caused.

Meanwhile, if the gate voltage is simply reduced by using the principle of resistor voltage division, when the input voltage is higher, the MOS tube works well, and when the input voltage is reduced, the gate voltage is insufficient, so that the conduction is not thorough enough, and the power consumption is increased.

3. Dual voltage application

In some control circuits, the logic portion uses a typical 5V or 3.3V digital voltage, while the power portion uses a voltage of 12V or even higher. The two voltages are typically connected in a common manner.

This puts a requirement that a circuit is required to be used to enable the low voltage side to effectively control the high voltage side MOS transistor, and the high voltage side MOS transistor also faces the problems of Vbe and wide voltage application.

In these three cases, the totem pole structure fails to meet the output requirements, and many off-the-shelf MOS drives I C do not appear to contain gate voltage limiting structures.

In particular, under some overvoltage, overcurrent and overload conditions, a single power MOS is easily damaged, thus causing failure of the whole drive plate and even risk of fire.

For this reason, redundant low-cost driving circuits must be considered to effectively avoid the negative effects of single-point failure of the MOS, so-called redundancy in engineering, which means that the critical components or functions of a system are intentionally repeated in order to improve the reliability of the system.

In view of the above analysis, the present utility model proposes a relatively universal simple MOS transistor redundant drive circuit to meet the above needs.

Firstly, considering protection of MOS, a protection circuit shown in FIG. 1 can be adopted for MOS tube, a discrete driving circuit based on totem pole structure improvement is constructed, a circuit diagram is shown in FIG. 2, and a simple analysis is performed for NMOS driving circuit:

Vl and Vh are low-side and high-side power supplies, respectively, and both voltages may be the same, but Vl should not exceed Vh.

The N-MOS tube Q1 and the P-MOS tube Q2 form a reverse totem pole for realizing isolation, and meanwhile, the two driving tubes P-MOS tube Q3 and N-MOS tube Q4 are ensured not to be conducted simultaneously.

Resistor R2 and resistor R3 provide PWM voltage references that can be varied to allow the circuit to operate in a position where the PWM signal waveform is relatively steep.

The P-MOS transistor Q3 and the N-MOS transistor Q4 are used to provide a driving current, and when they are turned on, the voltage drop of the P-MOS transistor Q3 and the N-MOS transistor Q4 with respect to Vh and GND is only one Vce at the minimum, and this voltage drop is usually only about 0.3V and is substantially lower than 0.7V Vce.

The resistor R5 and the resistor R6 are feedback resistors and are used for sampling gate voltage, and the sampled voltage generates strong negative feedback to the bases of the N-MOS tube Q1 and the P-MOS tube Q2 through the N-MOS tube Q5, so that the gate voltage is limited to a limited value. This value can be adjusted by means of a resistor R5 and a resistor R6.

Finally, resistor R1 provides base current limits for P-MOS transistor Q3 and N-MOS transistor Q4, and resistor R4 provides gate current limits for MOS transistors, i.e., I ce limits for P-MOS transistor Q3 and N-MOS transistor Q4. When necessary, the accelerating capacitor can be connected in parallel with the resistor R4, and when the accelerating capacitor is connected in parallel with the resistor R4, the accelerating capacitor has the advantages of improving the response speed of the circuit, preventing voltage mutation and storing charge, and changing the characteristics and performance of the circuit through the parallel connection of the accelerating capacitor and the resistor R4, so that the circuit is more stable and efficient.

As shown in fig. 3, it is understood that similar circuits may be employed for PMOS transistors.

For isolation applications, a signal level transformer may be added to the front end of the circuit.

Why isolation is required, the answer is that isolation is related to reliable protection. Electrical isolation is a circuit design technique that allows two circuits to communicate, eliminating any unwanted direct current flowing between them.

Isolation is commonly used to:

1. Protecting operators and the circuit from high voltages;

2. preventing ground potential differences between the communication subsystems;

3. Improve noise immunity.

The isolator may magnetically or capacitively couple data to the other end of the isolation grating using a transformer or capacitor, and the optocoupler is light from an LED. This makes the static current, data transmission delay, CMTI common mode transient immunity and other performance of the optocoupler scheme poor. The magnetic separator is formed by passing a transformer current pulse through one coil to form a small local magnetic field, thereby generating an induced current in the other coil. Here we use a pulse transformer for isolation.

A pulse transformer is driven by a PWM signal. The transformer secondary winding provides the input signal to the buffer. The buffer transformer outputs impedance to provide large current pulse, so as to charge and discharge MOS tube connected with output end. The circuit is extremely efficient because it will drive the MOS transistor gate negative and can provide fast switching, thereby minimizing switching losses.

The improved discrete device driver circuit provides the following characteristics:

1. driving a high-end MOS tube by using low-end voltage and PWM;

2. driving the MOS tube with high gate voltage requirement by using a PWM signal with small amplitude;

3. Peak limitation of gate voltage;

4. Input and output current limits;

5. by using a suitable resistor, very low power consumption can be achieved;

6. Compared with the existing MOS transistor driving in an integrated circuit mode, the discrete device can greatly save the circuit cost;

7. the application of PWM isolation can be realized by adopting a preposed signal transformer;

8. The switching losses are reduced.

With redundant designs, under some overvoltage, overcurrent and overload conditions, a single power MOS is easily damaged, thus causing failure of the entire drive board and even risk of fire. For this reason, redundant low cost drive lines must be considered to effectively avoid the negative effects of single point failure of the MOS.

As shown in fig. 6, by redundant driving and power MOS, redundancy of driving can be achieved, effectively isolating faults of MOS failure. In this design, the drive lines are completely isolated, i.e. the primary and secondary sides of the drive are isolated, and the drive channels 1 and 2 are isolated. Even if the MOS fails, such as any MOS short, the high voltage of the system cannot be conducted to the low voltage side, thereby achieving fault isolation.

The design characteristics of the double-end redundant driving scheme are as follows:

1. The isolation type PMOS and NMOS drivers are used for controlling the on-off of the high end and the low end respectively, as shown in FIG. 6, the isolation type MOS gate driving circuits shown in the previous FIGS. 4 and 5 are used as the high end and low end gate drivers;

2. PWM input signals can pass through an RC filter network, so that input interference signals are avoided;

3. Comparing fig. 4 and fig. 5, it is noted that since the phases of the PWM signals connected to the transformer are opposite, the same PWM signal output by the MCU can be used to control the on-off of the PMOS and the NMOS simultaneously, i.e. the PMOS and the NMOS are synchronously on-off.

The safety requirement is that the system does not generate safety risk under a single fault condition, and analysis can show that under the failure conditions of DS, GD, GS, GDS short circuit and the like of a single MOS, the normal function of the system can be ensured, and the expansion of fault points is blocked. However, the disadvantage is that under the condition of GS and DS open circuit failure of a single MOS, the power loop is disconnected, the system can be reliably turned off, but the power supply function is abnormal.

Under the condition that the GS and DS of the MOS fail to open, the two-way redundancy driving scheme has abnormal system functions, and the two-way redundancy driving scheme needs to be further improved, as shown in fig. 7, the MOS and the driving circuit are doubled, and the high-end and low-end two-way MOS are respectively connected in parallel, so that the normal system functions under the condition that the GS and DS of the MOS fail to open can be ensured.

For simplicity and clarity of the device in fig. 7, the reverse diode, zener diode, gate resistor, and magnetic beads added to the MOS transistor are not shown.

The comparative analysis of the redundant drive scheme is as follows:

In the high-low double-tube redundant driving scheme, under the failure of DS, GD, GS, GDS short circuit and the like of a single MOS, fault points are isolated, and the system functions normally; under the failure of DS, GS open circuit and the like of a single MOS, a fault point is isolated, and the system is reliably turned off.

In the two-way high-low double-tube redundant driving scheme, under the condition that DS, GD, GS, GDS of a single MOS is short-circuited and DS and GS of the single MOS are open and invalid, the fault is isolated and the system functions are normal.

The two MOS redundant driving circuits can effectively avoid the influence caused by MOS single-point faults, under the conditions of DS, GD, GS, GDS short circuits and the like of the MOS, the upper and lower double-tube redundant driving can ensure the normal function of the system, block the expansion of fault points, and simultaneously, the more perfect two-circuit upper and lower double-tube redundant driving can ensure the isolation of faults and the normal function of the system under any single-point faults of the MOS.

The foregoing description of the preferred embodiments of the utility model is not intended to limit the utility model, but rather to enable any modification, equivalent replacement, improvement or the like to be made within the spirit and principles of the utility model.

Claims

1. A MOS transistor redundant drive circuit, the circuit comprising:

2. The MOS transistor redundant drive circuit of claim 1, wherein the MOS transistor is an NMOS transistor, the discrete drive circuit comprising:

A PWM circuit;

a NAND gate logic circuit connected with the PWM circuit;

N-MOS transistor Q1, N-MOS transistor Q4 and N-MOS transistor Q5;

P-MOS transistor Q2, P-MOS transistor Q3; and

3. The MOS transistor redundant drive circuit of claim 1, wherein the MOS transistor is a PMOS transistor, the discrete drive circuit comprising:

A PWM circuit;

a NAND gate logic circuit connected with the PWM circuit;

N-MOS transistor Q1 and N-MOS transistor Q4;

P-MOS transistor Q2, P-MOS transistor Q3 and P-MOS transistor Q5; and

4. A MOS transistor redundant drive circuit according to claim 2 or 3 wherein said resistor R4 is connected in parallel with an accelerating capacitor.

5. A MOS transistor redundant drive circuit according to claim 2 or 3 wherein a signal level transformer is added to the front end of the discrete drive circuit.

6. A MOS transistor redundant drive circuit according to claim 2 or 3, wherein the low-side voltage V1 does not exceed the high-side voltage Vh.