CN220985700U

CN220985700U - Multi-master concurrent communication network system for converting serial port into LoRa

Info

Publication number: CN220985700U
Application number: CN202322636087.9U
Authority: CN
Inventors: 张林兵; 徐武剑; 罗玲
Original assignee: Wuhan Mobile Star Technology Co ltd
Current assignee: Wuhan Mobile Star Technology Co ltd
Priority date: 2023-09-26
Filing date: 2023-09-26
Publication date: 2024-05-17
Anticipated expiration: 2033-09-26

Abstract

The utility model provides a serial port-to-LoRa multi-master concurrent communication network system, which comprises a plurality of industrial site serial port devices and corresponding wireless communication devices, wherein each wireless communication device comprises an interface daughter board capable of being optionally provided with a communication interface and a mother board for providing a LoRa wireless channel, the interface daughter board is optionally provided with a plurality of interface circuits and interface protection circuits, and the mother board is provided with the LoRa interface circuits; each industrial field serial port device is connected with an interface circuit and an interface protection circuit of the corresponding wireless communication device through an interface connection line, and the two industrial field serial port devices are communicated through the corresponding wireless communication devices through LoRa wireless channels. The utility model adopts the sub-mother board structure, and a user can flexibly adapt to the sub-board of the equipment according to different interface requirements of the field equipment so as to realize the interface compatibility of the industrial field equipment, and the utility model utilizes the LoRa wireless channel to communicate, thus being capable of realizing multi-master concurrent communication compared with the existing wired communication.

Description

Multi-master concurrent communication network system for converting serial port into LoRa

Technical Field

The utility model relates to the field of industrial field equipment communication, in particular to a serial port-to-LoRa multi-master concurrent communication network system.

Background

Various instruments, sensors, industrial control stations and other devices with RS232, RS422 and RS485 interfaces can be seen at any place, and certain limitations exist in networking communication of the industrial field devices: RS232 and RS422 only support two devices to perform point-to-point communication, and cannot construct a many-to-many communication network; RS485 allows multiple devices to build a many-to-many communication network, but due to the wired communication mode, only a master-multiple-slave mode can be realized, i.e. only a single device is allowed to transmit data at the same time in the network system, and other devices must be in a receiving or silence (standby) state.

The point-to-point communication system only supports the intercommunication of two devices, does not have the function of constructing a multi-device intercommunication network system, and has extremely low capacity of networking nodes.

Besides not supporting concurrent communication, a master multi-slave network system has the following obvious defects: the network system is fragile, and the whole network is crashed when the host computer fails; the network dilatability is poor, and the system dilatation can obviously cause network communication delay; the communication efficiency of the slave computers is low, and the communication between the slave computers in the single master network is required to be transferred through the master computer, so that the communication efficiency is low; the construction process of the network is complex, and the user needs to strictly limit the roles and communication mechanisms of each network device when networking in an industrial field; etc.

Disclosure of Invention

The utility model provides a serial port-to-LoRa multi-master concurrent communication network system, which aims at the technical problems in the prior art and comprises a plurality of industrial field serial port devices and wireless communication devices configured for each industrial field serial port device, wherein each wireless communication device comprises an interface daughter board which can be optionally matched with an industrial field communication interface and a mother board which can provide a LoRa wireless channel, the interface daughter board is optionally provided with various interface circuits and interface protection circuits, the mother board is provided with a LoRa interface circuit, the interface daughter board is connected with a mother board connecting groove of the mother board through a daughter board connecting card through a circuit, and the LoRa interface circuit of the mother board is connected with a LoRa antenna;

Each industrial field serial port device is connected with an interface circuit and an interface protection circuit of the corresponding wireless communication device through an interface connection line, and the two industrial field serial port devices are communicated through the corresponding wireless communication devices through LoRa wireless channels.

On the basis of the technical scheme, the utility model can also make the following improvements.

Optionally, the multiple interface circuits and interface protection circuits of the optional layout in the wireless communication device include an RS232 interface circuit and a first interface protection circuit, an RS422/RS485 interface circuit and a second interface protection circuit.

Optionally, the RS232 interface circuit includes an RS232 interface chip, a model of the RS232 interface chip is SP3243EEA, a pin 1 of the RS232 interface chip is connected to a pin 2 through a capacitor C46, a pin 3 is grounded through a capacitor C50, a pin 6 and a pin 9 are connected to corresponding first interface protection circuits, a pin 14 is a ttl_tx pin, responsible for sending signals outwards, a pin 17 is a ttl_rx pin, responsible for receiving signals, the ttl_tx pin and the ttl_rx pin are connected to a daughter board connection card, a pin 22 and a pin 23 are both grounded, a pin 24 is connected to a pin 28 through a capacitor C47, a pin 25 is grounded, a pin 26 is connected to VCC and is grounded through a capacitor C48, and a pin 27 is grounded through a capacitor C49.

Optionally, the first interface protection circuit includes a first fuse FR9, a second fuse FR10, a first thyristor T4, a second thyristor T5, and a third thyristor T6, where one end of the first fuse is connected to a pin 9 of the RS232 interface chip, the other end is used as an RS232 TX pin and connected to a transmitting pin of the RS232 interface chip, one end of the second fuse is connected to a pin 6 of the RS232 chip, the other end is used as an RS232 RX pin and connected to a receiving pin of the RS232 interface circuit, a pin 1 of the first thyristor is connected to a pin 1 of the third thyristor, a pin 2 of the first thyristor is connected to a pin 1 of the second thyristor, a pin 2 of the second thyristor is connected to a pin 2 of the third thyristor, and both a pin 2 of the second thyristor and a pin 2 of the third thyristor are grounded.

Optionally, the RS422/RS485 interface circuit includes an RS422/RS485 interface chip, the model of the RS422/RS485 interface chip is MAX13487EESA +, the pin 1 of the RS422/RS485 interface chip is used as a ttl_rx pin, and is responsible for receiving signals, the pin 1 is connected to VCC through a resistor R27, the pin 2 and the pin 3 are connected to VCC through a resistor R26, the pin 4 is used as a ttl_tx pin, and is responsible for sending signals outwards, the pin 5 is grounded, the pin 6 is respectively connected to VCC through a resistor R22 and grounded through a capacitor C51, the pin 7 is respectively connected to ground through a resistor R23 and a capacitor C52, the pin 8 is grounded through a capacitor C53, and the pin 6 and the pin 7 are both connected to the second interface protection circuit.

Optionally, the second interface protection circuit includes a third fuse FR7, a fourth fuse FR8, a fourth thyristor T7, a fifth thyristor T8 and a sixth thyristor T9, one end of the third fuse FR7 is connected to a pin 6 of the RS422/RS485 interface chip, the other end is connected to a positive pin of the RS422/RS485 interface circuit, one end of the fourth fuse FR8 is connected to a pin 7 of the RS422/RS485 interface chip, the other end is connected to a negative pin of the RS422/RS485 interface circuit, a fourth pin 1 of the fourth via-exhibition hall T7 is connected to a pin 1 of the sixth thyristor T8, a pin2 of the fourth thyristor T7 is connected to a pin 1 of the fifth thyristor T8, a pin2 of the fifth thyristor T8 is connected to a pin2 of the sixth thyristor T9, and both the pin2 of the fifth thyristor T8 and the pin2 of the sixth thyristor T9 are grounded.

Optionally, the LoRa interface circuit includes the LoRa chip, the model of LoRa chip is LSD4RF, the ANT pin of LoRa chip is connected one end of resistance R1 to and is grounded through electric capacity C2, the LoRa antenna interface is connected to the other end of resistance R1 to and is grounded through electric capacity C1, the TX pin is ttl_tx, is responsible for sending the signal outwards, and the RX pin is ttl_rx, is responsible for receiving the signal, and ttl_tx pin and ttl_rx pin are connected to the corresponding pin of motherboard spread groove.

Aiming at the networking limitation of industrial field devices, the serial port-to-LoRa multi-master concurrent communication network system provided by the utility model selects the LoRa wireless channel with excellent performance as a networking link and adopts a self-defined communication protocol, can support multi-node networking, can realize multi-master concurrent communication, and can construct a more flexible, efficient and stable communication network.

Drawings

Fig. 1 is a schematic structural diagram of a serial port to LoRa multi-master concurrent communication network system provided by the present utility model;

FIG. 2 is a pin definition diagram of a mother-son card docking slot;

FIG. 3 is a schematic diagram of an interface and protection circuit of an RS232 interface sub-board

Fig. 4 is a schematic structural diagram of interfaces and protection circuits of RS422 and RS485 interface sub-boards;

fig. 5 is a schematic structural diagram of an interface circuit of the LoRa interface motherboard.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present utility model more apparent, the technical solutions of the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model, and it is apparent that the described embodiments are some embodiments of the present utility model, but not all embodiments of the present utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model. In addition, the technical features of each embodiment or the single embodiment provided by the utility model can be combined with each other at will to form a feasible technical scheme, and the combination is not limited by the sequence of steps and/or the structural composition mode, but is necessarily based on the fact that a person of ordinary skill in the art can realize the combination, and when the technical scheme is contradictory or can not realize, the combination of the technical scheme is not considered to exist and is not within the protection scope of the utility model claimed.

Fig. 1 is a schematic diagram of a serial port-to-LoRa multi-master concurrent communication network system provided by the utility model, which comprises a plurality of industrial field serial port devices and wireless communication devices configured for each industrial field serial port device, wherein each wireless communication device comprises an interface daughter board capable of optionally matching with an industrial field communication interface and a motherboard for providing a LoRa wireless channel, the interface daughter board is optionally provided with various interface circuits and interface protection circuits, the motherboard is provided with a LoRa interface circuit, the interface daughter board is connected with a motherboard connecting groove of the motherboard through a daughter board connecting card through a circuit, and the LoRa interface circuit of the motherboard is connected with a LoRa antenna.

The utility model is based on the LoRa wireless technology, and can be flexibly adapted to wireless communication equipment from serial ports with multi-master concurrent communication capability to LoRa in industrial sites. The industrial field device which can only perform point-to-point communication can realize the application of many-to-many communication by performing signal conversion through the wireless communication device. The industrial field device which can only communicate with one master and multiple slaves can be subjected to signal conversion through the wireless communication device, and the multi-master concurrent communication can be realized. The wireless channel is adopted, so that networking is very convenient, networking difficulty of an industrial field is greatly reduced, concurrent communication of multiple devices is supported, and networking robustness, flexibility and communication efficiency of the industrial field are obviously improved.

Referring to fig. 2, the connection relationship between a daughter board connection card and a motherboard connection slot is shown, wherein the daughter board connection card is connected with the motherboard connection slot through corresponding pins, specifically, the daughter board connection card includes a VCC pin, a GND pin, a ttl_rx pin, and a ttl_tx pin, which are respectively connected with the VCC pin, the GND pin, the ttl_rx pin, and the ttl_tx pin of the motherboard connection slot.

The interface sub-board comprises a plurality of interface circuits and interface protection circuits which can be matched and laid out, wherein the interface circuits and the interface protection circuits comprise an RS232 interface circuit, a first interface protection circuit, an RS422/RS485 interface circuit and a second interface protection circuit.

It can be understood that, for different serial devices in the industrial field, an interface circuit sub-board is optionally matched, and in order to increase the adaptability of the network device relative to the industrial field, the circuit of the network device is simultaneously provided with a plurality of interface circuits and matched with corresponding interface protection circuits, so as to support the selection and matching of different users. The industrial field serial port equipment mainly comprises RS232 serial port equipment and RS422/RS485 serial port equipment. Therefore, the RS232 interface circuit, the first interface protection circuit, the RS422/RS485 interface circuit and the second interface protection circuit are adapted on the interface daughter board.

The utility model adopts a sub-mother board structure, and a user can flexibly adapt to the sub-board of the equipment according to different interface requirements of equipment such as a field instrument and the like, thereby realizing the interface compatibility of industrial field equipment.

Referring to fig. 3, the RS232 interface circuit includes an RS232 interface chip, the model of the RS232 interface chip is SP3243EEA, pin 1 of the RS232 interface chip is connected to pin 2 through capacitor C46, pin 3 is grounded through capacitor C50, pin 6 and pin 9 are connected to corresponding first interface protection circuits, pin 14 is a ttl_tx pin responsible for transmitting signals outwards, pin 17 is a ttl_rx pin responsible for receiving signals, the ttl_tx pin and the ttl_rx pin are connected to a daughter board connection card, pin 22 and pin 23 are both grounded, pin 24 is connected to pin 28 through capacitor C47, pin 25 is grounded, pin 26 is connected to VCC and grounded through capacitor C48, and pin 27 is grounded through capacitor C49.

The first interface protection circuit comprises a first fuse FR9, a second fuse FR10, a first thyristor T4, a second thyristor T5 and a third thyristor T6, one end of the first fuse is connected with a pin 9 of the RS232 interface chip, the other end of the first fuse is used as an RS232_TX pin and connected with a sending pin of the RS232 interface chip, one end of the second fuse is connected with a pin 6 of the RS232 chip, the other end of the second fuse is used as an RS232_RX pin and connected with a receiving pin of the RS232 interface circuit, a pin 1 of the first thyristor is connected with a pin 1 of the third thyristor, a pin 2 of the first thyristor is connected with a pin 1 of the second thyristor, a pin 2 of the second thyristor is connected with a pin 2 of the second thyristor, and both the pin 2 of the second thyristor and the pin 2 of the third thyristor are grounded.

Referring to fig. 4, the RS422/RS485 interface circuit includes an RS422/RS485 interface chip, the model of the RS422/RS485 interface chip is MAX13487EESA +, the pin 1 of the RS422/RS485 interface chip is used as a ttl_rx pin and is responsible for receiving signals, the pin 1 is connected to VCC through a resistor R27, the pin 2 and the pin 3 are connected to VCC through a resistor R26, the pin 4 is used as a ttl_tx pin and is responsible for sending signals outwards, the pin 5 is grounded, the pin 6 is respectively connected to VCC through a resistor R22 and is grounded through a capacitor C51, the pin 7 is respectively connected to ground through a resistor R23 and a capacitor C52, the pin 8 is grounded through a capacitor C53, and the pin 6 and the pin 7 are also both connected to the second interface protection circuit.

The second interface protection circuit comprises a third fuse FR7, a fourth fuse FR8, a fourth thyristor T7, a fifth thyristor T8 and a sixth thyristor T9, one end of the third fuse FR7 is connected with a pin 6 of an RS422/RS485 interface chip, the other end of the third fuse FR7 is connected with a positive pin of the RS422/RS485 interface circuit, one end of the fourth fuse FR8 is connected with a pin 7 of the RS422/RS485 interface chip, the other end of the fourth fuse FR8 is connected with a negative pin of the RS422/RS485 interface circuit, a fourth pin 1 of the fourth thyristor T7 is connected with a pin 1 of the sixth thyristor T8, a pin 2 of the fourth thyristor T7 is connected with a pin 2 of the fifth thyristor T8, and both the pin 2 of the fifth thyristor T8 and the pin 2 of the sixth thyristor T9 are grounded.

Referring to fig. 5, the LoRa interface circuit includes a LoRa chip, the type of the LoRa chip is LSD4RF, the ANT pin of the LoRa chip is connected to one end of a resistor R1 and is grounded through a capacitor C2, the other end of the resistor R1 is connected to the LoRa antenna interface and is grounded through the capacitor C1, the TX pin is ttl_tx, responsible for transmitting signals outwards, the RX pin is ttl_rx, responsible for receiving signals, and the ttl_tx pin and the ttl_rx pin are connected to corresponding pins of the motherboard connecting slot.

The multi-master concurrency communication network system for converting serial ports into LoRa, which is provided by the utility model, supports multi-node networking based on the LoRa wireless technology and can realize multi-master concurrency communication, wherein wireless communication equipment selects a LoRa channel with excellent performance as a networking link, adopts a self-defined communication protocol, adopts a wireless channel to carry out networking construction, can support multi-node networking and multi-master concurrency communication, and can be a communication network with more flexible components, high efficiency and robustness.

In the foregoing embodiments, the descriptions of the embodiments are focused on, and for those portions of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments.

While preferred embodiments of the present utility model have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the utility model.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present utility model without departing from the spirit or scope of the utility model. Thus, it is intended that the present utility model also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. The multi-master concurrent communication network system for converting serial ports into LoRa is characterized by comprising a plurality of industrial field serial port devices and wireless communication devices configured for each industrial field serial port device, wherein each wireless communication device comprises an interface daughter board capable of being optionally matched with an industrial field communication interface and a mother board for providing a LoRa wireless channel, the interface daughter board is optionally matched with a plurality of interface circuits and interface protection circuits, the mother board is provided with a LoRa interface circuit, the interface daughter board is connected with a mother board connecting groove of the mother board through a daughter board connecting card through a circuit, and the LoRa interface circuit of the mother board is connected with a LoRa antenna;

2. The communication network system of claim 1, wherein the plurality of interface circuits and interface protection circuits of the wireless communication device that are optionally configured include an RS232 interface circuit and a first interface protection circuit, an RS422/RS485 interface circuit, and a second interface protection circuit.

3. The communication network system according to claim 2, wherein the RS232 interface circuit includes an RS232 interface chip, the type of the RS232 interface chip is SP3243EEA, the pin 1 of the RS232 interface chip is connected to the pin 2 through the capacitor C46, the pin 3 is grounded through the capacitor C50, the pins 6 and 9 are connected to the corresponding first interface protection circuit, the pin 14 is a ttl_tx pin responsible for transmitting signals to the outside, the pin 17 is a ttl_rx pin responsible for receiving signals, the ttl_tx pin and the ttl_rx pin are connected to the daughter board connection card, the pins 22 and 23 are both grounded, the pin 24 is connected to the pin 28 through the capacitor C47, the pin 25 is grounded, the pin 26 is connected to VCC and is grounded through the capacitor C48, and the pin 27 is grounded through the capacitor C49.

4. A communication network system according to claim 3, wherein the first interface protection circuit comprises a first fuse FR9, a second fuse FR10, a first thyristor T4, a second thyristor T5 and a third thyristor T6, one end of the first fuse is connected to a pin 9 of the RS232 interface chip, the other end is used as an RS232 TX pin and connected to a transmitting pin of the RS232 interface chip, one end of the second fuse is connected to a pin 6 of the RS232 interface chip, the other end is used as an RS232 RX pin and connected to a receiving pin of the RS232 interface circuit, a pin 1 of the first thyristor is connected to a pin 1 of the third thyristor, a pin 2 of the first thyristor is connected to a pin 1 of the second thyristor, a pin 2 of the second thyristor is connected to a pin 2 of the third thyristor, and both a pin 2 of the second thyristor and a pin 2 of the third thyristor are grounded.

5. The communication network system according to claim 2, wherein the RS422/RS485 interface circuit comprises an RS422/RS485 interface chip, the model of the RS422/RS485 interface chip is MAX13487EESA +, the pin1 of the RS422/RS485 interface chip is used as a ttl_rx pin, responsible for receiving signals, and the pin1 is connected to VCC through a resistor R27, the pin2 and the pin3 are connected to VCC through a resistor R26, the pin 4 is used as a ttl_tx pin, responsible for sending signals outwards, the pin 5 is grounded, the pin 6 is grounded through a resistor R22 to VCC and through a capacitor C51, respectively, the pin 7 is grounded through a resistor R23 and through a capacitor C52, the pin 8 is grounded through a capacitor C53, and both the pin 6 and the pin 7 are also connected to the second interface protection circuit.

6. The communication network system according to claim 5, wherein the second interface protection circuit comprises a third fuse FR7, a fourth fuse FR8, a fourth thyristor T7, a fifth thyristor T8 and a sixth thyristor T9, one end of the third fuse FR7 is connected to the pin 6 of the RS422/RS485 interface chip, the other end is connected to the positive pin of the RS422/RS485 interface circuit, one end of the fourth fuse FR8 is connected to the pin 7 of the RS422/RS485 interface chip, the other end is connected to the negative pin of the RS422/RS485 interface circuit, the pin 1 of the fourth via-exhibition hall T7 is connected to the pin 1 of the sixth thyristor T8, the pin 2 of the fourth thyristor T7 is connected to the pin 1 of the fifth thyristor T8, the pin 2 of the fifth thyristor T8 is connected to the pin 2 of the sixth thyristor T9, and both the pin 2 of the fifth thyristor T8 and the pin 2 of the sixth thyristor T9 are grounded.

7. The communication network system of claim 1, wherein the LoRa interface circuit comprises a LoRa chip, the LoRa chip is of the type LSD4RF, the ANT pin of the LoRa chip is connected to one end of a resistor R1 and is grounded via a capacitor C2, the other end of the resistor R1 is connected to the LoRa antenna interface and is grounded via a capacitor C1, the TX pin is ttl_tx and is responsible for transmitting signals outwards, the RX pin is ttl_rx and is responsible for receiving signals, and the ttl_tx pin and the ttl_rx pin are connected to corresponding pins of a motherboard connection slot.