CN220964852U - Drive control signal holding circuit, BMS and battery pack - Google Patents
Drive control signal holding circuit, BMS and battery pack Download PDFInfo
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- CN220964852U CN220964852U CN202322545524.6U CN202322545524U CN220964852U CN 220964852 U CN220964852 U CN 220964852U CN 202322545524 U CN202322545524 U CN 202322545524U CN 220964852 U CN220964852 U CN 220964852U
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- 230000000694 effects Effects 0.000 description 12
- 230000008901 benefit Effects 0.000 description 5
- 230000003111 delayed effect Effects 0.000 description 5
- 230000000670 limiting effect Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000010485 coping Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
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Abstract
The utility model provides a drive control signal holding circuit, a BMS and a battery pack, wherein the drive control signal holding circuit is arranged between an MCU and a load switch and comprises a power circuit connected with a power supply, an MOS tube is arranged on the power circuit, a charge-discharge circuit is arranged on the power circuit, and two low-level output ends of the MCU are respectively connected with the power circuit in parallel through a logic circuit; the charging and discharging circuit is provided with a first triode, the high-level output end of the MCU is connected with the base electrode of the first triode, and when the first triode is conducted, the power supply circuit can charge the charging and discharging circuit; when the high-level output end and the two low-level output ends both output low-level signals, the charge and discharge circuit can discharge to the grid electrode of the MOS tube, so that the holding time of the driving control signals is prolonged. The driving control signal holding circuit can prolong the on time of the load switch when the MCU fails, provides response time for the processing of a driver, and has a simple scheme and is easy to implement.
Description
Technical Field
The utility model relates to the technical field of power batteries, in particular to a drive control signal holding circuit. Meanwhile, the utility model also relates to the BMS and the battery pack.
Background
In the requirements of automobiles for functional safety, the requirements of the contactor for maintaining the functions are increasing. Load switches, such as contactors or relays, can control the charge and discharge of the battery packs in the new energy automobile. Taking the contactor as an example, when the contactor is closed, the battery pack can discharge outwards and can charge the battery pack. When the contactor is disconnected, the battery pack cannot be discharged and charged.
In the normal running process of the vehicle, a main control chip of a BMS (battery management system) or an HVC (high voltage controller) fails, and the failure of the contactor can lead to immediate power-down of the vehicle, so that immediate power-down is extremely dangerous in running.
The holding function of the contactor means that when the BMS or the HVC fails due to the main control chip, the contactor is not opened but is maintained in a closed state for a period of time, giving the driver an operation time to cope with the loss of power.
Currently, the holding function in the contactor is mostly implemented by a latch matched with a system base chip, and the most important function is the requirement of realizing the holding time of the contactor, which is generally 3S. This scheme may set a delayed release by between FS0B and FS1B of the system base chip, with FS1B being delayed by a maximum of 3 seconds release. Such a3 second delayed state switch may be used for the purpose of achieving a 3S hold of the contactor. This scheme relies on the chip level, requiring a specific chip to support. But the cost of the chip is better, which is unfavorable for the reduction of the production cost.
Disclosure of utility model
In view of the above, the present utility model aims to propose a drive control signal holding circuit to lengthen the holding time of a load switch drive control signal to give a driver coping time when an MCU fails.
In order to achieve the above purpose, the technical scheme of the utility model is realized as follows:
The driving control signal holding circuit is arranged between the MCU and the load switch and comprises a power supply circuit connected with a power supply, an MOS tube is arranged on the power supply circuit, a charging and discharging circuit is connected in parallel between the power supply circuit and the grid electrode of the MOS tube, two low-level output ends of the MCU are respectively connected in parallel with the power supply circuit through logic circuits, and each logic circuit can convert the corresponding low-level signal into a driving control signal of the load switch;
the charging and discharging circuit is provided with a first triode, the high-level output end of the MCU is connected with the base electrode of the first triode, and when the first triode is conducted, the power supply circuit can charge the charging and discharging circuit;
When the high-level output end and the two low-level output ends both output low-level signals, the charge-discharge circuit can discharge to the grid electrode of the MOS tube, so that the conduction time of the MOS tube and the holding time of the driving control signals are prolonged.
Further, the charging and discharging circuit comprises a charging resistor, a capacitor and a discharging resistor;
One end of the charging resistor is connected with the power supply circuit, and the other end of the charging resistor is connected with the collector electrode of the first triode;
One end of the capacitor is connected with the emitter of the first triode, and the other end of the capacitor is grounded;
One end of the discharging resistor is connected with the emitter of the first triode and the grid electrode of the MOS tube respectively, and the other end of the discharging resistor is connected with the grounding end of the capacitor.
Further, the logic circuit comprises a second triode, a third triode, a fourth triode and a signal output circuit;
The base electrode of the second triode is connected with the drain electrode of the MOS tube, and the emitter electrode of the second triode is connected with the low-level output end;
The base electrode of the third triode is connected with the collector electrode of the second triode, the collector electrode is connected with the drain electrode of the MOS tube, and the emitter electrode is grounded;
The base electrode of the fourth triode is connected with the emitter electrode of the third triode, the collector electrode of the fourth triode is connected with the MOS tube, and the reflecting electrode of the fourth triode is connected with the emitter electrode of the third triode;
And the input end of the signal output circuit is connected with the collector electrode of the fourth triode so as to output the driving control signal.
Further, a first resistor is arranged between the base electrode of the second triode and the drain electrode of the MOS tube;
A second resistor is arranged between the collector electrode of the third triode and the drain electrode of the MOS tube;
And a third resistor is arranged between the collector electrode of the fourth triode and the drain electrode of the MOS tube.
Further, a fourth resistor is arranged between the emitter of the third triode and the emitter of the fourth triode.
Further, the high-voltage power supply further comprises a diode, the positive electrode of the diode is grounded, and the negative electrode of the diode is respectively connected with the low-level output end and the second triode.
Compared with the prior art, the utility model has the following advantages:
According to the drive control signal holding circuit, the charge and discharge circuit is arranged, so that when the MCU fails and the high-level output end and the two low-level output ends output low-level signals, the charge and discharge circuit can discharge the grid electrode of the MOS tube, the conduction time of the MOS tube is prolonged, and the holding time of the drive control signal is further prolonged, the load switch is delayed to be closed when the MCU fails, response time is provided for a driver, and compared with the scheme of realizing delayed closing by means of a chip in the prior art, the drive control signal holding circuit is beneficial to arrangement and implementation and low in production cost.
In addition, the capacitor can be charged through the charging resistor in the charging and discharging circuit, the charged capacitor can be discharged through the discharging resistor, so that the conduction time of the MOS tube can be prolonged, and the charging and discharging circuit is simple in structure and good in using effect. When the second triode in the logic circuit is switched on, the third triode and the fourth triode are disconnected, at the moment, the use effect of the MCU is facilitated when the MCU does not fail, and when the second triode is disconnected, the second triode can be switched on through the third triode and the fourth triode, so that the MCU can still output a driving control signal when the MCU fails.
In addition, through setting up first resistance, second resistance and third resistance all can play the effect of partial pressure current limiting, and do benefit to second triode, third triode and fourth triode and have better result of use. And the voltage of the base electrode of the fourth triode is favorably adjusted by arranging the fourth resistor. The diode is arranged to play a better role in protection, and is simple in structure and convenient to arrange.
In addition, another object of the present utility model is to provide a BMS having the driving control signal holding circuit as described above between the MUC and the load switch.
Further, it is still another object of the present utility model to provide a battery pack provided with the BMS as described above.
The BMS and the battery pack of the present utility model have the same advantageous effects as the driving control signal holding circuit described above, and are not described herein again.
Drawings
The accompanying drawings, which are included to provide a further understanding of the utility model and are incorporated in and constitute a part of this specification, illustrate embodiments of the utility model and together with the description serve to explain the utility model. In the drawings:
Fig. 1 is a circuit configuration diagram of a drive control signal holding circuit according to an embodiment of the present utility model;
Fig. 2 is a schematic circuit diagram of a driving control signal holding circuit according to an embodiment of the present utility model.
Reference numerals illustrate:
1. A power supply; 2. a power supply circuit; 3. a MOS tube; 4. a charging resistor; 5. a first triode; 6. a high level output terminal; 7. a capacitor; 8. a discharge resistor; 9. a fifth resistor; 10. a first resistor; 11. a second resistor; 12. a third resistor; 13. a low level output terminal; 14. a diode; 15. a second triode; 16. a fourth resistor; 17. a third triode; 18. a fourth triode; 19. a signal output circuit; 20. driving the control signal.
Detailed Description
It should be noted that, without conflict, the embodiments of the present utility model and features of the embodiments may be combined with each other.
In the description of the present utility model, it should be noted that, if terms indicating an azimuth or a positional relationship such as "upper", "lower", "inner", "back", and the like are presented, they are based on the azimuth or the positional relationship shown in the drawings, only for convenience in describing the present utility model and simplifying the description, and do not indicate or imply that the apparatus or element to be referred to must have a specific azimuth, be constructed and operated in a specific azimuth, and thus should not be construed as limiting the present utility model. Furthermore, the terms "first," "second," and the like, if any, are also used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
The utility model will be described in detail below with reference to the drawings in connection with embodiments.
The present embodiment relates to a drive control signal holding circuit provided between an MCU and a load switch for prolonging the holding time of the load switch drive control signal 20 when the MCU fails, giving the driver coping time.
In the whole structure, as shown in fig. 1 and 2, the driving control signal holding circuit comprises a power circuit 2 connected with a power supply 1, a MOS tube 3 is arranged on the power circuit 2, a charge-discharge circuit is connected in parallel between the power circuit 2 and the gate electrode of the MOS tube 3, two low-level output ends 13 of the MCU are respectively connected in parallel with the power circuit 2 through logic circuits, and each logic circuit can convert a corresponding low-level signal into a driving control signal 20 of a load switch.
The charging and discharging circuit is provided with a first triode 5, the high-level output end 6 of the MCU is connected with the base electrode of the first triode 5, and when the first triode 5 is conducted, the power supply circuit 2 can charge the charging and discharging circuit. When the high-level output end 6 and the two low-level output ends 13 both output low-level signals, the charge-discharge circuit can discharge to the grid electrode of the MOS tube 3, so that the on time of the MOS tube 3 and the holding time of the driving control signal 20 are prolonged.
The driving control signal holding circuit of this embodiment, through setting up the charge-discharge circuit, can lead to high level output 6 and two low level output 13 when all outputting low level signal when the MCU breaks down, the charge-discharge circuit can be to the discharge of the grid of MOS pipe 3, and extension MOS pipe 3's conduction time, and then extension driving control signal 20's hold time, thereby make load switch delay to close when the MCU breaks down, provide the response time for the driver, and rely on the scheme that the chip was realized delaying to close in the prior art, do benefit to the arrangement implementation, and manufacturing cost is lower.
Based on the above overall description, the structure of the drive control signal holding circuit will be described in detail with reference to fig. 1 and 2. The load switch in this embodiment may be a contactor or a relay. The charge-discharge circuit in this embodiment includes a charge resistor 4, a capacitor 7, and a discharge resistor 8. One end of the charging resistor 4 is connected with the power circuit 2, and the other end is connected with the collector electrode of the first triode 5. One end of the capacitor 7 is connected with the emitter of the first triode 5, and the other end of the capacitor is grounded. One end of the discharging resistor 8 is connected with the emitter of the first triode 5 and the grid electrode of the MOS tube 3 respectively, and the other end of the discharging resistor 8 is connected with the grounding end of the capacitor 7. In addition, a fifth resistor 9 is further arranged between the discharge resistor 8 and the drain electrode of the MOS tube 3, so as to improve the use effect.
The MOS tube in the embodiment is an N-type MOS tube, the product is mature, the arrangement and implementation are convenient, and the using effect is good. At the initial stage of MCU under normal operating condition, can charge to electric capacity 7 through charging resistor 4, when MCU breaks down, can discharge the electric energy on the electric capacity 7 through discharging resistor 8 to do benefit to the conduction time of extension MOS pipe 3, and charging and discharging circuit's simple structure, excellent in use effect.
The logic circuit in this embodiment includes a second transistor 15, a third transistor 17, a fourth transistor 18, and a signal output circuit 19. The base electrode of the second triode 15 is connected with the drain electrode of the MOS tube 3, and the emitter electrode is connected with the low-level output end 13. The base electrode of the third triode 17 is connected with the collector electrode of the second triode 15, the collector electrode is connected with the drain electrode of the MOS tube 3, and the emitter electrode is grounded. The base electrode of the fourth triode 18 is connected with the emitter electrode of the third triode 17, the collector electrode is connected with the MOS tube 3, and the reflecting electrode is connected with the emitter electrode of the third triode 17. The input terminal of the signal output circuit 19 is connected to the collector of the fourth transistor 18 to output the driving control signal 20.
In this embodiment, when the second triode 15 in the logic circuit is turned on, the third triode 17 and the fourth triode 18 are both turned off, and at this time, the use effect of the MCU when no fault occurs is facilitated, and when the second triode 15 is turned off, the third triode 17 and the fourth triode 18 can be turned on, so that the MCU can still output the driving control signal 20 when the MCU fails.
In order to further improve the use effect of the logic circuit, as shown in fig. 2, a first resistor 10 is disposed between the base of the second triode 15 and the drain of the MOS transistor 3, a second resistor 11 is disposed between the collector of the third triode 17 and the drain of the MOS transistor 3, and a third resistor 12 is disposed between the collector of the fourth triode 18 and the drain of the MOS transistor 3. A fourth resistor 16 is arranged between the emitter of the third transistor 17 and the emitter of the fourth transistor 18.
The first resistor 10, the second resistor 11 and the third resistor 12 can have the voltage dividing and current limiting effects, so that the second triode 15, the third triode 17 and the fourth triode 18 have good use effects. The voltage of the base electrode of the fourth triode 18 is favorably adjusted by arranging the fourth resistor 16, so that the fourth triode 18 has better use effect.
As a preferred embodiment, the driving control signal holding circuit in this embodiment further includes a diode 14, wherein the anode of the diode 14 is grounded, and the cathode of the diode 14 is connected to the low-level output terminal 13 and the second transistor 15, respectively. The diode 14 can play a better role in protection, and the diode 14 is simple in structure and convenient to arrange.
When the MCU is in a normal operation state, the high level output terminal 6 outputs a high level signal, and the two low level output terminals 13 output a low level signal. The capacitor 7 in the charge-discharge circuit is charged, the source electrode and the drain electrode of the MOS tube 3 are in a conducting state, the second triode 15 is in a conducting state, the third triode 17 and the fourth triode 18 are in a disconnecting state, and at the moment, the output of each signal output circuit 19 is in a high level state, so that a driving control signal 20 is output, a load switch is in a conducting state, and the battery pack can be charged and discharged.
When the MCU breaks down, the high level output end 6 and the two low level output ends 13 are simultaneously in low level, the charging circuit discharges, so that the MOS tube 3 can still keep on for a certain time, at the moment, the second triode 15 is disconnected, the power supply 1 can supply power to the bases of the third triode 17 and the fourth triode 18, so that the third triode 17 and the fourth triode 18 keep on for a period of time, the output time of the driving control signal 20 can be prolonged on the signal output circuit 19, the time of the on state of the load switch is prolonged, the time of charging and discharging of the battery pack is prolonged, and the power is not immediately cut off due to the fault of the MCU.
In this embodiment, the charge/discharge circuit discharges through the discharge resistor 8 during discharge, and the time constant is τ C =10uf 1000000Ω=10s. For example, the voltage of the first triode 5 is 0.3V, and the maximum voltage across the capacitor 7 is about 3V.
V TL12＝V(e-0.3) =3×0.741= 2.223V when the extended hold time t=3 s is required, and V TL12＝V(e-0.7) =3×0.497=1.491V when the extended hold time t=7 s is required.
That is, the charge-discharge circuit in this embodiment may be such that the gate voltage of the first transistor 5 is maintained at 7S when it is 1.5V or more. From the start of discharging the capacitor 7 to the completion of discharging, the logic gate supplies power until the discharge completion MOS transistor 3 is turned off, and the drive control signal 20 also disappears.
Therefore, according to the resistance value of the discharge resistor 8 being 1000000Ω and the capacitance 7 of the capacitor 7 being 10uF, parameters are selected, the condition that the load switch is abnormal can be guaranteed, 7s is kept from being powered down, and the circuit debugging can finely tune and correct the capacitor 7 and the discharge resistor 8 according to actual requirements.
The driving control signal holding circuit of the embodiment has the advantages of simple structure, easy arrangement and implementation, good use effect, contribution to reducing production cost and good practicability.
In addition, the present embodiment also relates to a BMS having the drive control signal holding circuit as described above provided between the MUC and the load switch of the BMS, and a battery pack. The battery pack is provided with the BMS as described above.
The BMS and the battery pack of this embodiment have the same beneficial effects as the driving control signal holding circuit described above, and are not described here again.
The foregoing description of the preferred embodiments of the utility model is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements that fall within the spirit and scope of the utility model.
Claims (8)
1. The utility model provides a drive control signal keeps circuit, locates between MCU and the load switch, its characterized in that:
The driving control signal holding circuit comprises a power circuit connected with a power supply, wherein an MOS tube is arranged on the power circuit, a charge-discharge circuit is connected in parallel between the power circuit and the grid electrode of the MOS tube, two low-level output ends of the MCU are respectively connected in parallel with the power circuit through logic circuits, and each logic circuit can convert a corresponding low-level signal into a driving control signal of the load switch;
the charging and discharging circuit is provided with a first triode, the high-level output end of the MCU is connected with the base electrode of the first triode, and when the first triode is conducted, the power supply circuit can charge the charging and discharging circuit;
When the high-level output end and the two low-level output ends both output low-level signals, the charge-discharge circuit can discharge to the grid electrode of the MOS tube, so that the conduction time of the MOS tube and the holding time of the driving control signals are prolonged.
2. The drive control signal holding circuit according to claim 1, wherein:
the charging and discharging circuit comprises a charging resistor, a capacitor and a discharging resistor;
One end of the charging resistor is connected with the power supply circuit, and the other end of the charging resistor is connected with the collector electrode of the first triode;
One end of the capacitor is connected with the emitter of the first triode, and the other end of the capacitor is grounded;
One end of the discharging resistor is connected with the emitter of the first triode and the grid electrode of the MOS tube respectively, and the other end of the discharging resistor is connected with the grounding end of the capacitor.
3. The drive control signal holding circuit according to claim 1, wherein:
The logic circuit comprises a second triode, a third triode, a fourth triode and a signal output circuit;
The base electrode of the second triode is connected with the drain electrode of the MOS tube, and the emitter electrode of the second triode is connected with the low-level output end;
The base electrode of the third triode is connected with the collector electrode of the second triode, the collector electrode is connected with the drain electrode of the MOS tube, and the emitter electrode is grounded;
The base electrode of the fourth triode is connected with the emitter electrode of the third triode, the collector electrode of the fourth triode is connected with the MOS tube, and the reflecting electrode of the fourth triode is connected with the emitter electrode of the third triode;
And the input end of the signal output circuit is connected with the collector electrode of the fourth triode so as to output the driving control signal.
4. The drive control signal holding circuit according to claim 3, wherein:
A first resistor is arranged between the base electrode of the second triode and the drain electrode of the MOS tube;
A second resistor is arranged between the collector electrode of the third triode and the drain electrode of the MOS tube;
And a third resistor is arranged between the collector electrode of the fourth triode and the drain electrode of the MOS tube.
5. The drive control signal holding circuit according to claim 4, wherein:
and a fourth resistor is arranged between the emitter of the third triode and the emitter of the fourth triode.
6. The drive control signal holding circuit according to any one of claims 3 to 5, characterized in that:
The low-level output terminal is connected with the second triode, and the low-level output terminal is connected with the second triode.
7. A BMS, characterized in that:
A drive control signal holding circuit according to any one of claims 1 to 6 is provided between the MUC and the load switch of the BMS.
8. A battery pack, characterized in that:
The battery pack is provided with the BMS of claim 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322545524.6U CN220964852U (en) | 2023-09-18 | 2023-09-18 | Drive control signal holding circuit, BMS and battery pack |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322545524.6U CN220964852U (en) | 2023-09-18 | 2023-09-18 | Drive control signal holding circuit, BMS and battery pack |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220964852U true CN220964852U (en) | 2024-05-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202322545524.6U Active CN220964852U (en) | 2023-09-18 | 2023-09-18 | Drive control signal holding circuit, BMS and battery pack |
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| Country | Link |
|---|---|
| CN (1) | CN220964852U (en) |
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2023
- 2023-09-18 CN CN202322545524.6U patent/CN220964852U/en active Active
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