CN220896676U - Double-circuit USB isolator - Google Patents
Double-circuit USB isolator Download PDFInfo
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- CN220896676U CN220896676U CN202322689645.8U CN202322689645U CN220896676U CN 220896676 U CN220896676 U CN 220896676U CN 202322689645 U CN202322689645 U CN 202322689645U CN 220896676 U CN220896676 U CN 220896676U
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- 238000002955 isolation Methods 0.000 claims abstract description 111
- 230000000087 stabilizing effect Effects 0.000 claims abstract description 40
- 239000003990 capacitor Substances 0.000 claims description 18
- 230000008030 elimination Effects 0.000 claims description 18
- 238000003379 elimination reaction Methods 0.000 claims description 18
- 239000000919 ceramic Substances 0.000 claims description 12
- 101000941170 Homo sapiens U6 snRNA phosphodiesterase 1 Proteins 0.000 claims description 9
- 102100031314 U6 snRNA phosphodiesterase 1 Human genes 0.000 claims description 9
- 101100489717 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) GND2 gene Proteins 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The utility model provides a double-path USB isolator, and belongs to the technical field of USB isolation; the problem that the existing USB isolator cannot eliminate spark under the conditions of two paths of signal interference and short circuit at the same time is solved; the USB isolation circuit comprises a shell and a bottom plate, wherein a circuit board is arranged in the shell, two paths of USB isolation circuits which are in mirror symmetry are integrated on the circuit board, and isolation wires are divided between the two paths of USB isolation circuits on the circuit board; each path of USB isolation circuit comprises a chip isolation circuit, an isolation voltage stabilizing circuit and a limiting overvoltage circuit, wherein the input end of the chip isolation circuit is connected with a host USB interface, the output end of the chip isolation circuit is connected with an external device USB interface, the input end of the isolation voltage stabilizing circuit is connected with a host power supply end, the output end of the isolation voltage stabilizing circuit is connected with external devices through the limiting overvoltage circuit, and the limiting overvoltage circuit and a ground wire of the output end of the chip isolation circuit are connected with the output end of the isolation voltage stabilizing circuit; the utility model is applied to USB isolation.
Description
Technical Field
The utility model provides a double-path USB isolator, and belongs to the technical field of USB isolators.
Background
With the continuous development of computer technology, the security problem is more and more emphasized, and most of the existing computer systems are not isolated, so that great hidden danger exists in the aspect of security. The interference of a host or a power supply and the interference brought by other equipment externally connected with the host can be conducted to the external equipment through a USB circuit to influence the operation of the external equipment, so that an isolator is required to be arranged between the host and the external equipment, the isolator is a device for exchanging data signals between two galvanically isolated circuit systems, and the isolating device can pass through isolation barrier to provide data exchange to keep galvanically isolated. The utility model provides a double-path USB isolator which is used for eliminating signal interference and is safe in short circuit, and an isolation circuit, and solves the problem that the existing USB isolator cannot eliminate spark under the conditions of two paths of signal interference and short circuit at the same time.
Disclosure of utility model
The utility model provides a double-path USB isolator, which aims to solve the problem that the existing USB isolator can not realize the simultaneous elimination of two paths of signal interference and spark generation under the condition of short circuit, and aims to eliminate the signal interference and the short circuit safety by improving hardware or improving the combined connection of hardware modules and/or circuits.
In order to solve the technical problems, the utility model adopts the following technical scheme: the double-path USB isolator comprises a shell and a bottom plate, wherein a circuit board is arranged in the shell, isolation columns are arranged on the bottom plate, the circuit board is isolated from the bottom plate through the isolation columns, threaded columns corresponding to the isolation columns are arranged on the circuit board, the top of the shell is in threaded connection with the threaded columns through screws, the bottom of the bottom plate is in threaded connection with the threaded columns after penetrating through the isolation columns through bolts, wiring ports are formed in two sides of the shell, and the wiring ports correspond to an input port and an output port on the circuit board respectively;
Two paths of USB isolation circuits which are in mirror symmetry are integrated on the circuit board, and isolation wires are divided between the two paths of USB isolation circuits on the circuit board, so that no electrical connection exists between the two paths of USB isolation circuits;
Each path of USB isolation circuit comprises a chip isolation circuit, an isolation voltage stabilizing circuit and a limiting overvoltage circuit, wherein the input end of the chip isolation circuit is connected with a host USB interface, the output end of the chip isolation circuit is connected with an external device USB interface, the input end of the isolation voltage stabilizing circuit is connected with a host power supply end, the output end of the isolation voltage stabilizing circuit is connected with an external device through the limiting overvoltage circuit, and the ground wires of the output ends of the limiting overvoltage circuit and the chip isolation circuit are connected with a 0V output end of the isolation voltage stabilizing circuit.
The input end and the output end of the chip isolation circuit are respectively connected with an input electrostatic interference elimination circuit and an output electrostatic interference elimination circuit.
The chip isolation circuit comprises a USB isolation chip U5, UD_1 and UD+1 pins of the USB isolation chip U5 are correspondingly connected with D-, D+ pins of a USB interface of a host through the input electrostatic interference elimination circuit, and UD_2 and UD+2 pins of the USB isolation chip U5 are correspondingly connected with D-, D+ pins of a USB interface of an external device through the output electrostatic interference elimination circuit.
The isolation voltage stabilizing circuit comprises a power isolation chip U4, a 10K resistor R5, a polar capacitor C10, a capacitor C4, a diode D1 and an inductor L1, wherein the chip U4 is connected with the polar capacitor C10 and the capacitor C4 in parallel, one end of the inductor L1 is connected with the anode of the diode D1 in parallel, the diode D1 is connected with the resistor R5 in series, then the polar capacitor C10 and one end of the capacitor C4 are connected with a 5V power supply in parallel, and the 5V power supply is used for supplying power to the chip U4.
The overvoltage limiting circuit comprises an output end USB1, a ceramic high-voltage discharge tube G2, a ceramic high-voltage discharge tube G3, a resistor R8, a resistor R9, a voltage stabilizing diode D2, a voltage stabilizing diode D3 and a voltage stabilizing diode D4; the DD-of the USB1 is connected with one ends of the ceramic high-voltage discharge tube G3 and the resistor R8 in parallel, the DD-of the USB1 is connected with one ends of the ceramic high-voltage discharge tube G4 and the resistor R9 in parallel, and the zener diode D2, the zener diode D3 and the zener diode D4 are connected in parallel and are connected with the GND of the USB 1.
The USB isolating chip U5 specifically adopts ADUM4160 chips, a GND2 PIN of ADUM4160 chips is connected with the ground wire of the output end of the isolating voltage stabilizing circuit, a GND2 PIN of ADUM4160 chips is also connected with an L PIN of the SW-SPDT switch, an H PIN of the SW-SPDT switch is connected with one end of a resistor R13 in series and then connected with a VDD2 PIN of ADUM4160 chips, and the other end of the resistor R14 is connected with a PIN PIN of ADUM4160 chips.
The chips of the input signal interference elimination circuit and the output signal interference circuit adopt SN65240 chips, the chips of the input electrostatic interference elimination circuit and the output electrostatic interference elimination circuit adopt SRV05 chips, and the chips of the isolation voltage stabilizing circuit adopt B0505S-2W chips.
Compared with the prior art, the utility model has the following beneficial effects: according to the utility model, through arranging the USB isolation circuit and the isolation circuit, the requirements of two paths of signals of a double system of the touch equipment are met while signal interference is eliminated, meanwhile, the boosting voltage stabilizing circuit is arranged to ensure output voltage, the arranged DC-DC isolation module separates the ground wires at two ends of the isolation circuit, common-mode interference is eliminated while output working current is increased, and the USB isolation circuit, the isolation circuit and the boosting voltage stabilizing circuit are arranged in an isolated manner, so that the signal interference, electrostatic interference and power supply interference are eliminated simultaneously, and the performance of the USB isolator is improved.
Drawings
The utility model is further described below with reference to the accompanying drawings:
FIG. 1 is a schematic diagram of the structure of the present utility model;
FIG. 2 is a system block diagram of the present utility model;
FIG. 3 is a schematic diagram of one USB isolation circuit according to the present utility model;
In the figure: 1. a screw; 2. a housing; 3. a wiring port; 4. an input port; 5. an output port; 6. a bottom plate; 7. a circuit board; 8. a bolt; 9. a separation column; 10. a threaded column; 11. and a fixing hole.
Detailed Description
As shown in fig. 1 to 3, the two-way USB isolator of the present utility model includes a base plate 6 and a housing 2, an isolation column 9 is provided on the base plate 6, the base plate 6 is isolated from a circuit board 7 by the isolation column 9, a threaded column 10 is provided on the circuit board 7 corresponding to the position of the isolation column 9, and a screw 1 is screwed with the threaded column 10 on the top of the housing 2, so as to fix the housing 2 and the circuit board 8, and the bottom of the base plate 6 is screwed with the threaded column 10 after passing through the isolation column 9 by a bolt 8, so as to fix the base plate 6 and the circuit board 7. Wiring ports 3 are also provided on both sides of the housing 2, corresponding to the input port 4 and the output port 5 on the circuit board 7, respectively.
The circuit board 7 is integrated with a double-circuit USB isolation circuit, so that the requirements of two signals of an external circuit and a host machine are met while signal interference is eliminated, and the signal interference and the power interference are eliminated. The two paths of USB isolation circuits on the circuit board 7 are arranged in a mirror symmetry mode on the circuit board, no electrical connection is achieved between the two paths of USB isolation circuits through dividing isolation lines on the circuit board, and each path of USB isolation circuit comprises a chip isolation circuit, an isolation voltage stabilizing circuit and an overvoltage limiting circuit; the input end of the chip isolation circuit is connected with the USB interface of the host computer, and the output end of the chip isolation circuit is connected with the USB interface of the external equipment; the input end of the isolation voltage stabilizing circuit is connected with the power end of the host, and the output end of the isolation voltage stabilizing circuit is connected with external equipment through the overvoltage limiting circuit; and the ground wire of the output ends of the overvoltage limiting circuit and the chip isolation circuit is connected with the 0V output end of the isolation voltage stabilizing circuit.
The chip isolation circuit comprises a USB isolation chip U5, UD_1 and UD+1 pins of the USB isolation chip U5 are correspondingly connected with D-, D+ pins of a USB interface of a host, and UD_2 and UD+2 pins of the USB isolation chip U5 are correspondingly connected with D-, D+ pins of a USB interface of an external device.
The isolation voltage stabilizing circuit comprises a chip U4, a 10K resistor R5, a polar capacitor C10, a capacitor C4, a diode D1 and an inductor L1, wherein the chip U4 is connected with the polar capacitor C10 and the capacitor C4 in parallel, one end of the inductor L1 is connected with the anode of the diode D1 in parallel, the diode D1 is connected with the resistor R5 in series and then connected with the polar capacitor C10 and one end of the capacitor C4 in parallel, and then a 5V power supply is connected to the chip U4 through the 5V power supply.
The overvoltage limiting circuit comprises an output end USB1, a ceramic high-voltage discharge tube G2, a ceramic high-voltage discharge tube G3, a resistor R8, a resistor R9, a voltage stabilizing diode D2, a voltage stabilizing diode D3 and a voltage stabilizing diode D4. The DD-of the USB1 is connected with one ends of the ceramic high-voltage discharge tube G3 and the resistor R8 in parallel, the DD-of the USB1 is connected with one ends of the ceramic high-voltage discharge tube G4 and the resistor R9 in parallel, and the zener diode D2, the zener diode D3 and the zener diode D4 are connected in parallel and are connected with the GND of the USB 1.
An isolator is a device that exchanges data signals between two galvanically isolated circuit systems, and the isolating device can provide data exchange across an isolation barrier, maintaining galvanic isolation. Isolation devices have been used for USB communications, and these devices typically include a USB receiver that receives data from a USB cable according to a USB protocol, and transmits the received data across an isolation barrier. The USB physical layer contains only 4 lines: two wires providing 5V power and ground to the external device and two other wires (D + and D-) form twisted pair wires that can carry differential data, these wires can also carry single ended data and idle states implemented with passive resistors. When the device is connected to the bus, the current in the passive resistive structure negotiates the transmission speed and establishes an idle state without drive. The data is organized into data frames or packets, each frame may contain clock synchronization bits, a data type identifier, a device address, a data payload, and a sequence of packet tails.
The device comprises a host, an external device, a USB isolation circuit, a voltage stabilizing and boosting circuit and a common mode interference removing device, wherein an isolator is arranged between the host and the external device to remove power supply interference and signal interference, the input end of the USB isolation circuit is connected with a USB interface of the host, the output end of the USB isolation circuit is connected with a USB interface of the external device, the interference of two paths of signals is cut off, the requirement of double signals is met, the input end of the voltage stabilizing and boosting circuit is connected with the host, the output end of the voltage stabilizing and boosting circuit is connected with the external device to ensure the output of 5V voltage, the ground wires of the input end of the external device are respectively connected with the input end of the isolation voltage stabilizing circuit, the ground wires of the output end of the USB isolation circuit are respectively connected with the output end of the isolation voltage stabilizing circuit, and the ground wires of the two ends of the USB isolation circuit are separated, so that common mode interference is removed.
The USB isolation circuit adopts ADUM4160BRWZ isolation chips, the chip of the signal interference elimination circuit adopts N65240, and the isolation voltage stabilizing circuit adopts B0505S-2W; the static interference eliminating chip adopts an SRV05 chip.
The specific structure of the utility model needs to be described that the connection relation between the component modules adopted by the utility model is definite and realizable, and besides the specific description in the embodiment, the specific connection relation can bring about corresponding technical effects, and on the premise of not depending on execution of corresponding software programs, the technical problems of the utility model are solved, the types of the components, the modules and the specific components, the connection modes of the components and the expected technical effects brought by the technical characteristics are clear, complete and realizable, and the conventional use method and the expected technical effects brought by the technical characteristics are all disclosed in patents, journal papers, technical manuals, technical dictionaries and textbooks which can be acquired by a person in the field before the application date, or the prior art such as conventional technology, common knowledge in the field, and the like, so that the provided technical scheme is clear, complete and the corresponding entity products can be reproduced or obtained according to the technical means.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present utility model, and not for limiting the same; although the utility model has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the utility model.
Claims (7)
1. A double-circuit USB isolator is characterized in that: the circuit board is arranged in the shell, the bottom plate is provided with an isolation column, the circuit board is isolated from the bottom plate through the isolation column, the circuit board is provided with a threaded column corresponding to the isolation column, the top of the shell is in threaded connection with the threaded column through a screw, the bottom of the bottom plate is in threaded connection with the threaded column after passing through the isolation column through a bolt, and two sides of the shell are provided with wiring ports corresponding to an input port and an output port on the circuit board respectively;
Two paths of USB isolation circuits which are in mirror symmetry are integrated on the circuit board, and isolation wires are divided between the two paths of USB isolation circuits on the circuit board, so that no electrical connection exists between the two paths of USB isolation circuits;
Each path of USB isolation circuit comprises a chip isolation circuit, an isolation voltage stabilizing circuit and a limiting overvoltage circuit, wherein the input end of the chip isolation circuit is connected with a host USB interface, the output end of the chip isolation circuit is connected with an external device USB interface, the input end of the isolation voltage stabilizing circuit is connected with a host power supply end, the output end of the isolation voltage stabilizing circuit is connected with an external device through the limiting overvoltage circuit, and the ground wires of the output ends of the limiting overvoltage circuit and the chip isolation circuit are connected with a 0V output end of the isolation voltage stabilizing circuit.
2. A two-way USB isolator as claimed in claim 1, wherein: the input end of the chip isolation circuit is connected with the USB interface of the host through the input signal interference elimination circuit and the input electrostatic interference elimination circuit, and the output end of the chip isolation circuit is connected with the USB interface of the external equipment through the output signal interference elimination circuit and the output electrostatic interference elimination circuit.
3. A two-way USB isolator as claimed in claim 2, wherein: the chip isolation circuit comprises a USB isolation chip U5, UD_1 and UD+1 pins of the USB isolation chip U5 are correspondingly connected with D-, D+ pins of a USB interface of a host through the input electrostatic interference elimination circuit, and UD_2 and UD+2 pins of the USB isolation chip U5 are correspondingly connected with D-, D+ pins of a USB interface of an external device through the output electrostatic interference elimination circuit.
4. A two-way USB isolator according to claim 3, wherein: the isolation voltage stabilizing circuit comprises a power isolation chip U4, a 10K resistor R5, a polar capacitor C10, a capacitor C4, a diode D1 and an inductor L1, wherein the chip U4 is connected with the polar capacitor C10 and the capacitor C4 in parallel, one end of the inductor L1 is connected with the anode of the diode D1 in parallel, the diode D1 is connected with the resistor R5 in series, then the polar capacitor C10 and one end of the capacitor C4 are connected with a 5V power supply in parallel, and the 5V power supply is used for supplying power to the chip U4.
5. The two-way USB isolator of claim 4, wherein: the overvoltage limiting circuit comprises an output end USB1, a ceramic high-voltage discharge tube G2, a ceramic high-voltage discharge tube G3, a resistor R8, a resistor R9, a voltage stabilizing diode D2, a voltage stabilizing diode D3 and a voltage stabilizing diode D4;
The DD-of the USB1 is connected with one ends of the ceramic high-voltage discharge tube G3 and the resistor R8 in parallel, the DD-of the USB1 is connected with one ends of the ceramic high-voltage discharge tube G4 and the resistor R9 in parallel, and the zener diode D2, the zener diode D3 and the zener diode D4 are connected in parallel and are connected with the GND of the USB 1.
6. A two-way USB isolator as claimed in claim 5, wherein: the USB isolating chip U5 specifically adopts ADUM4160 chips, a GND2 PIN of ADUM4160 chips is connected with the ground wire of the output end of the isolating voltage stabilizing circuit, a GND2 PIN of ADUM4160 chips is also connected with an L PIN of the SW-SPDT switch, an H PIN of the SW-SPDT switch is connected with one end of a resistor R13 in series and then connected with a VDD2 PIN of ADUM4160 chips, and the other end of the resistor R14 is connected with a PIN PIN of ADUM4160 chips.
7. A two-way USB isolator as in claim 6, wherein: the chips of the input signal interference elimination circuit and the output signal interference circuit adopt SN65240 chips, the chips of the input electrostatic interference elimination circuit and the output electrostatic interference elimination circuit adopt SRV05 chips, and the chips of the isolation voltage stabilizing circuit adopt B0505S-2W chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322689645.8U CN220896676U (en) | 2023-10-08 | 2023-10-08 | Double-circuit USB isolator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322689645.8U CN220896676U (en) | 2023-10-08 | 2023-10-08 | Double-circuit USB isolator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220896676U true CN220896676U (en) | 2024-05-03 |
Family
ID=90871989
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202322689645.8U Active CN220896676U (en) | 2023-10-08 | 2023-10-08 | Double-circuit USB isolator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220896676U (en) |
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2023
- 2023-10-08 CN CN202322689645.8U patent/CN220896676U/en active Active
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