CN220794265U - Encoder output circuit, laser galvanometer and processing equipment - Google Patents
Encoder output circuit, laser galvanometer and processing equipment Download PDFInfo
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- CN220794265U CN220794265U CN202321978877.9U CN202321978877U CN220794265U CN 220794265 U CN220794265 U CN 220794265U CN 202321978877 U CN202321978877 U CN 202321978877U CN 220794265 U CN220794265 U CN 220794265U
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Abstract
The application relates to encoder output circuit, laser galvanometer and processing equipment, wherein encoder output circuit includes: the comparator circuit is provided with a first input end, a second input end and a comparison signal output end, wherein the first input end is used for being connected with the first signal output end of the encoder, the second input end is used for being connected with the second signal output end of the encoder, and the first signal output end and the second signal output end are respectively used for outputting different zero signals; and the base electrode of the triode circuit is connected to the comparison signal output end, the emitter electrode of the triode circuit is grounded, and the collector electrode of the triode circuit is used for being connected to a power supply and can be used as an output end. The encoder output circuit realizes the detection of the rotor shaft position, effectively ensures that the laser galvanometer motor realizes high-speed high-dynamic motion performance, ensures the working reliability of the motor encoder, and further improves the stability of the laser galvanometer.
Description
Technical Field
The application relates to the field of laser processing signal processing, in particular to an encoder output circuit, a laser galvanometer and processing equipment.
Background
Along with the continuous progress of laser processing signal processing technology and the continuous and abundant application scenes of modern industry, the requirements on the product integration level and stability of laser processing equipment are higher and higher. The laser galvanometer motor is used as an important component of laser processing equipment, and is important for driving the laser galvanometer so as to ensure the laser processing precision.
In the laser processing process, in order to realize high-speed high-dynamic motion performance, the motor inner encoder is required to detect the rotor position and the like, and in order to conveniently detect the rotor shaft position, a zero position is usually required to be determined, so that the acquisition of the zero position of the motor inner encoder is important, however, the structure of a common zero detection circuit is complex.
Disclosure of Invention
Accordingly, it is desirable to provide an encoder output circuit, a laser galvanometer, and a processing apparatus, in order to solve the above-mentioned problems.
An encoder output circuit, comprising:
the comparator circuit is provided with a first input end, a second input end and a comparison signal output end, wherein the first input end is used for being connected with the first signal output end of the encoder, the second input end is used for being connected with the second signal output end of the encoder, and the first signal output end and the second signal output end are respectively used for outputting different zero signals;
and the base electrode of the triode circuit is connected with the comparison signal output end, the emitting electrode of the triode circuit is grounded, and the collecting electrode of the triode circuit is used for being connected with a power supply and can be used as an output end.
In one embodiment, the method further comprises:
the amplifier circuit comprises a non-inverting input end, an inverting input end and an amplifying signal output end, wherein the non-inverting input end is used for being connected with a third signal output end of the encoder, the inverting input end is used for being connected with a fourth signal output end of the encoder, and the third signal output end and the fourth signal output end are respectively used for outputting different sine signals or different cosine signals;
the first end of any one of the voltage dividing units is correspondingly connected with the amplified signal output end of one of the amplifier circuits, and the second end of any one of the voltage dividing units is used for being connected with the output end of the encoder output circuit.
In one embodiment, the plurality of voltage dividing units includes a first voltage dividing unit, a second voltage dividing unit, a third voltage dividing unit, and a fourth voltage dividing unit, and the plurality of amplifier circuits includes:
the non-inverting input end of the first amplifier circuit is used for being connected with the first sinusoidal signal output end of the encoder, the inverting input end of the first amplifier circuit is used for being connected with the second sinusoidal signal output end of the encoder, and the amplified signal output end of the first amplifier circuit is connected with the first end of the first voltage dividing unit;
the non-inverting input end of the second amplifier circuit is used for being connected with the second sinusoidal signal output end of the encoder, the inverting input end of the second amplifier circuit is used for being connected with the first sinusoidal signal output end of the encoder, and the amplified signal output end of the second amplifier circuit is connected with the first end of the second voltage division unit;
the non-inverting input end of the third amplifier circuit is used for being connected with the first cosine signal output end of the encoder, the inverting input end of the third amplifier circuit is used for being connected with the second cosine signal output end of the encoder, and the amplified signal output end of the third amplifier circuit is connected with the first end of the third voltage dividing unit;
and the non-inverting input end of the fourth amplifier circuit is used for being connected with the second cosine signal output end of the encoder, the inverting input end of the fourth amplifier circuit is used for being connected with the first cosine signal output end of the encoder, and the amplified signal output end of the fourth amplifier circuit is connected with the first end of the fourth voltage dividing unit.
In one embodiment, the method further comprises:
the first end of the first pre-stage filter is connected with the non-inverting input end of the first amplifier circuit and the inverting input end of the second amplifier circuit, and the second end of the first pre-stage filter is connected with the inverting input end of the first amplifier circuit and the non-inverting input end of the second amplifier circuit;
the first end of the second pre-stage filter is connected with the non-inverting input end of the third amplifier circuit and the inverting input end of the fourth amplifier circuit, and the second end of the second pre-stage filter is connected with the inverting input end of the third amplifier circuit and the non-inverting input end of the fourth amplifier circuit.
In one embodiment, the method further comprises:
the second end of the first post-stage filter is connected with the second end of the second voltage division unit;
the first end of the second post-stage filter is connected to the second end of the third voltage dividing unit, and the second end of the second post-stage filter is connected to the second end of the third voltage dividing unit.
In one embodiment, the method further comprises:
the follower circuit is provided with a non-inverting input end, an inverting input end and a compensation signal output end, wherein the non-inverting input end is used for being connected with the power supply, and the compensation signal output end is connected with the inverting input end and the non-inverting input end of any amplifier circuit.
In one embodiment, the method further comprises:
and the decoupler is used for being connected with the power supply and the comparator circuit and outputting a target power supply signal.
In one embodiment, the decoupler comprises a first capacitor and a second capacitor, the first end of the first capacitor and the first end of the second capacitor being configured to be connected to the power source, the second end of the first capacitor and the second end of the second capacitor being configured to be connected to the power source input of the comparator circuit.
A laser galvanometer, comprising:
such as the encoder output circuit described above.
A processing apparatus comprising:
such as the encoder output circuit described above.
The beneficial effects that the embodiment exists are provided in this application:
according to the encoder output circuit, different zero signals output by the encoder are respectively obtained through the two input ends of the comparator circuit, and the common collector output mode of the triode is matched, when the signal input by the base electrode (namely, the signal output by the comparison signal output end) is at a low level, the signal output by the collector electrode is at a high level; when the signal input by the base electrode is high level, the signal output by the collector electrode is low level, so that different level signal output can be realized when the zero signal output by the encoder is detected, and different level signals are respectively output by the comparison signal output end and the collector electrode of the triode circuit, so that level transition is detected, namely, the zero position is acquired, further, the detection of the rotor shaft position is realized, the high-speed high-dynamic motion performance of the laser galvanometer motor is effectively ensured, the working reliability of the motor encoder is ensured, and further, the stability of the laser galvanometer is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of the encoder output circuitry in one embodiment;
FIG. 2 is a block diagram of the encoder output circuitry in one embodiment;
FIG. 3 is a block diagram of the encoder output circuitry in one embodiment;
FIG. 4 is a block diagram of the encoder output circuitry in one embodiment;
FIG. 5 is a block diagram of the encoder output circuitry in one embodiment;
FIG. 6 is a schematic diagram of an encoder output circuit in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Fig. 1 is a block diagram schematically illustrating the structure of an encoder output circuit in one embodiment.
In this embodiment, the encoder output circuit can be applied to a laser galvanometer, and as shown in fig. 1, the encoder output circuit includes a comparator circuit 10 and a triode circuit 20.
The comparator circuit 10 has a first input for connection to the first signal output of the encoder, a second input for connection to the second signal output of the encoder, and a comparison signal output for outputting different zero signals.
The comparator circuit 10 may be a functional circuit connected to the encoder and the triode circuit 20, and capable of comparing the magnitudes of the zero signals output from the encoder and outputting the compared magnitudes of the compared signals to the triode circuit 20. The first input terminal and the second input terminal may be a negative input terminal and a positive input terminal of the comparator, respectively. The comparison signal may be a level signal. The zero signal can be a zero signal output by a motor encoder; optionally, the zero signal includes a zero output signal z+ and a zero output signal Z-, the zero output signal z+ being opposite in direction to the zero output signal Z-at the same time.
The amplitude comparison processing can be to compare the amplitudes of the zero-bit output signal Z+ and the zero-bit output signal Z-so as to judge the logic magnitude relation between the zero-bit output signal Z+ and the zero-bit output signal Z-; the level signals include a high level signal 1 and a low level signal 0.
The comparison signal may be outputted according to the amplitude comparison result, in which the high-level signal 1 is outputted when the amplitude of the zero-position output signal z+ is greater than the amplitude of the zero-position output signal Z-, or the high-level signal 0 is outputted when the amplitude of the zero-position output signal z+ is smaller than the amplitude of the zero-position output signal Z-.
The base of the triode circuit 20 is connected to the comparison signal output terminal, the emitter of the triode circuit 20 is grounded, and the collector of the triode circuit 20 is used for being connected to a power supply and can be used as the output terminal of the encoder output circuit.
The transistor circuit 20 may be a functional circuit which is connected to the comparator circuit 10, performs signal inversion processing based on a comparison signal output from the comparator circuit 10, and outputs an inverted signal. The signal inversion processing may be a process of outputting a low-level signal based on a high-level signal or a process of outputting a high-level signal based on a low level signal.
The case of performing signal inversion processing according to the comparison signal output from the comparator circuit 10 and outputting the inverted signal to the output terminal of the encoder output circuit includes:
when the signal input from the negative input terminal of the comparator circuit 10 is greater than the signal input from the positive input terminal, the comparison signal output from the comparison signal output terminal is a low-level signal, that is, the signal input from the base of the triode circuit 20 is a low-level signal, and the signal output from the collector of the triode circuit 20 is a high-level signal, then the low-level signal and the high-level signal are respectively output through the comparison signal output terminal and the collector of the triode circuit 20.
When the signal input from the negative input terminal of the comparator circuit 10 is smaller than the signal input from the positive input terminal, the comparison signal output from the comparison signal output terminal is a high level signal, that is, the signal input from the base of the triode circuit 20 is a high level signal, and the signal output from the collector of the triode circuit 20 is a low level signal, then the high level signal and the low level signal are respectively output through the comparison signal output terminal and the collector of the triode circuit 20.
In the encoder output circuit provided in this embodiment, two input ends of the comparator circuit 10 respectively obtain different zero signals output by the encoder, and cooperate with a common collector output mode of the triode, when a signal input by the base (i.e. a signal output by the comparison signal output end) is at a low level, a signal output by the collector is at a high level; when the signal input by the base electrode is in a high level, the signal output by the collector electrode is in a low level, so that different level signal output can be realized when the zero signal output by the encoder is detected, and different level signals are respectively output by the comparison signal output end and the collector electrode of the triode circuit 20, so that level transition is detected, namely, the zero position is acquired, further, the detection of the rotor shaft position is realized, the high-speed high-dynamic motion performance of the laser galvanometer motor is effectively ensured, the working reliability of the motor encoder is ensured, and further, the stability of the laser galvanometer is improved.
Fig. 2 is a block diagram schematically illustrating the structure of an encoder output circuit in one embodiment.
In the present embodiment, as shown in fig. 2, the encoder output circuit includes a comparator circuit 10 and a triode circuit 20, and further includes a plurality of amplifier circuits 30 and a plurality of voltage dividing units 40.
Any amplifier circuit is provided with an in-phase input end, an anti-phase input end and an amplified signal output end, wherein the in-phase input end is used for being connected with a third signal output end of the encoder, the anti-phase input end is used for being connected with a fourth signal output end of the encoder, and the third signal output end and the fourth signal output end are respectively used for outputting different sine signals or different cosine signals.
The sinusoidal signal may be a sinusoidal differential signal output by the encoder; optionally, the sinusoidal differential signal includes a sinusoidal differential signal sin+ and a sinusoidal differential signal sin-, and the same time sinusoidal differential signal sin+ and the sinusoidal differential signal sin-are opposite in direction. The cosine signal can be a cosine differential signal output by the motor encoder; optionally, the cosine differential signal includes a cosine differential signal cos+ and a cosine differential signal cos-, and the cosine differential signal cos+ and the cosine differential signal cos-are opposite in direction at the same time.
The amplifier circuit may be a functional circuit connected to the encoder and the voltage dividing unit, and capable of amplifying different sinusoidal signals or different cosine signals output from the encoder, and outputting the amplified target amplified signal to the voltage dividing unit.
The amplification process may be a process of multiplying the amplitude of the sine differential signal or the cosine differential signal output from the encoder to adjust the amplitude to a target value. The target amplified signal may be a signal generated by amplifying a multiple of the amplitude of the sine differential signal or the cosine differential signal.
The first end of any voltage dividing unit is correspondingly connected with the amplified signal output end of one amplifier circuit, and the second end of any voltage dividing unit is used for being connected with the output end of the encoder output circuit.
The voltage dividing unit may be connected to the output ends of the amplifier circuit and the encoder output circuit, and may perform voltage dividing processing on the target amplified signal output by the amplifier circuit, output the divided target amplified signal to the output end of the encoder output circuit, and may also perform amplitude adjusting processing on the return signal from the output end of the encoder output circuit, and output the return signal with the amplitude adjusted to the functional circuit of the amplifier circuit.
The return signal may be an interfering signal input via the output of the encoder output circuit. The amplitude adjustment process may be a process of reducing the amplitude of the return signal to reduce the interference effect of the return signal on the amplifier circuit.
Alternatively, the plurality of voltage dividing units 40 includes a first voltage dividing unit 420, a second voltage dividing unit 440, a third voltage dividing unit 460, and a fourth voltage dividing unit 480, and the plurality of amplifier circuits 30 includes a first amplifier circuit 320, a second amplifier circuit 340, a third amplifier circuit 360, and a fourth amplifier circuit 380.
The non-inverting input terminal of the first amplifier circuit 320 is used for being connected to a first sinusoidal signal output terminal of an encoder, the inverting input terminal of the first amplifier circuit 320 is used for being connected to a second sinusoidal signal output terminal of the encoder, and the amplified signal output terminal of the first amplifier circuit 320 is connected to a first terminal of the first voltage dividing unit 420.
The non-inverting input terminal of the second amplifier circuit 340 is connected to the second sinusoidal signal output terminal of the encoder, the inverting input terminal of the second amplifier circuit 340 is connected to the first sinusoidal signal output terminal of the encoder, and the amplified signal output terminal of the second amplifier circuit 340 is connected to the first terminal of the second voltage dividing unit 440.
The non-inverting input terminal of the third amplifier circuit 360 is used for connecting with the first cosine signal output terminal of the encoder, the inverting input terminal of the third amplifier circuit 360 is used for connecting with the second cosine signal output terminal of the encoder, and the amplified signal output terminal of the third amplifier circuit 360 is connected with the first terminal of the third voltage dividing unit 460.
The non-inverting input terminal of the fourth amplifier circuit 380 is used for connecting with the second cosine signal output terminal of the encoder, the inverting input terminal of the fourth amplifier circuit 380 is used for connecting with the first cosine signal output terminal of the encoder, and the amplified signal output terminal of the fourth amplifier circuit 380 is connected with the first terminal of the fourth voltage dividing unit 480.
The encoder output circuit provided in this embodiment, through the cooperation of a plurality of amplifier circuits 30 and a plurality of voltage dividing units 40, when realizing compatible conditioning to the sine output signal and the cosine output signal output by the laser galvanometer motor encoder, effectively reduces the interference effect of external reflux signals, improves the overall integration level of the motor encoder, ensures the working reliability of the motor encoder, and then improves the integration level and stability of the laser galvanometer.
Fig. 3 is a block diagram schematically illustrating the structure of an encoder output circuit in one embodiment.
In the present embodiment, as shown in fig. 3, the encoder output circuit includes a comparator circuit 10, a triode circuit 20, a plurality of amplifier circuits 30, and a plurality of voltage dividing units 40, and further includes a front stage filter 50 and a rear stage filter 60.
The pre-stage filter 50 includes a first pre-stage filter 520 and a second pre-stage filter 540, a first end of the first pre-stage filter 520 is connected to the non-inverting input of the first amplifier circuit 320 and the inverting input of the second amplifier circuit 340, and a second end of the first pre-stage filter 520 is connected to the inverting input of the first amplifier circuit 320 and the non-inverting input of the second amplifier circuit 340.
The first end of the second pre-stage filter 540 is connected to the non-inverting input of the third amplifier circuit 360 and the inverting input of the fourth amplifier circuit 380, and the second end of the second pre-stage filter 540 is connected to the non-inverting input of the third amplifier circuit 360 and the non-inverting input of the fourth amplifier circuit 380.
The pre-filter 50 may be a functional circuit connected to the encoder and the amplifier circuit, and capable of performing a first filtering process on different sinusoidal signals or different residual signals output from the encoder, and outputting a first target filtered signal after the first filtering to the amplifier circuit.
The first filtering process may be a process of filtering noise signals of a specific frequency in the sine differential signal or the cosine differential signal output from the encoder and generating a first target filtered signal. The first target filtered signal may be a signal generated by filtering noise signals in a sine differential signal or a cosine differential signal.
The post-stage filter 60 includes a first post-stage filter 620 and a second post-stage filter 640, wherein a first end of the first post-stage filter 620 is connected to a second end of the first voltage dividing unit 420, and a second end of the first post-stage filter 620 is connected to a second end of the second voltage dividing unit 440.
The first end of the second post-stage filter 640 is connected to the second end of the third voltage dividing unit 460, and the second end of the second post-stage filter 640 is connected to the second end of the third voltage dividing unit 460.
The post-stage filter 60 may be a functional circuit connected to the voltage dividing unit, and capable of performing a second filtering process on different sinusoidal signals or different residual signals output by the amplifier circuit, and outputting a second target filtered signal after the second filtering to an output terminal of the encoder output circuit.
The second filtering process may be a process of filtering noise signals of a specific frequency in the target amplified signal output from the amplifier circuit and generating a second target filtered signal. The second target filtered signal may be a signal generated by filtering noise signals in the target amplified signal.
The encoder output circuit provided in this embodiment, through the cooperation of the front-stage filter 50 and the rear-stage filter 60, can filter out the noise signal in the sine differential signal or the cosine differential signal output by the encoder, and also can filter out the noise signal with a specific frequency in the target amplified signal output by the amplifier circuit, thereby improving the signal-to-noise ratio of the transmission signal, improving the accuracy of the output signal acquisition of the encoder, ensuring the working reliability of the motor encoder, and further improving the integration level and stability of the laser galvanometer.
Fig. 4 is a block diagram schematically illustrating the structure of an encoder output circuit in one embodiment.
In the present embodiment, as shown in fig. 4, the encoder output circuit includes a comparator circuit 10, a triode circuit 20, a plurality of amplifier circuits 30, a plurality of voltage dividing units 40, a front stage filter 50, and a rear stage filter 60, and further includes a follower circuit 70.
The follower circuit 70 has a non-inverting input for connection to a power supply, an inverting input, and a compensation signal output connected to the inverting input and to the non-inverting input of either of the amplifier circuits.
The follower circuit 70 may be a functional circuit connected to the power supply and the amplifier circuit, and capable of performing an amplitude compensation process on the first target filtered signal and outputting the first target filtered signal after the amplitude compensation process to the amplifier circuit. The amplitude compensation process may be a process of performing positive compensation or negative compensation adjustment on the amplitude of the first target filtered signal to adjust to the target amplitude.
The encoder output circuit provided in this embodiment performs positive compensation adjustment to adjust to a target amplitude when the amplitude of the first target filtered signal is smaller than a preset value by using the follower circuit 70; when the amplitude of the first target filtering signal is larger than a preset value, negative compensation adjustment is performed to adjust the amplitude to the target amplitude, so that the amplitude stability of the first target filtering signal is effectively improved, the detection stability of a sine signal or a cosine signal output by the encoder is further improved, the working reliability of the encoder is ensured, and the stability of the laser vibrating mirror is improved.
Fig. 5 is a block diagram schematically illustrating the structure of an encoder output circuit in one embodiment.
In the present embodiment, as shown in fig. 4, the encoder output circuit includes a comparator circuit 10, a triode circuit 20, a plurality of amplifier circuits 30, a plurality of voltage dividing units 40, a front stage filter 50, a rear stage filter 60, and a follower circuit 70, and further includes a decoupler 80.
The decoupler 80 is connected to the power supply and comparator circuit 10 and outputs a target power supply signal.
The decoupler 80 may be a functional circuit that is connected to the power supply and comparator circuit 10 and is capable of adjusting the coupling between the power supply and the comparator circuit 10 to maintain the power supply output signal within a predetermined range. The target power signal may be a power output signal after removing the coupling between the power supply and the comparator circuit 10.
The conditions for regulating the coupling between the power supply and the comparator circuit 10 include: coupling noise between the power supply and the comparator circuit 10 is reduced so that the comparator circuit 10 receives a smoothed power supply output signal.
According to the encoder output circuit provided by the embodiment, the decoupler 80 is adopted, so that the amplitude of a power output signal from a power supply to the comparator circuit 10 is maintained within a preset range, the running stability of the comparator circuit 10 is further ensured, the working reliability of the encoder is ensured, and the stability of the laser galvanometer is improved.
Specifically, when the encoder outputs a signal, the first and second ends of the pre-filter 50 receive different sinusoidal signals or different cosine signals output from the encoder, and output the first target filtered signal after the first filtering to the plurality of amplifier circuits 30. The plurality of amplifier circuits 30 amplify the first target filtered signal after the first filtering output from the pre-filter 50, and output the amplified target amplified signal to the voltage dividing unit. The voltage dividing unit divides the target amplified signal and outputs the divided target amplified signal to the post-filter 60. The post-filter 60 performs a second filtering process on the different sinusoidal signals or the different residual signals output from the amplifier circuit, and outputs a second target filtered signal after the second filtering to the output terminal of the encoder output circuit. Meanwhile, the voltage dividing unit also carries out amplitude adjustment processing on the reflux signal from the output end of the encoder output circuit, and outputs the reflux signal with the amplitude adjusted to the amplifier circuit. The follower circuit 70 performs an amplitude compensation process on the first target filtered signal output from the preceding filter 50, and outputs the first target filtered signal after the amplitude compensation process to the amplifier circuit.
In addition, the first input terminal and the second input terminal of the comparator circuit 10 receive different zero signals output by the encoder, perform amplitude comparison processing on the zero signals output by the encoder, and output comparison signals after the amplitude comparison to the triode circuit 20. The triode circuit 20 performs signal inversion processing according to the comparison signal output by the comparator circuit 10, and outputs the inverted signal to the output end of the encoder output circuit. At the same time, decoupler 80 adjusts the coupling between the power supply and comparator circuit 10 to maintain the power supply output signal at a predetermined range.
FIG. 6 is a schematic diagram of an encoder output circuit in one embodiment.
In the present embodiment, the encoder output circuit is applied to a laser galvanometer, and as shown in fig. 6, the encoder output circuit includes a comparator circuit 10, a triode circuit 20, a plurality of amplifier circuits 30, a plurality of voltage dividing units 40, a pre-stage filter 50, a post-stage filter 60, a follower circuit 70, and a decoupler 80.
The front stage filter 50 includes a first front stage filter 520 and a second front stage filter 540, the plurality of amplifier circuits 30 includes a first amplifier circuit 320, a second amplifier circuit 340, a third amplifier circuit 360, and a fourth amplifier circuit 380, and the rear stage filter 60 includes a first rear stage filter 620 and a second rear stage filter 640. The voltage dividing units 40 include a fifth resistor R5, a tenth resistor R10, a fifteenth resistor R15, and a twentieth resistor R20.
As shown in fig. 6, the first amplifier circuit 320 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a first amplifier U1, the second amplifier circuit 340 includes a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and a second amplifier U2, the third amplifier circuit 360 includes an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, and a third amplifier U3, and the fourth amplifier circuit 380 includes a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, and a fourth amplifier U4. The first pre-stage filter 520 includes a first capacitor C1, the second pre-stage filter 540 includes a second capacitor C2, the first post-stage filter 620 includes a third capacitor C3, and the second post-stage filter 640 includes a fourth capacitor C4.
The first end of the first resistor R1 is connected to the first end of the first capacitor C1, the second end of the first resistor R1 is connected to the first end of the second resistor R2 and the positive input end of the first amplifier U1, the second end of the second resistor R2 is connected to the compensation signal output end of the follower circuit 70, the first end of the third resistor R3 is connected to the second end of the first capacitor C1, the second end of the third resistor R3 is connected to the negative input end of the first amplifier U1 and the first end of the fourth resistor R4, the second end of the fourth resistor R4 is connected to the output end of the first amplifier U1 and the first end of the fifth resistor R5, and the second end of the fifth resistor R5 is connected to the first end of the third capacitor C3.
The first end of the sixth resistor R6 is connected to the second end of the first capacitor C1, the second end of the sixth resistor R6 is connected to the first end of the seventh resistor R7 and the positive input end of the amplifier U1, the second end of the seventh resistor R7 is connected to the compensation signal output end of the follower circuit 70, the first end of the eighth resistor R8 is connected to the first end of the first capacitor C1, the second end of the eighth resistor R8 is connected to the negative input end of the amplifier U1 and the first end of the ninth resistor R9, the second end of the ninth resistor R9 is connected to the output end of the second amplifier U2 and the first end of the tenth resistor R10, and the second end of the tenth resistor R10 is connected to the second end of the third capacitor C3.
The first end of the eleventh resistor R11 is connected to the first end of the second capacitor C2, the second end of the eleventh resistor R11 is connected to the first end of the twelfth resistor R12 and the positive input end of the third amplifier U3, the second end of the twelfth resistor R12 is connected to the compensation signal output end of the follower circuit 70, the first end of the thirteenth resistor R13 is connected to the second end of the second capacitor C2, the second end of the thirteenth resistor R13 is connected to the negative input end of the third amplifier U3 and the first end of the fourteenth resistor R14, the second end of the fourteenth resistor R14 is connected to the output end of the third amplifier U3 and the first end of the fifteenth resistor R15, and the second end of the fifteenth resistor R15 is connected to the first end of the fourth capacitor C4.
The first end of the sixteenth resistor R16 is connected to the second end of the second capacitor C2, the second end of the sixteenth resistor R16 is connected to the first end of the seventeenth resistor R17 and the positive input end of the fourth amplifier U4, the second end of the seventeenth resistor R17 is connected to the compensation signal output end of the follower circuit 70, the first end of the eighteenth resistor R18 is connected to the first end of the first capacitor C1, the second end of the eighteenth resistor R18 is connected to the negative input end of the fourth amplifier U4 and the first end of the nineteenth resistor R19, the second end of the nineteenth resistor R19 is connected to the output end of the fourth amplifier U4 and the first end of the twentieth resistor R20, and the second end of the twentieth resistor R20 is connected to the second end of the fourth capacitor C4.
With continued reference to fig. 6, the follower circuit 70 includes a twenty-first resistor R21, a twenty-second resistor R22, and a fifth amplifier U5. The first end of the twenty-first resistor R21 is connected to the positive input end of the power supply, the second end of the twenty-first resistor R21 is connected to the first end of the twenty-second resistor R22 and the positive input end of the fifth amplifier U5, the second end of the twenty-second resistor R22 is grounded, and the negative input end of the fifth amplifier U5 is connected to the output end of the fifth amplifier U5 and the positive input ends of the amplifier circuits 30.
With continued reference to fig. 6, the comparator circuit 10 includes a twenty-third resistor R23, a twenty-fourth resistor R24, and a comparator U6, the triode circuit 20 includes a twenty-fifth resistor R25 and a triode Q, and the decoupler 80 includes a fifth capacitor C5 and a sixth capacitor C6. The encoder output circuit also comprises a feedback resistor R26 and a bias resistor R27, and the encoder detects zero signal output to perform signal inversion, so that the stability of the comparator circuit can be improved.
The first end of the twenty-third resistor R23 is connected to the output end of the encoder, the second end of the twenty-third resistor R23 is connected to the first end of the comparator U6 and the first end of the feedback resistor R26, the first end of the twenty-fourth resistor R24 is connected to the output end of the encoder, the second end of the twenty-fourth resistor R24 is connected to the second end of the comparator U6, the third end of the comparator U6 is connected to the power supply, the first end of the fifth capacitor C5 and the first end of the sixth capacitor C6, the second end of the fifth capacitor C5 is connected to the second end of the sixth capacitor C6 and is grounded, the fourth end of the comparator U6 is connected to the first end of the twenty-fifth resistor R25, the second end of the feedback resistor R26 and the preset output port, the second end of the twenty-fifth resistor R25 is connected to the first end of the triode Q, the fifth end of the comparator U6 is connected to the second end of the triode Q and is grounded, and the third end of the triode Q is connected to the first end of the bias resistor R27 and the preset output port, respectively. Optionally, the first and second ends of the comparator U6 are a negative input end and a positive input end, respectively.
The application also provides a laser galvanometer comprising the encoder output circuit in the embodiment.
The present application also provides a processing apparatus including the encoder output circuit of the above embodiment. Wherein the processing device may be a laser processing device.
The division of the various modules in the encoder output circuit described above is for illustration only, and in other embodiments, the encoder output circuit may be divided into different modules as desired to perform all or part of the functions of the encoder output circuit described above.
According to the encoder output circuit, the laser galvanometer and the processing equipment provided by the embodiment, different zero signals output by the encoder are respectively obtained through the two input ends of the comparator circuit, and when a signal input by the base electrode (namely, a signal output by the comparison signal output end) is in a low level, a signal output by the collector electrode is in a high level in cooperation with a common collector electrode output mode of the triode; when the signal input by the base electrode is in a high level, the signal output by the collector electrode is in a low level, so that different level signal output can be realized when the zero signal output by the encoder is detected, and different level signals are respectively output by the comparison signal output end and the collector electrode of the triode circuit, so that level transition is detected, namely, the zero position is acquired, further, the detection of the rotor shaft position is realized, the high-speed and high-dynamic motion performance of the laser galvanometer motor is effectively ensured, the working reliability of the motor encoder is ensured, the stability of the laser galvanometer is further improved, and the laser galvanometer has important economic value and popularization and practical value.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (10)
1. An encoder output circuit, comprising:
the comparator circuit is provided with a first input end, a second input end and a comparison signal output end, wherein the first input end is used for being connected with the first signal output end of the encoder, the second input end is used for being connected with the second signal output end of the encoder, and the first signal output end and the second signal output end are respectively used for outputting different zero signals;
and the base electrode of the triode circuit is connected with the comparison signal output end, the emitting electrode of the triode circuit is grounded, and the collecting electrode of the triode circuit is used for being connected with a power supply and can be used as an output end.
2. The encoder output circuit of claim 1, further comprising:
the amplifier circuit comprises a non-inverting input end, an inverting input end and an amplifying signal output end, wherein the non-inverting input end is used for being connected with a third signal output end of the encoder, the inverting input end is used for being connected with a fourth signal output end of the encoder, and the third signal output end and the fourth signal output end are respectively used for outputting different sine signals or different cosine signals;
the first end of any one of the voltage dividing units is correspondingly connected with the amplified signal output end of one of the amplifier circuits, and the second end of any one of the voltage dividing units is used for being connected with the output end of the encoder output circuit.
3. The encoder output circuit of claim 2, wherein the plurality of voltage dividing units includes a first voltage dividing unit, a second voltage dividing unit, a third voltage dividing unit, and a fourth voltage dividing unit, and the plurality of amplifier circuits includes:
the non-inverting input end of the first amplifier circuit is used for being connected with the first sinusoidal signal output end of the encoder, the inverting input end of the first amplifier circuit is used for being connected with the second sinusoidal signal output end of the encoder, and the amplified signal output end of the first amplifier circuit is connected with the first end of the first voltage dividing unit;
the non-inverting input end of the second amplifier circuit is used for being connected with the second sinusoidal signal output end of the encoder, the inverting input end of the second amplifier circuit is used for being connected with the first sinusoidal signal output end of the encoder, and the amplified signal output end of the second amplifier circuit is connected with the first end of the second voltage division unit;
the non-inverting input end of the third amplifier circuit is used for being connected with the first cosine signal output end of the encoder, the inverting input end of the third amplifier circuit is used for being connected with the second cosine signal output end of the encoder, and the amplified signal output end of the third amplifier circuit is connected with the first end of the third voltage dividing unit;
and the non-inverting input end of the fourth amplifier circuit is used for being connected with the second cosine signal output end of the encoder, the inverting input end of the fourth amplifier circuit is used for being connected with the first cosine signal output end of the encoder, and the amplified signal output end of the fourth amplifier circuit is connected with the first end of the fourth voltage dividing unit.
4. The encoder output circuit of claim 3, further comprising:
the first end of the first pre-stage filter is connected with the non-inverting input end of the first amplifier circuit and the inverting input end of the second amplifier circuit, and the second end of the first pre-stage filter is connected with the inverting input end of the first amplifier circuit and the non-inverting input end of the second amplifier circuit;
the first end of the second pre-stage filter is connected with the non-inverting input end of the third amplifier circuit and the inverting input end of the fourth amplifier circuit, and the second end of the second pre-stage filter is connected with the inverting input end of the third amplifier circuit and the non-inverting input end of the fourth amplifier circuit.
5. The encoder output circuit of claim 3, further comprising:
the second end of the first post-stage filter is connected with the second end of the second voltage division unit;
the first end of the second post-stage filter is connected to the second end of the third voltage dividing unit, and the second end of the second post-stage filter is connected to the second end of the third voltage dividing unit.
6. The encoder output circuit of claim 2, further comprising:
the follower circuit is provided with a non-inverting input end, an inverting input end and a compensation signal output end, wherein the non-inverting input end is used for being connected with the power supply, and the compensation signal output end is connected with the inverting input end and the non-inverting input end of any amplifier circuit.
7. The encoder output circuit of any of claims 1 to 4, further comprising:
and the decoupler is used for being connected with the power supply and the comparator circuit and outputting a target power supply signal.
8. The encoder output circuit of claim 7, wherein the decoupler comprises a first capacitor and a second capacitor, the first end of the first capacitor and the first end of the second capacitor being configured to be coupled to the power source, the second end of the first capacitor and the second end of the second capacitor being coupled to the power source input of the comparator circuit.
9. A laser galvanometer, comprising:
an encoder output circuit as claimed in any one of claims 1 to 8.
10. A processing apparatus, comprising:
an encoder output circuit as claimed in any one of claims 1 to 8.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321978877.9U CN220794265U (en) | 2023-07-25 | 2023-07-25 | Encoder output circuit, laser galvanometer and processing equipment |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321978877.9U CN220794265U (en) | 2023-07-25 | 2023-07-25 | Encoder output circuit, laser galvanometer and processing equipment |
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| CN220794265U true CN220794265U (en) | 2024-04-16 |
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| CN202321978877.9U Active CN220794265U (en) | 2023-07-25 | 2023-07-25 | Encoder output circuit, laser galvanometer and processing equipment |
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