CN220774382U

CN220774382U - Wafer packaging structure

Info

Publication number: CN220774382U
Application number: CN202322474788.7U
Authority: CN
Inventors: 赖芳奇; 欧家林; 赵飞龙; 李媛媛; 李帅; 房玉亮; 任鹏; 庾亚运; 谢春雷
Original assignee: Guangdong Yuehai Integrated Technology Co ltd
Current assignee: Guangdong Yuehai Integrated Technology Co ltd
Priority date: 2023-09-12
Filing date: 2023-09-12
Publication date: 2024-04-12
Anticipated expiration: 2033-09-12

Abstract

The utility model belongs to the technical field of semiconductor manufacturing, and discloses a wafer packaging structure. The wafer packaging structure comprises a wafer, a connecting layer, a silicon lens and a tin ball, wherein the connecting layer is arranged on the wafer; the silicon lens comprises a bottom layer and spherical protruding parts, the bottom layer is connected with the wafer in a bonding way through the connecting layer, and the spherical protruding parts are spaced and uniformly distributed on one side, far away from the connecting layer, of the bottom layer; the solder balls are arranged on one side of the wafer away from the connecting layer. According to the wafer packaging structure provided by the utility model, the silicon lens is directly arranged on the connecting layer, and plays roles of filtering and converging light, so that the manufacturing cost of the silicon lens is low, the power consumption is low, the overall structure is simplified, and the manufacturing cost is reduced.

Description

Wafer packaging structure

Technical Field

The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a wafer packaging structure.

Background

At present, electronic intelligent products provide great convenience for life of people, and the chip determines the service life of the intelligent products. The semiconductor manufacturing is divided into three stages, wherein the upstream is chip design, the middle stream is chip manufacturing, and the downstream is chip sealing and testing. Although the downstream chip package is the end of the whole semiconductor process, the function is critical, and the finished product of the chip of the electronic intelligent product is from the chip package company.

In the conventional optical chip packaging process, a wafer is usually cut into individual dies, and then the individual dies are encapsulated. Fig. 1 is a schematic diagram of a conventional chip package structure after encapsulation, and the encapsulation process includes: the optical chip 2' is attached to the front surface of the substrate 1' and connected by the connection line 4', the connection layer 3' is attached to the surface of the optical chip 2', the glass 5' is attached to the connection layer 3', the lens 6' is mounted on the glass 5', and finally the solder ball 7' is mounted on the back surface of the substrate 1 '. The glass 5' acts as a filter, which can make the image clear, reduce the aberration, obtain the focal length required for photographing, and realize other optical related functions, but it is only transparent to infrared light, and is not suitable for ordinary light. The lens 6' is used for converging light and forming an image of a scene on the photosensitive area of the optical chip 2', and most of the lenses 6' are made of plastic grease. The existing chip packaging structure is complex in structure, high in manufacturing cost, complex in processing process flow and high in manufacturing process risk.

Disclosure of Invention

The utility model aims to provide a wafer packaging structure, which aims to solve the problems of long process flow, complex structure and high manufacturing cost of the traditional packaging structure, simplify the packaging process, effectively reduce the manufacturing process risk and improve the packaging efficiency.

To achieve the purpose, the utility model adopts the following technical scheme:

a wafer package structure, comprising:

a wafer;

the connecting layer is arranged on the wafer;

the silicon lens comprises a bottom layer and spherical protruding parts, wherein the bottom layer is connected with the wafer in a bonding way through the connecting layer, and the spherical protruding parts are uniformly distributed at intervals on one side, far away from the connecting layer, of the bottom layer;

and the solder balls are arranged on one side of the wafer away from the connecting layer.

Optionally, the thickness of the bottom layer is 200-400 μm; the thickness of the spherical protruding part is 300-500 mu m.

Optionally, the thickness of the wafer is 80-150 μm.

Optionally, a plurality of equidistant conical grooves are formed in one side, away from the connecting layer, of the wafer, and each conical groove is formed in the middle line of two adjacent spherical protruding portions.

Optionally, a plurality of conical grooves are formed in one side, far away from the connecting layer, of the wafer, the conical grooves are arranged at equal intervals, two spherical protruding portions form a spherical protruding portion group, and each conical groove is formed in the middle line of two adjacent spherical protruding portion groups.

Optionally, a bonding pad is disposed at the bottom of the conical groove, a circuit layer is disposed on one side of the wafer away from the connection layer, and the bonding pad is used for conducting the circuit layer.

Optionally, a solder mask layer is coated on a side, far away from the wafer, of the circuit layer, and a bonding pad position for connecting with the solder ball is arranged on the solder mask layer.

Optionally, each two solder balls form a solder ball group, and each solder ball group is disposed between adjacent conical grooves.

Optionally, a protective layer is further disposed between the circuit layer and the solder mask layer, and the protective layer is used for preventing the circuit layer from being corroded.

Optionally, the circuit layer is provided as a copper layer.

The utility model has the beneficial effects that: according to the wafer packaging structure provided by the utility model, the silicon lens is directly arranged on the connecting layer, the silicon lens comprises the bottom layer and the spherical protruding parts, the bottom layer is connected with the wafer in a bonding way through the connecting layer, the spherical protruding parts are uniformly distributed on one side of the bottom layer far away from the connecting layer at intervals, the silicon lens simultaneously plays roles of filtering and converging light, and the silicon lens is low in manufacturing cost and power consumption, the whole structure is simplified, and the manufacturing cost is reduced.

Drawings

FIG. 1 is a schematic diagram of a conventional chip package structure;

FIG. 2 is a schematic diagram of a wafer package structure according to an embodiment of the present utility model;

FIG. 3 is a schematic diagram of a structure of a silicon wafer coated with photoresist according to an embodiment of the present utility model;

FIG. 4 is a schematic diagram of a structure of a photoresist formed with a spherical structure according to an embodiment of the present utility model;

FIG. 5 is a schematic diagram of an etching process for a silicon wafer and photoresist according to an embodiment of the present utility model;

fig. 6 is a schematic structural diagram of a silicon lens provided in an embodiment of the present utility model after being disposed on a connection layer;

fig. 7 is a schematic diagram of a structure of a thinned wafer according to an embodiment of the present utility model;

FIG. 8 is a schematic diagram of a structure of a wafer after sequentially preparing a tapered groove, a circuit layer, a protective layer and a solder mask layer according to an embodiment of the present utility model;

fig. 9 is a schematic structural diagram of a solder ball according to an embodiment of the present utility model;

fig. 10 is a schematic diagram of a single lens wafer package structure according to an embodiment of the present utility model;

fig. 11 is a schematic diagram of a dual-lens wafer package structure according to an embodiment of the utility model.

In the figure:

1', a substrate; 2', an optical chip; a 3' connection layer; 4', connecting lines; 5', glass; 6', a lens; 7', solder balls;

100. a wafer; 110. a conical groove; 200. a connection layer; 300. a silicon lens; 310. a bottom layer; 320. a spherical projection; 400. solder balls; 500. a silicon wafer; 600. a bonding pad; 700. a solder mask layer; 710. a pad position; 800. a photoresist; 900. a circuit layer; 1000. a protective layer; 1100. single grains.

Detailed Description

The utility model is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the utility model and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present utility model are shown in the drawings.

In the description of the present utility model, unless explicitly stated and limited otherwise, the terms "connected," "connected," and "fixed" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present utility model will be understood in specific cases by those of ordinary skill in the art.

In the present utility model, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other through additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.

In the description of the present embodiment, the terms "upper", "lower", "right", etc. orientation or positional relationship are based on the orientation or positional relationship shown in the drawings, and are merely for convenience of description and simplicity of operation, and do not indicate or imply that the apparatus or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the utility model. Furthermore, the terms "first," "second," and the like, are used merely for distinguishing between descriptions and not for distinguishing between them.

The embodiment provides a wafer packaging structure, which aims to solve the problems of long process flow, complex structure and high manufacturing cost of the conventional packaging structure, simplify the packaging process, effectively reduce the manufacturing process risk and improve the packaging efficiency.

As shown in fig. 2, the wafer package structure includes a wafer 100, a connection layer 200, a silicon lens 300 and a solder ball 400, wherein the connection layer 200 is disposed on the wafer 100; the silicon lens 300 comprises a bottom layer 310 and spherical protruding parts 320, wherein the bottom layer 310 is connected with the wafer 100 in a bonding way through the connecting layer 200, and a plurality of spherical protruding parts 320 are spaced and uniformly distributed on one side, far away from the connecting layer 200, of the bottom layer 310; the solder balls 400 are disposed in plurality, and the solder balls 400 are disposed on a side of the wafer 100 away from the connection layer 200.

In the wafer packaging structure provided in this embodiment, the silicon lens 300 is directly disposed on the connection layer 200, the silicon lens 300 includes the bottom layer 310 and the spherical protruding portions 320, the bottom layer 310 is connected with the wafer 100 by bonding through the connection layer 200, the spherical protruding portions 320 are uniformly distributed on one side of the bottom layer 310 far away from the connection layer 200, the silicon lens 300 plays the roles of filtering and converging light, and the silicon lens 300 has the advantages of low manufacturing cost, low power consumption, simplified overall structure and reduced manufacturing cost.

Optionally, the thickness of the bottom layer 310 is 200 μm to 400 μm; the thickness of the spherical protrusion 320 is 300 μm to 500 μm; the thickness of the wafer 100 is 80 μm to 150 μm. The thickness of the spherical protrusion 320 is 300 μm to 500 μm so that the silicon lens 300 sufficiently plays a role of converging light. The specific thicknesses of the bottom layer 310, the spherical protrusions 320, and the wafer 100 may be determined according to the actual functional requirements of the product during the actual design process.

In this embodiment, a plurality of tapered grooves 110 are disposed at equal intervals on a side of the wafer 100 away from the connection layer 200, and each tapered groove 110 is disposed on a middle line of two adjacent spherical protruding portions 320. Alternatively, a plurality of tapered grooves 110 are disposed at equal intervals on a side of the wafer 100 away from the connection layer 200, and two spherical protrusions 320 form a spherical protrusion group, and each tapered groove 110 is disposed on a middle line of two adjacent spherical protrusion groups. The tapered recess 110 cooperates with a scribe line on the wafer 100 for scribe the wafer package to divide the wafer package into a plurality of individual dies 1100. According to different product designs and requirements, a single spherical protruding part 320 is arranged between every two adjacent conical grooves 110 in single-lens packaging, and a spherical protruding part group is arranged between every two adjacent conical grooves 110 in double-lens packaging, namely, two spherical protruding parts 320 are arranged between every two adjacent conical grooves 110.

Further, a bonding pad 600 is disposed at the bottom of the tapered recess 110, a circuit layer 900 is disposed on a side of the wafer 100 away from the connection layer 200, and the bonding pad 600 is used for conducting the circuit layer 900. The arrangement of the circuit layer 900 and the bonding pad 600 provides the wafer 100 with a function of performing data processing on light. In this embodiment, two pads 600 disposed at intervals and symmetrical along the middle line of two adjacent spherical protruding portions 320 (or the middle line of two adjacent spherical protruding portions), each pad 600 being used for connecting the circuit layer 900 of a corresponding single die 1100, are disposed at the bottom of the tapered recess 110.

Alternatively, every second solder ball 400 forms a solder ball set, each set being disposed between adjacent tapered recesses 110. The number of the solder balls 400 included in the solder ball group can be set according to the requirement, and the requirement of subsequent package welding communication can be met.

In this embodiment, a solder mask 700 is coated on a side of the circuit layer 900 away from the wafer 100, and a pad 710 for connecting with the solder ball 400 is disposed on the solder mask 700. Further, a protective layer 1000 is further disposed between the circuit layer 900 and the solder mask 700, where the protective layer 1000 is used to prevent the circuit layer 900 from being corroded.

As shown in fig. 3-11, the present embodiment further provides a method for manufacturing a wafer package structure, taking a single lens package structure as an example, including the following steps:

s1, providing a silicon wafer 500 and a wafer 100;

s2, coating a photoresist 800 on the silicon wafer 500, and patterning the photoresist 800;

illustratively, referring to fig. 3, a photoresist 800 is coated on a silicon wafer 500 using a coater, and after the coating is completed, the photoresist 800 is patterned by exposure and development.

S3, forming a spherical structure of the photoresist 800 through a reflow process;

s4, etching the silicon wafer 500 and the photoresist 800 to remove the photoresist 800, and enabling the silicon wafer 500 to form a silicon lens 300, wherein the silicon lens 300 comprises a bottom layer 310 and a plurality of spherical protruding parts 320 which are uniformly distributed on the bottom layer 310 at intervals;

in this embodiment, referring to fig. 5, SF is used ₆ /C ₄ F ₈ The gas etches the surface of the silicon wafer 500, the gas can etch the surface of the silicon wafer 500 while attacking the photoresist 800, the etching rate ratio of the photoresist 800 to the silicon wafer 500 is 1:1 until the photoresist 800 on the surface of the silicon wafer 500 is etched, and the pattern of the photoresist 800 is transferred to the silicon wafer 500, so that the silicon lens 300 is finally formed.

S5, coating a connecting layer 200 on the wafer 100, and arranging a bottom layer 310 of the silicon lens 300 on the connecting layer 200;

referring to fig. 6, alternatively, the connection layer 200 may be a connection film or a connection paste, which bonds the silicon lens 300 and the wafer 100 together.

S6, arranging a solder ball 400 on one side of the wafer 100 away from the silicon lens 300;

s7, cutting the wafer 100 into a plurality of single dies 1100 along the dicing lines on the wafer 100.

At dicing, referring to fig. 9 and 10, the entire wafer 100 is singulated into a plurality of individual die 1100 using a dicing machine to form the final product. Referring to fig. 11, when dicing the dual-lens wafer package structure, a dicing machine is also used to divide the dual-lens wafer package structure into a plurality of single dies 1100 along dicing streets of the wafer 100.

According to the preparation method of the wafer packaging structure, the silicon lens 300 is prepared through the etching process, the processing process is simple and convenient, the connecting layer 200 is prepared on the surface of the wafer 100, the silicon lens 300 is adhered to the connecting layer 200, and finally the wafer 100 is cut to obtain a plurality of single crystal grains 1100, so that the process steps are few, the processing risk is effectively reduced, the use reliability of a product is further improved, the consumption of manpower and material resources is reduced, and the packaging efficiency is improved.

Optionally, after the bottom layer 310 of the silicon lens 300 is disposed on the connection layer 200, before the solder balls 400 are disposed, the method further includes:

preparing a plurality of conical grooves 110 on one side of the wafer 100 away from the silicon lens 300, wherein each conical groove 110 is arranged on the middle line of two adjacent spherical protruding parts 320;

a circuit layer 900, a protective layer 1000 and a solder mask 700 are sequentially prepared on one side of the wafer 100 far from the silicon lens 300, and a bonding pad 710 for connecting with the solder ball 400 is reserved on the solder mask 700.

Specifically, referring to fig. 8 and 9, the dicing streets and silicon regions near the dicing streets on the side of the wafer 100 away from the silicon lens 300 are exposed, a positive photoresist 800 is applied to other regions of the wafer 100 to protect the other regions, the dicing streets and the silicon regions near the dicing streets are etched with an etching gas to form a tapered recess 110, and the bonding pads 600 at the bottom of the tapered recess 110 are exposed to provide for electrical conduction and metal interconnection. Next, a circuit layer 900 is prepared on one side of the wafer 100 far from the silicon lens 300 through an exposure and development process, the circuit layer 900 is arranged between the adjacent conical grooves 110, the circuit layer 900 is connected with the bonding pads 600, a protective layer 1000 is plated on the circuit layer 900 through a chemical deposition method, finally, a layer of solder mask 700 is coated on the protective layer 1000 to cover the circuit, a bonding pad position 710 is reserved, and a UBM (Under Bump Metallization ) bonding pad of a ball to be planted is exposed, so that the solder ball 400 is prepared. In this embodiment, the circuit layer 900 is a copper circuit, and the protection layer 1000 includes nickel and gold. Optionally, when the solder ball 400 is prepared, solder paste is printed on the surface of the UBM pad, and the solder ball 400 is formed through reflow soldering.

Preferably, referring to fig. 7, after the bottom layer 310 of the silicon lens 300 is disposed on the connection layer 200, the side of the wafer 100 away from the silicon lens 300 needs to be thinned before the plurality of tapered recesses 110 are formed on the side of the wafer 100 away from the silicon lens 300. The wafer 100 is thinned by a grinder, and the thickness of the wafer 100 is usually about 720 μm before the thinning, and the thinning serves to thin the thickness of the wafer 100 to the thickness of the optical chip.

It is to be understood that the above examples of the present utility model are provided for clarity of illustration only and are not limiting of the embodiments of the present utility model. Various obvious changes, rearrangements and substitutions can be made by those skilled in the art without departing from the scope of the utility model. It is not necessary here nor is it exhaustive of all embodiments. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the utility model are desired to be protected by the following claims.

Claims

1. The wafer packaging structure is characterized by comprising:

a wafer (100);

a connection layer (200) provided on the wafer (100);

the silicon lens (300) comprises a bottom layer (310) and spherical protruding parts (320), wherein the bottom layer (310) is connected with the wafer (100) in a bonding way through the connecting layer (200), and a plurality of spherical protruding parts (320) are spaced and uniformly distributed on one side, far away from the connecting layer (200), of the bottom layer (310);

and a plurality of solder balls (400) are arranged, and the solder balls (400) are arranged on one side of the wafer (100) away from the connecting layer (200).

2. The wafer package structure according to claim 1, wherein the thickness of the bottom layer (310) is 200 μm to 400 μm; the thickness of the spherical protruding part (320) is 300-500 μm.

3. The wafer package structure according to claim 1, wherein the thickness of the wafer (100) is 80 μm to 150 μm.

4. The wafer packaging structure according to claim 1, wherein a plurality of tapered grooves (110) are arranged at equal intervals on a side of the wafer (100) away from the connection layer (200), and each tapered groove (110) is arranged on a middle line of two adjacent spherical protruding parts (320).

5. The wafer packaging structure according to claim 1, wherein a plurality of tapered grooves (110) are arranged at equal intervals on a side, away from the connection layer (200), of the wafer (100), two spherical protruding portions (320) form one spherical protruding portion group, and each tapered groove (110) is arranged on a middle line of two adjacent spherical protruding portion groups.

6. The wafer packaging structure according to claim 4 or 5, wherein a bonding pad (600) is disposed at a bottom of the tapered recess (110), a circuit layer (900) is disposed on a side of the wafer (100) away from the connection layer (200), and the bonding pad (600) is used for conducting the circuit layer (900).

7. The wafer package structure according to claim 4 or 5, wherein each two solder balls (400) form a solder ball group, each solder ball group being disposed between adjacent ones of the tapered recesses (110).

8. The wafer packaging structure according to claim 6, wherein a solder mask layer (700) is coated on a side of the circuit layer (900) away from the wafer (100), and a pad position (710) for connecting with the solder ball (400) is provided on the solder mask layer (700).

9. The wafer packaging structure according to claim 8, wherein a protective layer (1000) is further disposed between the circuit layer (900) and the solder mask layer (700), and the protective layer (1000) is used for preventing the circuit layer (900) from being corroded.

10. The wafer package structure according to claim 9, wherein the wiring layer (900) is provided as a copper layer.