CN220731484U

CN220731484U - Chip assembly

Info

Publication number: CN220731484U
Application number: CN202322343480.9U
Authority: CN
Inventors: 贺婷; 范丽萍; 曾旭
Original assignee: Yuexin Semiconductor Technology Co ltd
Current assignee: Yuexin Semiconductor Technology Co ltd
Priority date: 2023-08-29
Filing date: 2023-08-29
Publication date: 2024-04-05
Anticipated expiration: 2033-08-29

Abstract

The utility model provides a chip assembly, and relates to the technical field of semiconductors. The chip assembly comprises a chip and a stabilizing part, the stabilizing part coats the chip, the chip comprises a first metal layer and a substrate, the substrate is attached to the first metal layer, the stabilizing part coats the first metal layer and the substrate, and the thickness of the stabilizing part is larger than that of the chip; the chip assembly further comprises a first lead and a second lead, wherein the first lead and the second lead are connected with the chip, a part of the first lead is located in the stabilizing portion, another part of the first lead extends out of the stabilizing portion, a part of the second lead is located in the stabilizing portion, and another part of the second lead extends out of the stabilizing portion. The chip assembly can complete back failure positioning by manufacturing the chip as an inverted chip under the condition of no equipment or jig, and solves the problem that the chip is likely to be cracked due to the fact that the metal layer on the back of the chip is directly ground to generate great stress in the chip.

Description

Chip assembly

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a chip assembly.

Background

In the field of semiconductor manufacturing, as the IC process is developed toward small-sized multi-level, in the process of chip Failure Analysis (FA), in order to improve the accuracy of failure analysis, EMMI (Emission Microscope, micro light microscope) and OBIRCH (Optical Beam Induced Resistance Change, beam induced resistance change) are generally required to be used to locate failure points of an abnormal chip, and the mechanism of chip failure is determined by combining the original design condition of the chip.

In failure positioning, it is often impossible to perform front positioning due to some restrictions. For example, the limitation of the packaging structure, such as the novel flip chip packaging adopted by the very large scale integrated circuit and the lead-on-chip packaging adopted by the memory, is a new challenge for the front positioning of the chip; the development of the multilayer metal wiring structure of the chip prevents light transmission and is not suitable for front positioning.

The common front side light reflection means that photons penetrate through the relatively transparent dielectric layer and exit from the front side of the chip through the dielectric layer between metal wires or along the metal wires. If infrared or near infrared light is used as the light source of the reflected image, the chip can be placed upside down due to the transparency of silicon to infrared and near infrared bands, so that the light source can be incident from the back of the chip to obtain the reflected image. The luminous image is emitted from the back surface, so that absorption and reflection of the multilayer metal wiring structure on the front surface of the chip are avoided, and the positioning of failure points from the back surface of the chip can be realized. Backside failure location is generally more accurate than front side failure location due to the avoidance of interference from surface metallization.

The current method for realizing the back failure positioning is divided into three types:

(1) The inverted micro light microscope can realize the function of scanning failure points from the front lower needle back, but the back analysis instrument is more expensive.

(2) The chip internal circuit is connected with external pins through leads and is packaged to form COB, and the chip can be inverted to scan the back failure point through the redefinition mode of the pins. This approach requires the use of a bonding tool.

(3) Back type wafer failure positioning jig.

The above methods (1) and (2) require expensive equipment, and the method (3) requires additional jigs, and all three methods raise the cost of locating the back failure.

In addition, taking MOS (MOS, abbreviation of MOSFET, MOSFET metal-oxide semiconductor field effect transistor, abbreviated as metal oxide semiconductor field effect transistor) products as an example, a thinning back-gold process is generally adopted in MOS products to deposit metal layers formed by Ti, niV and Ag on a silicon substrate in sequence, and the metal layers block photon transmission when EMMI or OBIRCH technology is used for back failure positioning. The backside of the chip is therefore lapped to expose the silicon wafer substrate enclosed in the package, allowing photons to pass through the substrate and be received by the detector, thereby achieving defect localization. However, grinding the metal layer directly on the back of the chip can create significant stresses within the chip that can lead to chip chipping.

Disclosure of Invention

In view of this, the present application provides a chip assembly to accomplish the back failure location by making the chip itself as an inverted chip without equipment or a jig, and solve the problem that directly grinding the metal layer on the back of the chip may generate a great stress to the inside of the chip, which may cause chip cracking.

The application provides a chip assembly, the chip assembly includes chip and stabilizer, the cladding of stabilizer the chip, the chip includes first metal level and substrate, the substrate with first metal level laminating, the stabilizer cladding first metal level and the substrate, the thickness of stabilizer is greater than the thickness of chip;

the chip assembly further comprises a first lead and a second lead, wherein the first lead and the second lead are connected with the chip, a part of the first lead is located inside the stabilizing part, another part of the first lead extends out of the stabilizing part, a part of the second lead is located inside the stabilizing part, and another part of the second lead extends out of the stabilizing part.

Preferably, the orthographic projection of the chip on the stabilizing portion is located inside the stabilizing portion.

Preferably, the chip further comprises a source electrode and a grid electrode, the source electrode and the grid electrode are respectively positioned at two ends of the upper surface of the chip, the first lead wire is connected with the source electrode, and the second lead wire is connected with the grid electrode.

Preferably, the chip further comprises a second metal layer, the second metal layer is attached to the side of the substrate, which is opposite to the first metal layer, and the second metal layer is covered by the stabilizing part.

Preferably, the thickness of the first metal layer is greater than the thickness of the second metal layer.

Preferably, the chip further comprises a drain electrode, and the drain electrode is located on the lower surface of the chip.

Preferably, the stabilizing portion has a cylindrical shape, and a diameter of the stabilizing portion is greater than or equal to a maximum dimension of the chip.

Preferably, the first lead extends from a side portion of the stabilizing portion to an end portion of the stabilizing portion through an inside of the stabilizing portion, and the second lead extends from a side portion of the stabilizing portion to an end portion of the stabilizing portion through an inside of the stabilizing portion.

Preferably, the stabilizing portion is a crystal glue layer.

In the chip assembly of this application, the part and the first metal level that are located one side of first metal level back to the substrate of stabilizer cladding chip can be ground before using EMMI or OBIRCH to detect for the chip assembly is overturned afterwards for stabilizer bearing chip, can power up the chip through first lead wire and second lead wire this moment, and then carries out back failure location, need not extra equipment or tool, has reduced the cost of back failure location. The thickness of the stabilizing part is greater than the thickness of the chip, and the integral strength of the chip assembly can be improved through the stabilizing part, so that the stress of the chip is reduced, and the chip is prevented from being broken in the process of grinding the first metal layer.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered limiting the scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 shows a schematic diagram of a chip assembly of an embodiment of the utility model;

FIG. 2 shows a schematic diagram of the structure of a chip according to an embodiment of the utility model;

FIG. 3 shows a cross-sectional view of the chip of FIG. 2 taken along line A-A';

fig. 4 is a schematic diagram showing a state after the chip bonding is completed;

FIG. 5 shows a relative position diagram of a die and a chip;

fig. 6 shows a schematic view of a state in which the stabilizing portion is formed;

fig. 7 is a schematic view showing a structure when polishing is performed;

fig. 8 shows a schematic diagram of the state of the chip assembly at the time of detection.

Icon: 1-chip; 11-a substrate; 12-a first metal layer; 13-a second metal layer; 14-source electrode; 15-grid electrode; 16-drain electrode; 2-a stabilizing section; 3-a first lead; 4-a second lead; 5-a mold; 6-sand paper; 7-a glue bearing container; 8-a detector lens; 9-probe.

Detailed Description

The following detailed description is provided to assist the reader in obtaining a thorough understanding of the methods, apparatus, and/or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatuses, and/or systems described herein will be apparent after an understanding of the present disclosure. For example, the order of operations described herein is merely an example, and is not limited to the order set forth herein, but rather, obvious variations may be made upon an understanding of the present disclosure, other than operations that must occur in a specific order. In addition, descriptions of features known in the art may be omitted for the sake of clarity and conciseness.

The features described herein may be embodied in different forms and should not be construed as limited to the examples described herein. Rather, the examples described herein have been provided solely to illustrate some of the many possible ways of implementing the methods, devices, and/or systems described herein that will be apparent after a review of the disclosure of the present application.

In the entire specification, when an element (such as a layer, region or substrate) is described as being "on", "connected to", "bonded to", "over" or "covering" another element, it may be directly "on", "connected to", "bonded to", "over" or "covering" another element or there may be one or more other elements interposed therebetween. In contrast, when an element is referred to as being "directly on," directly connected to, "or" directly coupled to, "another element, directly on," or "directly covering" the other element, there may be no other element intervening therebetween.

As used herein, the term "and/or" includes any one of the listed items of interest and any combination of any two or more.

Although terms such as "first," "second," and "third" may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections should not be limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first member, component, region, layer or section discussed in examples described herein could also be termed a second member, component, region, layer or section without departing from the teachings of the examples.

For ease of description, spatially relative terms such as "above … …," "upper," "below … …," and "lower" may be used herein to describe one element's relationship to another element as illustrated in the figures. Such spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" or "upper" relative to another element would then be oriented "below" or "lower" relative to the other element. Thus, the term "above … …" includes both orientations "above … …" and "below … …" depending on the spatial orientation of the device. The device may also be otherwise positioned (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing various examples only and is not intended to be limiting of the disclosure. Singular forms also are intended to include plural forms unless the context clearly indicates otherwise. The terms "comprises," "comprising," and "having" are intended to specify the presence of stated features, integers, operations, elements, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, operations, elements, and/or groups thereof.

Variations from the shapes of the illustrations as a result, of manufacturing techniques and/or tolerances, are to be expected. Accordingly, the examples described herein are not limited to the particular shapes shown in the drawings, but include changes in shapes that occur during manufacture.

The features of the examples described herein may be combined in various ways that will be apparent after an understanding of the disclosure of the present application. Further, while the examples described herein have a variety of configurations, other configurations are possible as will be apparent after an understanding of the present disclosure.

The application provides a chip assembly, as shown in fig. 1, the chip assembly includes chip 1 and stable portion 2, and stable portion 2 cladding chip 1, and chip 1 includes first metal layer 12 and substrate 11, and substrate 11 is laminated with first metal layer 12, and first metal layer 12 and substrate 11 are covered by stable portion 2, and the thickness of stable portion 2 is greater than the thickness of chip 1. In the chip assembly of this application, the chip 1 is wrapped to the stabilizer 2, before using EMMI or OBIRCH to detect, can grind the part and the first metal layer 12 of the side that the stabilizer 2 is located the first metal layer 12 back to the substrate 11, later upset chip assembly for the stabilizer 2 holds chip 1, can carry out back failure location this moment, need not extra equipment or tool, has reduced the cost of back failure location. Meanwhile, the thickness of the stabilizing part 2 is larger than that of the chip 1, so that the integral strength of the chip assembly can be improved through the stabilizing part 2, the stress of the chip 1 is reduced, and the chip 1 is prevented from being broken in the process of grinding the first metal layer 12.

Further, as shown in fig. 1, the orthographic projection of the chip 1 on the stabilizing portion 2 is located inside the stabilizing portion 2, that is, the outer edge of the stabilizing portion 2 is located outside the outer edge of the chip 1, which makes the chip 1 completely covered inside the stabilizing portion 2, so that the structural strength of the whole chip assembly can be ensured.

Preferably, the stabilizing portion 2 has a cylindrical shape, and the diameter of the stabilizing portion 2 is greater than or equal to the largest dimension of the chip 1. Specifically, the chip 1 has a rectangular parallelepiped shape, and both the upper end surface and the lower end surface of the chip 1 are rectangular, and the diameter of the stabilizing section 2 is greater than or equal to the length of the diagonal line of the rectangle. In this way, the encapsulation of the chip 1 by the stabilizer 2 is further ensured.

Alternatively, the shape of the stabilizing portion 2 is not limited thereto, and the stabilizing portion 2 may be any shape that can satisfy the condition that the orthographic projection of the chip 1 on the stabilizing portion 2 is located inside the stabilizing portion 2, for example, the stabilizing portion 2 may be in a rectangular parallelepiped shape or the like.

In the embodiment of the present application, as shown in fig. 2, the chip 1 includes a source 14, a gate 15 and a drain 16, where the source 14 and the gate 15 are located on the same side of the chip 1, the source 14 and the drain 16 are located on two sides of the chip 1, that is, the source 14 and the gate 15 are located on the upper surface of the chip 1, the drain 16 is located on the lower surface of the chip 1, and the source 14 and the gate 15 are located on two ends of the same side of the chip 1.

Further, as shown in fig. 1, the chip assembly further includes a first lead 3 and a second lead 4, the first lead 3 is connected to the source 14, the second lead 4 is connected to the gate 15, a portion of the first lead 3 is located inside the stabilizing portion 2, another portion of the first lead 3 protrudes from the stabilizing portion 2, a portion of the second lead 4 is located inside the stabilizing portion 2, and another portion of the second lead 4 protrudes from the stabilizing portion 2.

In the embodiment of the present application, the first lead 3 extends from the end of the cylindrical stabilizer 2 to the side of the stabilizer 2, and the second lead 4 extends from the end of the cylindrical stabilizer 2 to the side of the stabilizer 2. By arranging the first lead 3 and the second lead 4, the source 14 and the grid 15 can be respectively powered through the first lead 3 and the second lead 4 in the process of chip detection, and then the detection of the chip 1 is realized.

Further, as shown in fig. 3, the chip 1 further includes a second metal layer 13, where the second metal layer 13 is attached to a side portion of the substrate 11 opposite to the first metal layer 12, and the second metal layer 13 is covered by the stabilizing portion 2, that is, in the chip assembly of the present application, a side surface of the first metal layer 12 is covered by the stabilizing portion 2, and the substrate 11, the first metal layer 12, and the second metal layer 13 are covered by the stabilizing portion 2. When the chip assembly is inverted, the end face, opposite to the second metal layer 13, of the first metal layer 12 can be located at the upper end, and at the moment, the back failure positioning of the chip 1 can be directly achieved by using EMMI (or OBIRCH), so that new detection equipment is not required to be purchased additionally, and the economic cost is reduced.

Alternatively, the first metal layer 12 may be a metal layer formed by sequentially depositing Ti, niV, and Ag on a silicon substrate, the second metal layer 13 may be a metal layer structure formed by sequentially depositing silicon oxide and silicon nitride, and the substrate 11 may be a silicon substrate.

In the embodiment of the present application, as shown in fig. 3, the thickness of the first metal layer 12 is greater than the thickness of the second metal layer 13, so that grinding of the first metal layer 12 before the chip 1 is inspected can be facilitated.

Preferably, the stabilizing portion 2 is a crystal glue layer, that is, the stabilizing portion 2 may be a layered structure formed by curing crystal glue.

Taking the chip 1 as a MOS product as an example, before the chip 1 is tested, a chip assembly needs to be manufactured first, and the manufacturing steps of the chip assembly are as follows:

1. the chip 1 to be tested is wire-bonded, namely, the source electrode 14 and the grid electrode 15 are wire-bonded and led out to form a first lead 3 and a second lead 4, and at the moment, the state of the chip 1 is shown in fig. 4;

2. the chip 1 is covered with a cylindrical hollow mold 5, and the first lead 3 and the second lead 4 are led out through holes in the side surfaces of the mold 5, and the state of the chip 1 and the mold 5 is shown in fig. 5. Then, as shown in fig. 6, the die 5 is filled with the crystal glue by using the glue container 7, the crystal glue is solidified to form a chip assembly, and then the chip assembly is removed from the die 5.

As shown in fig. 7, when the chip assembly of the present application is ground, the side of the chip assembly where the first metal layer 12 is located may be placed toward the sandpaper 6, and then ground to the back surface (lower surface in view of fig. 7) of the substrate 11 using the sandpaper 6. Then, as shown in fig. 8, the chip 1 is placed under the detector lens 8 (the detector lens may be an EMMI detector lens or an OBIRCH detector lens), the micro probe 9 is used to power up the drain electrode 16 on the back of the chip 1, and the first lead 3 and the second lead 4 are used to power up the source electrode 14 and the gate electrode 15, so as to further realize the detection of the chip 1.

It should be noted that, the chip 1 in the chip assembly of the present application is not limited to a MOS product, and the chip 1 may be any chip that needs to perform back failure positioning, for example, a Logic chip, a CIS (CMOS image sensor, which is a complementary metal oxide semiconductor sensor, also referred to as a CMOS image sensor) and other chips, where the Logic chip, the CIS and other chips are connected to electrodes of the chip assembly through leads, and then are wrapped in a stabilizing portion, so as to form a chip assembly, and such a chip assembly may perform failure positioning by using EMMI or OBIRCH from the back after being turned over.

The chip assembly of this application can promote the holistic intensity of chip assembly through setting up the stabilizer to reduce the stress of chip, and then avoided taking place cracked at the in-process chip of grinding first metal level.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present utility model, and not for limiting the same; although the utility model has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the utility model.

Claims

1. The chip assembly is characterized by comprising a chip and a stabilizing part, wherein the stabilizing part is used for coating the chip, the chip comprises a first metal layer and a substrate, the substrate is attached to the first metal layer, the stabilizing part is used for coating the first metal layer and the substrate, and the thickness of the stabilizing part is larger than that of the chip;

2. The chip assembly of claim 1, wherein an orthographic projection of the chip on the stabilizing portion is located inside the stabilizing portion.

3. The chip assembly of claim 1, wherein the chip further comprises a source and a gate, the source and the gate being located at opposite ends of the upper surface of the chip, respectively, the first lead being connected to the source and the second lead being connected to the gate.

4. The chip assembly of claim 1, further comprising a second metal layer attached to a side of the substrate opposite the first metal layer, the second metal layer being encapsulated by the stabilizing portion.

5. The chip assembly of claim 4, wherein the thickness of the first metal layer is greater than the thickness of the second metal layer.

6. The chip assembly of claim 3, wherein the chip further comprises a drain electrode, the drain electrode being located on a lower surface of the chip.

7. The chip assembly of claim 1, wherein the stabilizing portion is cylindrical, and the diameter of the stabilizing portion is greater than or equal to the largest dimension of the chip.

8. The chip assembly of claim 7, wherein the first leads extend from sides of the stabilizing portion through an interior of the stabilizing portion to ends of the stabilizing portion, and the second leads extend from sides of the stabilizing portion through an interior of the stabilizing portion to ends of the stabilizing portion.

9. The chip assembly of any one of claims 1-8, wherein the stabilizing portion is a crystal glue layer.