CN220710307U - Chip structure and solid state disk - Google Patents
Chip structure and solid state disk Download PDFInfo
- Publication number
- CN220710307U CN220710307U CN202322122919.5U CN202322122919U CN220710307U CN 220710307 U CN220710307 U CN 220710307U CN 202322122919 U CN202322122919 U CN 202322122919U CN 220710307 U CN220710307 U CN 220710307U
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- chip
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- 239000007787 solid Substances 0.000 title claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 70
- 238000003466 welding Methods 0.000 claims abstract description 15
- 238000005476 soldering Methods 0.000 claims abstract description 11
- 238000009826 distribution Methods 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 description 10
- 101000797894 Caenorhabditis elegans Fructose-bisphosphate aldolase 1 Proteins 0.000 description 6
- 101000938676 Homo sapiens Liver carboxylesterase 1 Proteins 0.000 description 6
- 102100030817 Liver carboxylesterase 1 Human genes 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000004806 packaging method and process Methods 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
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- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
The utility model discloses a chip structure and a solid state disk, wherein the chip structure comprises a substrate, a bare chip and at least one bridging piece, and the substrate comprises a bare chip placing position and a plurality of pins; the bare chip is arranged on the bare chip placing position and comprises a plurality of welding pins; the bridge is arranged on the bare chip; part of the soldering feet of the bare chip are correspondingly connected with the pins of the substrate, and each bridging piece is connected with a plurality of soldering feet of the same signals of the bare chip. According to the technical scheme, the cost of chip iterative updating is reduced.
Description
Technical Field
The utility model relates to the technical field of chips, in particular to a chip structure and a solid state disk.
Background
When the chip is updated iteratively, the chip is often updated on the basis of the previous generation, and the positions of the chip soldering feet are approximately the same, but the chip soldering feet are different, so that the newly introduced chip cannot be subjected to sample sealing on the existing frame or substrate, and the frame or substrate needs to be redesigned, so that the cost is too high.
Disclosure of Invention
The utility model provides a chip structure and a solid state disk, aiming at reducing the cost of iterative updating of chips.
In order to achieve the above object, the chip structure according to the present utility model includes:
a substrate comprising a die placement site and a plurality of pins;
the bare chip is arranged on the bare chip placing position and comprises a plurality of welding pins;
at least one bridge disposed on the die;
the partial welding pins of the bare chip are correspondingly connected with the pins of the substrate, at least one bridging piece is connected with a plurality of welding pins of the bare chip with the same signals, and/or at least one bridging piece is connected with one pin of the substrate and at least one welding pin of the bare chip and has the same signals with the pins and welding pins connected with the same bridging piece.
In some embodiments, the bridge comprises a plurality of conductive parts arranged at intervals, each conductive part is connected in a conducting way, each conductive part is connected with at least one of a plurality of welding pins connected with the bridge, and the conductive parts are arranged adjacent to the welding pins connected with the conductive parts.
In some embodiments, the bridge member is one, and the bridge member is disposed to extend along a distribution direction of the fillets.
In some embodiments, the bridge is a plurality of bridges, and the signals of the fillets connected by each bridge are different.
In some embodiments, the die is bonded to the die rest position and the bridge is bonded to the die.
In some embodiments, the bridge is sheet metal.
In some embodiments, the die is bonded to the die rest position and the bridge is bonded to the die.
The utility model provides a solid state disk, which comprises at least one chip structure.
According to the technical scheme of the chip structure, the bridge piece is arranged on the bare chip, so that part of welding pins of the bare chip are correspondingly connected with pins of the substrate, at least one bridge piece is connected with a plurality of welding pins of the bare chip with the same signals, and/or at least one bridge piece is connected with one pin of the substrate and at least one welding pin of the bare chip, so that the number of the welding pins is not matched with that of the bare chip of the substrate, or the signal distribution sequence of the welding pins is not matched with that of the pins of the substrate, and the substrate can be used for packaging to obtain a chip component with normal functions; therefore, when the chip is updated iteratively, a new bare chip can use the substrate (lead frame or substrate, etc.) similar to the previous bare chip, and the lead frame or substrate does not need to be redesigned, so that the cost of the chip for updating iteratively is greatly reduced.
Drawings
FIG. 1 is a schematic diagram of a chip structure according to an embodiment of the utility model;
FIG. 2 is a schematic diagram of a chip structure according to an embodiment of the utility model;
FIG. 3 is a schematic diagram of a chip structure according to an embodiment of the utility model;
FIG. 4 is a schematic diagram of a chip structure according to an embodiment of the utility model;
FIG. 5 is a schematic diagram of a chip structure according to an embodiment of the utility model;
fig. 6 is a schematic structural diagram of a chip structure according to an embodiment of the utility model.
Detailed Description
The following description of the embodiments of the present utility model will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present utility model are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.
It will also be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.
Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present utility model.
The utility model provides a chip structure.
Referring to fig. 1 to 6, the chip structure includes a substrate 10, a die 20, and at least one bridge 30; wherein, the substrate 10 can be a lead frame or a substrate, etc., and the substrate 10 comprises a plurality of pins 11 and a die placement position 12; the die 20 is arranged on the die placing position 12, the die 20 can be adhered to the die placing position 12 through silver paste or insulating paste, of course, other arrangement modes can be adopted, the die 20 comprises a plurality of welding pins 21, the bridge piece 30 is arranged on the die 20, and the bridge piece 30 can be arranged on the die 20 in an adhering mode or in other modes; part of the pins 21 of the die 20 are correspondingly connected with the pins 11 of the substrate 10, each bridge 30 is connected with a plurality of pins 21 of the die 20 with the same signals, and/or at least one bridge 30 is connected with one pin 11 of the substrate 10 and at least one pin 21 of the die 20 and the same signals with the pins 11 and pins 21 connected with the same bridge 30.
The die 20 is a chip which is not packaged after the wafer is subjected to the dicing test, and cannot be directly applied to an actual circuit, and the die 20 can be used as a basic component after the packaging is completed, so that the die 20 is arranged on the substrate 10, and after the soldering pins 21 of the die 20 are completely connected, the die 20 is packaged to obtain a chip component which can be applied to the circuit; wherein die placement site 12 of substrate 10 physically supports die 20. The pins 11 of the substrate 10 are correspondingly connected with the solder pins 21 of the bare chip 20 according to the same signals, and one pin 11 is connected with one solder pin 21 with the same signals, wherein the connection mode of the pins 11 and the solder pins 21 can be wire bonding connection or other connection modes. The chip structure of this embodiment of course further includes a package (not shown) in which the die 20 is packaged, and the substrate 10 is substantially located in the package, and the outer ends of the leads 11 of the substrate 10 are exposed outside the package.
The shape of the bridge 30 is not particularly limited and may be rectangular, circular, or other shapes.
Referring to fig. 1 and 2, in the chip structure of the present embodiment, through the corresponding wire bonding connection between part of the bonding pins 21 of the die 20 and the pins 11 of the substrate 10, each bridge 30 is wire bonded to the bonding pins 21 of the die 20 with the same signals, wherein one bonding pin 21 of the plurality of bonding pins 21 with the same signals is connected to the same pin 11, and the other bonding pins 21 not connected to the pin 11 are connected to the other bonding pins 21, so that the die 20 can be connected and conducted with the pins 11 with the same signals through the bridge connection of the bridge 30 compared with the bonding pins 21 not connected to the pins 11 of the substrate 10. For example, the die 20 has 48 pins 21, 45 pins 21 of the die 20 are correspondingly connected with 45 pins 11 of the substrate 10, 4 pins 21 of the on signal (e.g., pins 21 of 4 VCC signals) are connected with one bridge 30, and 4 pins 21 of the same signal connected with the bridge 30 include 3 pins 21 not connected with pins 11 and one pin 21 connected with pins 11; for another example, the die 20 has 64 pins 21, 58 pins 21 of the die 20 are correspondingly connected with 58 pins 11 of the substrate 10, the remaining 6 pins 21 are 3 pins 21 of the WE signal and 3 pins 21 of the VCCQ signal, the 3 pins 21 of the WE signal are connected with one bridge 30 (denoted as a first bridge), the 3 pins 21 of the VCCQ signal are connected with another bridge 30 (denoted as a second bridge), and one pin 21 connected with pin 11 of the WE signal is also connected with the first bridge, and one pin 21 connected with pin 11 of the VCCQ signal is also connected with the second bridge.
Referring to fig. 3 and 4, in some embodiments, at least one of the bonding pads 21 connected to the bridge 30 may be a bonding pad 21 not connected to the pin 11 of the substrate 10, and the bridge 30 is connected to the pin 11 of the substrate 10 corresponding to the signal, so that each bonding pad 21 of the same signal connected to the bridge 30 is connected to the pin 11 of the substrate 10 corresponding to the signal. For example, the die 20 has 48 pins 21, 45 pins 21 of the die 20 are correspondingly connected with 45 pins 11 of the substrate 10, the remaining 3 pins 21 of the same signal (e.g., pins 21 of 3 VCC signals) are connected with one bridge 30, and the bridge 30 is connected with one pin 11 of the substrate 10, the signals of the pin 11 being the same as those of the remaining 3 pins 21 (e.g., pins 11 of the VCC signal).
For example, pins 11 on substrate 10 may have the signal distribution sequence CE-1, R/B-3, WP-1, WE-1, VCCQ, VSS, VCC 3.3.3, while pins 21 of new die 20 may have the signal distribution sequence CE-1, R/B-3, WP-1, VCCQ, VSS, VCC 3.3.3, WE-1, then pins 21 and pins 11 of the signals CE-1, R/B-3, WP-1, VCCQ, VSS, VCC 3.3.3 may be sequentially wire-bonded, while pins 21 of the WE-1 signal may be wire-bonded to pins 11 of the WE-1 signal by bridge 30, so that die 20 having pins 21 with a signal distribution sequence that does not match the signal distribution sequence of pins 11 of substrate 10 may also be packaged with the substrate 10 to obtain a chip device with normal function.
Referring to fig. 1-4, in some embodiments, a plurality of pins 21 (denoted as first signal pins) of the same signal of the die 20 may be wire-bonded by the first bridge, where one of the plurality of first signal pins 21 may be connected to the pin 11 with the same signal, and the rest are pins 21 not connected to the pin 11, i.e., the first signal pins may be connected to and conducted with the pin 11 with the signal by the bridge interconnection of the first bridge; the second bridge piece is wired to connect at least one solder leg 21 (denoted as a second signal solder leg) of the die 20, and the second signal solder legs may be the solder legs 21 of the same signal that are not connected to the pins 11 of the substrate 10, and only the second bridge piece is required to be connected to the pins 11 of the signal corresponding to the second signal solder leg, so that the second signal solder leg connected to the second bridge piece is also connected and conducted to the pins of the signal corresponding to the second signal solder leg.
For example, the die 20 has 64 pins 21, 58 pins 21 of the die 20 are correspondingly connected with 58 pins 11 of the substrate 10, the remaining 6 pins 21 are 3 VCCQ signals and 3 VSS signals, one VCCQ pin 21 connected with pin 11 of the VCCQ signal is also connected with the first bridge, 3 pins 21 of the VSS signal are connected with the second bridge, and the second bridge is connected with pin 11 of one VSS signal, for example, the signal distribution sequence near pin 11 of the VSS signal on the substrate 10 is CE-1, R/B-3, WP-1, VCCQ, VSS, VCC 3.3.3, while the signal distribution sequence of the pins 21 of the new die 20 is CE-1, R/B-3, WP-1, VCCQ, VCC-3, VSS, then CE-1, R/B-3, WP-3, and the pins 21 of the die can be connected with the second bridge through the pins 11 in order of the same order as that the pins 11 of the die can be connected with the second bridge, and the pins 21 of the substrate 10 can be connected with the other pins 11 in order that the same order as that the pins 11 of the die can be connected with the substrate 10.
In some embodiments, the scheme of the chip structure may also be: the combination of the connection of the embodiment of fig. 1 and 2 with the connection of the embodiment of fig. 3 and 4 means that one part of the bridge 30 is connected as shown in fig. 1 and 2 and another part of the bridge 30 is connected as shown in fig. 3 and 4.
The chip structure can select a proper connection scheme from the schemes according to the design and the actual requirements.
According to the technical scheme of the chip structure of the embodiment, by arranging the bridge piece 30 on the bare chip 20, part of the soldering pins 21 of the bare chip 20 are correspondingly connected with the pins 11 of the substrate 10, at least one bridge piece 30 is connected with a plurality of soldering pins 21 of the bare chip 20 with the same signals, and/or at least one bridge piece 30 is connected with one pin 11 of the substrate 10 and at least one soldering pin 21 of the bare chip 20, so that the number of the soldering pins 21 is not matched with that of the bare chip 20 of the substrate 10, or the signal distribution sequence of the soldering pins 21 is not matched with that of the bare chip 20 of the pin 11 of the substrate 10, the substrate 10 can be used for packaging to obtain a chip component with normal functions; in this way, when the chip is updated iteratively, the new die 20 can follow the substrate 10 (lead frame or substrate, etc.) similar to the die 20 before, without redesigning the lead frame or substrate, thereby greatly reducing the cost of the chip updating iteratively.
In some embodiments, after a portion of the bonding pads 21 of the die 20 are correspondingly wire-bonded to the pins 11 of the substrate 10, the bonding pads 21 of the same signal that are not correspondingly wire-bonded to the pins 11 of the substrate 10 may be wire-bonded to the bridge 30, and then the bridge 30 may be wire-bonded to one of the pins 11, which is the same as the bonding pads 21 to which the bridge 30 is connected, so that signal interconnection of the bonding pads 21 of the same signal that are not connected to the pins 11 may be achieved.
For example, after a portion of the bonding pins 21 of the die 20 are wire-bonded to the pins 11 of the substrate 10, the bonding pins 21 that are not wire-bonded to the pins 11 of the substrate 10 are VCC signals, the bonding pins 21 that are wire-bonded to the bridge 30 are VCC signals, and then the bridge 30 may be wire-bonded to the pins 11 of one VCC signal.
Referring to fig. 5 and 6, in the present embodiment, the bridge 30 includes a plurality of conductive portions 31 disposed at intervals, each conductive portion 31 is connected in conduction, each conductive portion 31 is connected to at least one of the plurality of fillets 21 connected to the bridge 30 to which it belongs, and the conductive portion 31 is disposed adjacent to the fillets 21 connected thereto.
In some embodiments, the plurality of conductive portions 31 are disposed at intervals and adjacent to the fillets 21 that are not correspondingly connected to the pins 11, so that the fillets 21 that are farther in the same signal can all facilitate connection to the bridge 30.
Referring to fig. 5, taking an example in which one bridge 30 includes two conductive portions 31, after a portion of the bonding pads 21 of the die 20 are correspondingly wire-bonded to the pins 11 of the substrate 10, a portion of the bonding pads 21 not correspondingly wire-bonded to the pins 11 of the substrate 10 may be wire-bonded to one conductive portion 31 of the bridge 30, another portion of the bonding pads may be wire-bonded to another conductive portion 31 of the bridge 30, and then the bridge 30 may be wire-bonded to one bonding pad 21 wire-bonded to the pins 11 of the substrate 10, thereby realizing signal interconnection between the bonding pads 21 and the pins 11 of the same signal not correspondingly connected to the pins 11.
Referring to fig. 6, taking an example in which one bridge 30 includes two conductive portions 31, after a portion of the bonding pads 21 of the die 20 are correspondingly wire-bonded to the pins 11 of the substrate 10, a portion of the bonding pads 21 not correspondingly wire-bonded to the pins 11 of the substrate 10 may be wire-bonded to one conductive portion 31 of the bridge 30, another portion of the bonding pads may be wire-bonded to the other conductive portion 31 of the bridge 30, and then one conductive portion 31 of the bridge 30 may be wire-bonded to one of the pins 11 of the substrate 10, the pins 11 being the same pins 11 as the bonding pads 21 connected to the bridge 30, so that signal interconnection between the bonding pads 21 and the pins 11 of the same signal not correspondingly connected to the pins 11 may be realized.
Referring to fig. 1, in the present embodiment, the bridge member 30 is one, and the bridge member 30 is disposed along the distribution direction of the fillets 21.
In this way, the bridge 30 extends along the distribution direction of the fillets 21, so that the bridge 30 and the fillets 21 can be connected more conveniently.
Referring to fig. 2 and 4, in the present embodiment, the number of bridges 30 is plural, and the signals of the fillets 21 to which the respective bridges 30 are connected are different.
Referring to fig. 2, for example, when the number of the bridges 30 is two, after a portion of the pins 21 of the die 20 are wire-bonded to the pins 11 of the substrate 10, the pins 21 not wire-bonded to the pins 11 of the substrate 10 are VCCQ signals and VCC signals, respectively, the pins 21 representing the VCCQ signals may be wire-bonded to one bridge 30, the pins 21 representing the VCC signals may be wire-bonded to the other bridge 30, then one bridge 30 may be wire-bonded to the pins 21 of one VCCQ signal, and the pins 21 of the VCCQ signals may be wire-bonded to the pins 11 of the VCCQ signals, and the other bridge 30 may be wire-bonded to the pins 21 representing the VCC signals, which are wire-bonded to the pins 11 of the substrate 10, so that signal interconnection of the pins 21 of the VCCQ signals and the pins 21 of the VCC signals with the pins 11 of the corresponding signals may be achieved.
Referring to fig. 4, for another example, when the number of the bridges 30 is two, after the partial bonding pins 21 of the die 20 are correspondingly wire-bonded to the pins 11 of the substrate 10, the bonding pins 21 which are not correspondingly wire-bonded to the pins 11 of the substrate 10 are respectively VCCQ signals and VCC signals, the bonding pins 21 representing VCCQ signals may be wire-bonded to one bridge 30, the bonding pins 21 representing VCC signals may be wire-bonded to the other bridge 30, then one bridge 30 may be wire-bonded to the pins 11 of one VCCQ signal, and the other bridge 30 may be wire-bonded to the pins 11 of one VCC signal, so that signal interconnection of the bonding pins 21 of VCCQ signals and the bonding pins 21 of VCC signals to the pins 11 of corresponding signals may be achieved.
In some embodiments, the bridge 30 may be a sheet of metal, e.g., aluminum, copper, etc.; of course, in other embodiments, the bridge 30 may be a non-sheet structure, and the bridge 30 may be made of other conductive materials.
In some embodiments, die 20 is bonded to die attach station 12, die 20 may be bonded to die attach station 12 by silver paste or insulating paste, and bridge 30 is bonded to die 20.
The utility model further provides a solid state disk, which comprises at least one chip structure or a chip manufactured by at least one chip manufacturing method, wherein the specific structure of the chip structure refers to the above embodiment.
The above description of the preferred embodiments of the present utility model should not be taken as limiting the scope of the utility model, but rather should be understood to cover all modifications, variations and adaptations of the present utility model using its general principles and the following detailed description and the accompanying drawings, or the direct/indirect application of the present utility model to other relevant arts and technologies.
Claims (7)
1. A chip structure, comprising:
a substrate comprising a die placement site and a plurality of pins;
the bare chip is arranged on the bare chip placing position and comprises a plurality of welding pins;
at least one bridge disposed on the die;
part of the soldering feet of the bare chip are correspondingly connected with the pins of the substrate; at least one of the bridge members connects a plurality of pins of the die with the same signals, and/or at least one of the bridge members connects one pin of the substrate with at least one pin of the die with the same signals as the pins and pins connected with the same bridge member.
2. The chip structure of claim 1, wherein the bridge member includes a plurality of spaced apart conductive portions, each conductive portion being conductively connected to at least one of a plurality of bonding pads to which it is connected, and wherein the conductive portion is disposed adjacent to the bonding pad to which it is connected.
3. The chip structure of claim 1, wherein the bridge member is one and extends along a distribution direction of the fillets.
4. The chip structure of claim 1, wherein the number of bridges is plural, and the signal of the fillets to which each bridge is connected is different.
5. The chip structure of claim 1, wherein the bridge is a metal sheet.
6. The chip structure of claim 1 wherein said die is bonded to said die placement site and said bridge is bonded to said die.
7. A solid state disk comprising at least one chip structure of any one of claims 1-6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322122919.5U CN220710307U (en) | 2023-08-08 | 2023-08-08 | Chip structure and solid state disk |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322122919.5U CN220710307U (en) | 2023-08-08 | 2023-08-08 | Chip structure and solid state disk |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220710307U true CN220710307U (en) | 2024-04-02 |
Family
ID=90438836
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202322122919.5U Active CN220710307U (en) | 2023-08-08 | 2023-08-08 | Chip structure and solid state disk |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220710307U (en) |
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2023
- 2023-08-08 CN CN202322122919.5U patent/CN220710307U/en active Active
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