CN220709959U - Discharge control circuit and solid state disk - Google Patents
Discharge control circuit and solid state disk Download PDFInfo
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- CN220709959U CN220709959U CN202322179871.1U CN202322179871U CN220709959U CN 220709959 U CN220709959 U CN 220709959U CN 202322179871 U CN202322179871 U CN 202322179871U CN 220709959 U CN220709959 U CN 220709959U
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- 239000003990 capacitor Substances 0.000 claims abstract description 70
- 238000006243 chemical reaction Methods 0.000 claims description 17
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- 230000006978 adaptation Effects 0.000 description 1
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Abstract
The utility model discloses a discharge control circuit and a solid state disk, wherein the discharge control circuit comprises a discharge module, the discharge module comprises a first control unit and a first switch unit, and the first control unit comprises a first control end and a first detection end for connecting a power supply; the first switch unit is electrically connected with the first control end, and the positive electrode of the load capacitor is grounded through the first switch unit; when the voltage of the first detection end is lower than a preset reference voltage, the first control unit controls the first switch unit to be conducted, and a rapid discharge loop from the positive electrode of the load capacitor to the ground through the first switch unit is formed; when the voltage of the first detection end is larger than or equal to a preset reference voltage, the first control unit controls the first switch unit to be disconnected. According to the technical scheme, the problem that the disc cannot be read normally easily when the solid state disc encounters the condition of repeated and repeated fast switching of the power supply system is solved.
Description
Technical Field
The utility model relates to the technical field of discharge circuits, in particular to a discharge control circuit and a solid state disk.
Background
The solid state disk is widely applied to various fields such as military, vehicle-mounted, industrial control, video monitoring, network terminals, electric power, medical treatment, aviation, navigation equipment and the like. At present, in the application of the solid state disk, if the power supply system is powered off repeatedly and rapidly, the solid state disk may be powered on again after the last power off, and the chip on the solid state disk works abnormally, so that the disk cannot be read normally.
Disclosure of Invention
The utility model provides a discharge control circuit and a solid state disk, and aims to solve the problem that when the solid state disk encounters the condition of repeated and repeated quick switching of a power supply system, the disk cannot be read normally easily.
In order to achieve the above object, the present utility model provides a discharge control circuit for controlling a load capacitor of a load circuit to discharge, the discharge control circuit including a discharge module, the discharge module including:
the first control unit comprises a first control end and a first detection end used for connecting with a power supply;
the first switch unit is electrically connected with the first control end, and the positive electrode of the load capacitor is grounded through the first switch unit;
when the voltage of the first detection end is lower than a preset reference voltage, the first control unit controls the first switch unit to be conducted, so that a rapid discharge loop from the positive electrode of the load capacitor to the ground through the first switch unit is formed; when the voltage of the first detection end is larger than or equal to the preset reference voltage, the first control unit controls the first switch unit to be disconnected.
In some embodiments, the on-resistance value of the first switch unit is much smaller than the resistance value of the load resistor of the load circuit, and the first control unit adjusts the discharging speed of the load capacitor by adjusting the on-resistance value of the first switch unit.
In some embodiments, the first switch unit includes a first MOS transistor and a first resistor, a conducting end of the first MOS transistor is electrically connected to the positive electrode of the load capacitor, another conducting end of the first MOS transistor is grounded, a gate of the first MOS transistor is electrically connected to the first control end, and the first resistor is serially connected to any conducting end of the first MOS transistor.
In some embodiments, the first control unit further includes a second detection terminal electrically connected to the positive electrode of the load capacitor.
In some embodiments, the first control unit includes a first control logic subunit and a first voltage comparison subunit and a first conversion subunit;
one input end of the first voltage comparison subunit is the first detection end, and the other input end receives the preset reference voltage input; an input end of the first conversion subunit is the second detection end, the first control logic subunit is electrically connected with the output end of the first voltage comparison subunit and the output end of the first conversion subunit respectively, and the first control end is an output end of the first control logic subunit.
In some embodiments, the discharge control circuit further comprises a detection module, wherein the detection module is electrically connected with the positive electrode of the load capacitor and is used for detecting the size of the load capacitor; the first control unit is in communication connection with the detection module, or the first control unit and the detection module are in communication connection with the same main control chip.
In some embodiments, the detection module comprises:
the second control unit comprises a second control end, a third detection end, a fourth detection end and a fifth detection end;
the second switch unit is electrically connected with the second control end;
the current detection unit is used for detecting the charging current of the power supply to the load capacitor;
the third detection end is used for being connected with the power supply, the third detection end is electrically connected with the positive electrode of the load capacitor through the second switch unit, the current detection unit is electrically connected with any one of the conducting ends of the second switch unit, the fourth detection end is electrically connected with the output end of the current detection unit, and the fifth detection end is electrically connected with the positive electrode of the load capacitor;
when the voltage of the third detection end reaches the preset reference voltage, the second control unit controls the second switch unit to be conducted; when the voltage of the third detection end is smaller than the preset reference voltage, the second control unit controls the second switch unit to be disconnected; the second control unit controls the charging current of the load capacitor by adjusting the conduction resistance value of the second switch unit.
In some embodiments, the second control unit includes a second control logic subunit, a second voltage comparison subunit, and a second conversion subunit;
one input end of the second voltage comparison subunit is the third detection end, and the other input end receives the preset reference voltage input; the second control logic subunit is electrically connected with the output end of the second voltage comparison subunit and the output end of the second conversion subunit respectively, and the second control end is an output end of the second control logic subunit.
In some embodiments, the second switching unit includes a second MOS transistor, an on end of the second MOS transistor is electrically connected to the third detection end, another on end of the second MOS transistor is electrically connected to the positive electrode of the load capacitor, and a gate of the second MOS transistor is electrically connected to the second control end.
The utility model also provides a solid state disk, which comprises a load circuit, wherein the load circuit comprises a load capacitor and a load resistor, and the solid state disk further comprises the discharge control circuit.
The discharging control circuit is applied to product equipment (such as a solid state disk), when the solid state disk encounters the condition that the power supply system is powered off repeatedly and rapidly, the voltage of the first detection end is lower than the preset reference voltage when the power supply system is powered off each time, the first control unit controls the first switch unit to be conducted, the load capacitor discharges rapidly through the first switch unit, so that the power on the load circuit is discharged rapidly, and the power on the load circuit is completely removed before the power supply system is powered on rapidly after the power supply system is powered off, so that the condition that partial devices (such as chips) on the load circuit work abnormally when the power supply circuit is powered on again before the power is not completely removed is effectively avoided, and the phenomenon that the solid state disk cannot be read normally is prevented.
Drawings
Fig. 1 is a schematic diagram of a configuration of a discharging control circuit connected to a load circuit according to a first embodiment of the present utility model;
FIG. 2 is a schematic diagram of a discharging control circuit connected to a load circuit according to a second embodiment of the present utility model;
FIG. 3 is a schematic diagram showing a structure of a discharging control circuit connected to a load circuit according to a third embodiment of the present utility model;
fig. 4 is a schematic diagram of a structure in which a discharge control circuit is connected to a load circuit according to a fourth embodiment of the present utility model;
FIG. 5 is a schematic diagram showing a structure of a discharging control circuit connected to a load circuit according to a fifth embodiment of the present utility model;
fig. 6 is a schematic structural diagram of a detection module connected to a load circuit according to a sixth embodiment of the present utility model.
Detailed Description
The following description of the embodiments of the present utility model will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present utility model are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.
It will also be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.
Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present utility model.
The present utility model proposes a discharge control circuit for controlling a load capacitor C1 of a load circuit 01 to discharge, the load circuit 01 including the load capacitor C1 and a load resistor RL (refer to fig. 1 to 6).
Referring to fig. 1, in the present embodiment, the discharge control circuit includes a discharge module 100, and the discharge module 100 includes a first control unit 110 and a first switching unit 120; wherein:
the first control unit 110 includes a first control terminal K1 and a first detection terminal J1; the first switch unit 120 is electrically connected with the first control end K1, and the positive electrode of the load capacitor C1 is grounded through the first switch unit 120; the first detection end J1 is used for being connected with the power supply 02 so as to detect the output voltage condition of the power supply 02; the first control unit 110 outputs a control signal through the first control terminal K1 to control the on-off state of the first switch unit 120;
when the voltage of the first detection end J1 is lower than the preset reference voltage Vref, it is indicated that the output voltage of the power supply 02 is too low (for example, the power supply system is powered off or powered off, so that the power supply 02 has no output voltage) and the load circuit 01 cannot work normally, at this time, the first control unit 110 controls the first switch unit 120 to be turned on, so as to form a rapid discharge loop from the positive electrode of the load capacitor C1 to the ground through the first switch unit 120, and the load capacitor C1 is rapidly discharged through the first switch unit 120; when the voltage of the first detection terminal J1 is greater than or equal to the preset reference voltage Vref, it is indicated that the output voltage of the power supply 02 is recovered to be normal (for example, the power supply system is powered off and then is powered on again, or the power supply system is powered on and is recovered to be normal), and the first control unit 110 controls the first switch unit 120 to be turned off, so that the load capacitor C1 stops discharging through the first switch unit 120 and charges, and the load circuit 01 recovers to be in normal operation. The preset reference voltage Vref may be a minimum voltage value that enables the load circuit 01 to operate normally.
When the product equipment (such as a solid state disk) using the discharge control circuit of the embodiment encounters the situation that the power supply system is powered off repeatedly and rapidly, the voltage of the first detection end J1 is lower than the preset reference voltage Vref when the power supply system is powered off each time, the first control unit 110 controls the first switch unit 120 to be conducted, the load capacitor C1 discharges rapidly through the first switch unit 120, so that the power on the load circuit 01 is discharged rapidly, and thus the power on the load circuit 01 is completely removed before the power supply system is powered on rapidly after the power supply system is powered off, and therefore, the situation that partial devices (such as chips) on the load circuit 01 work abnormally and the solid state disk cannot be read normally is effectively avoided.
In some embodiments, the on resistance of the first switch unit 120 is much smaller than the resistance of the load resistor RL of the load circuit 01, in this embodiment, the two values are different by at least two orders of magnitude (i.e. at least 100 times), for example, the resistance of the load resistor RL is a, and the on resistance of the first switch unit 120 is 1A/100, 1A/150, 1A/200, … …, 1A/500, etc.; the first control unit 110 adjusts the discharging speed of the load capacitor C1 by adjusting the on-resistance value of the first switching unit 120. In this embodiment, the scheme that the on resistance of the first switch unit 120 is far smaller than the resistance of the load resistor RL is adopted, so that the electricity on the load capacitor C1 is basically released through the current release path of the first switch unit 120, and thus, the discharging of the load capacitor C1 can be completed more rapidly, and the discharging time is shorter. In addition, the first control unit 110 may control the on resistance of the first switch unit 120, so that the first control unit 110 may correspondingly adjust the on resistance of the first switch unit 120 according to the discharge time required by the product, so that the discharge speed of the load capacitor C1 through the first switch unit 120 is increased or decreased, thereby achieving the discharge time required by the product.
Of course, in other embodiments, the on-resistance of the first switch unit 120 may be several times or tens of times smaller than the resistance of the load resistor RL of the load circuit 01, the resistance of the load resistor RL is a, and the on-resistance of the first switch unit 120 is 1A/5, 1A/10, 1A/20, … …, 1A/50, etc.
Referring to fig. 2, in some embodiments, the first switch unit 120 includes a first MOS transistor Q1 and a first resistor R1, wherein one conducting end (e.g., a drain) of the first MOS transistor Q1 is electrically connected to the positive electrode of the load capacitor C1, the other conducting end (e.g., a source) of the first MOS transistor Q1 is grounded, a gate of the first MOS transistor Q1 is electrically connected to the first control end K1, and the first resistor R1 is serially connected to any conducting end of the first MOS transistor Q1. In this embodiment, the on resistance of the first switch unit 120 is the sum of the resistance of the first resistor R1 and the on resistance of the first MOS transistor Q1, and the first control unit 110 adjusts the on internal resistance of the first MOS transistor Q1 by controlling the voltage of the gate of the first MOS transistor Q1, so as to adjust the on resistance of the first switch unit 120. Optionally, in some embodiments, the first MOS transistor Q1 is an N-type MOS transistor; of course, in other embodiments, the first MOS transistor Q1 may also be a P-type MOS transistor.
In some embodiments, the first switch unit 120 may further include a plurality of switch sub-units connected in parallel, where each switch sub-unit includes a resistor and a switch tube, the resistors in the switch sub-units have different resistance values, and the first control unit 110 includes a plurality of first control terminals K1 corresponding to the number of the switch tubes, and each first control terminal K1 is electrically connected to a trigger terminal of each switch tube in a one-to-one correspondence; in this way, the first control unit 110 can control different switching tubes to be turned on to change the conduction resistance of the first switching unit 120, and the first control unit 110 can also control different numbers of switching tubes to be turned on to change the conduction resistance of the first switching unit 120.
Referring to fig. 3, in some embodiments, the discharge control circuit further includes a detection module 200, where the detection module 200 is electrically connected to the positive electrode of the load capacitor C1, and is configured to detect the magnitude of the load capacitor C1; the first control unit 110 further includes a second detection end J2, where the second detection end J2 is electrically connected to the positive electrode of the load capacitor C1, so as to obtain a voltage on the load capacitor C1 and feed back the voltage to the first control unit 110; the first control unit 110 is communicatively connected to the detection module 200. Alternatively, in other embodiments, the first control unit 110 and the detection module 200 are communicatively connected to the same main control chip.
In the technical solution of the discharging control circuit of this embodiment, the first control unit 110 can obtain the voltage Vt0 when the load capacitor C1 begins to discharge through the second detection end J2, and the detection module 200 can detect the size of the load capacitor C1 of the load circuit 01, so that the first control unit 110 or the main control unit can obtain the relationship between the discharging time of the load capacitor C1 and the on resistance of the first switch unit 120: t=rcl (Vt 0/Vt 1), where t is the discharge time of the load capacitor C1, R is the on resistance of the first switch unit 120 (e.g. the sum of the resistance of the first resistor R1 and the on resistance of the first MOS transistor Q1), CL is the size of the load capacitor C1, and Vt1 is a preset voltage threshold (e.g. a preset voltage value, or a voltage threshold for disabling the load device on the load circuit 01, such as 0.3V); after the relationship between the discharge time t and the conduction resistance R of the first switch unit 120 is obtained, when the product equipment needs to change the discharge time t, the first control unit 110 can control and adjust the conduction resistance R of the first switch unit 120 to a corresponding size, so that the discharge time t of the product equipment can be changed, the discharge time t can be controlled and adjusted, and different requirements of different customers on the discharge time of the product can be better met.
Referring to fig. 4, in some embodiments, the first control unit 110 includes a first control logic subunit 111 and a first voltage comparison subunit 112 and a first conversion subunit 113 (e.g., an analog-to-digital converter); one input end of the first voltage comparison subunit 112 is a first detection end J1, and the other input end receives the input of a preset reference voltage Vref; an input end of the first conversion subunit 113 is a second detection end J2, the first control logic subunit 111 is electrically connected to the output end of the first voltage comparison subunit 112 and the output end of the first conversion subunit 113, and the first control end K1 is an output end of the first control logic subunit 111.
The working procedure of the first control unit 110 in this embodiment is as follows: when the power supply 02 supplies power normally, the voltage of the first detection terminal J1 is greater than or equal to the preset reference voltage Vref, the first voltage comparing subunit 112 outputs a first signal (e.g., a high level) to the first control logic subunit 111, the first control logic subunit 111 outputs a corresponding signal to the on/off control terminal of the first switch unit 120, so that the first switch unit 120 is in an off state, and at this time, the first converting subunit 113 obtains the voltage (i.e., vt 0) of the load capacitor C1 through the second detection terminal J2, and converts the obtained voltage into a digital signal to output to the first control logic subunit 111; when the power supply system is powered off and the power supply 02 does not output, the voltage of the first detection terminal J1 is smaller than the preset reference voltage Vref, the first voltage comparison subunit 112 outputs a second signal (for example, a low level) to the first control logic subunit 111, the first control logic subunit 111 outputs a corresponding signal to the on-off control terminal of the first switch unit 120, so that the first switch unit 120 is turned on, and the load capacitor C1 is rapidly discharged through the current discharge path from the first switch unit 120 to the ground.
Referring to fig. 5, in some embodiments, the detection module 200 includes a second control unit 210, a second switching unit 220, and a current detection unit 230, wherein:
the second control unit 210 includes a second control terminal K2, a third detection terminal J3, a fourth detection terminal J4, and a fifth detection terminal J5;
the second switch unit 220 is electrically connected with the second control terminal K2;
the current detection unit 230 is configured to detect a charging current of the load capacitor C1 by the power supply 02;
the third detection end J3 is used for being connected with the power supply 02, the third detection end J3 is electrically connected with the positive electrode of the load capacitor C1 through the second switch unit 220, the current detection unit 230 is electrically connected with any conducting end of the second switch unit 220, the fourth detection end J4 is electrically connected with the output end of the current detection unit 230, and the fifth detection end J5 is electrically connected with the positive electrode of the load capacitor C1;
when the voltage of the third detection terminal J3 reaches the preset reference voltage Vref, the second control unit 210 controls the second switch unit 220 to be turned on; when the voltage of the third detection terminal J3 is less than the preset reference voltage Vref, the second control unit 210 controls the second switching unit 220 to be turned off; the second control unit 210 controls the charging current of the load capacitor C1 by adjusting the on-resistance value of the second switching unit 220.
Referring to fig. 6, in some embodiments, the second control unit 210 includes a second control logic subunit 211, a second voltage comparison subunit 212 (e.g., a voltage comparator), and a second conversion subunit 213; one input end of the second voltage comparison subunit 212 is a third detection end J3, and the other input end receives the input of the preset reference voltage Vref; the two input ends of the second conversion subunit 213 are a fourth detection end J4 and a fifth detection end J5, respectively, the second control logic subunit 211 is electrically connected to the output end of the second voltage comparison subunit 212 and the output end of the second conversion subunit 213, respectively, and the second control end K2 is an output end of the second control logic subunit 211.
The working process of the detection module 200 of this embodiment is as follows: when the power supply 02 supplies power normally, the voltage of the third detection terminal J3 is higher than the preset reference voltage Vref, the second voltage comparing subunit 212 outputs a third signal (e.g., a high level) to the second control logic subunit 211, and the second control logic subunit 211 outputs a corresponding signal to the on/off control terminal of the second switching unit 220, so that the second switching unit 220 is in an on state, at this time, the second converting subunit 213 obtains the current value detected and outputted by the current detecting unit 230 in real time through the fourth detection terminal J4, that is, the charging current of the load capacitor C1, and obtains the voltage of the load capacitor C1 in real time through the fifth detection terminal J5, and converts the obtained current value and voltage value into a digital signal to output to the second control logic subunit 211, and the second control logic subunit 211 adjusts the on resistance of the second switching unit 220 according to the charging current and voltage of the load capacitor C1, so that the charging current of the load capacitor C1 is kept constant and continuously charged for a certain time (e.g., Δt) which is very short, usually in microsecond order; after charging Δt, the supply current to the load capacitor CL and the load RL through the second switching unit 220 is no longer controlled to be constant, and is supplied as required for normal operation. In addition, when the second control logic subunit 211 receives that the current output by the second conversion subunit 213 is excessive (for example, greater than the safety threshold), the second control logic subunit 211 determines that the circuit is faulty or shorted at this time, and outputs a corresponding signal to the on-off control end to control the second switch unit 220 to be turned off, so as to protect the safety of the circuit.
Referring to fig. 6, in some embodiments, the second switching unit 220 includes a second MOS transistor, one conducting end of the second MOS transistor is electrically connected to the third detecting end J3, the other conducting end of the second MOS transistor is electrically connected to the positive electrode of the load capacitor C1, and the gate electrode of the second MOS transistor is electrically connected to the second control end K2. In this embodiment, the on resistance of the second switch unit 220 is recorded as the on resistance of the second MOS transistor, and the second control unit 210 adjusts the on resistance of the second MOS transistor by controlling the voltage of the gate of the second MOS transistor, thereby adjusting the on resistance of the second switch unit 220. Optionally, in some embodiments, the first MOS transistor Q1 is a P-type MOS transistor; of course, in other embodiments, the first MOS transistor Q1 may also be an N-type MOS transistor.
In some embodiments, the second control unit 210 calculates the magnitude of the load capacitance C1 according to the formula cl=i×Δt/(V1-V0); the first control unit 110 calculates the on-resistance of the first switch unit 120 according to the formula t=rcl (Vt 0/Vt 1), and adjusts the first switch unit 120 according to the calculated on-resistance; wherein CL is the magnitude of the load capacitor C1, I is the magnitude of the charging current of the load capacitor C1, Δt is the charging duration of the load capacitor C1, V0 is the voltage when the load capacitor C1 starts to charge, V1 is the voltage when the load capacitor C1 starts to charge Δt, t is the required discharging time, R is the on resistance of the first switch unit 120, vt0 is the voltage when the load capacitor C1 starts to discharge, and Vt1 is the preset voltage threshold.
By combining the two formulas, t=r [ i×Δt/(V1-V0) ]×ln (Vt 0/Vt 1) can be obtained, that is, the relationship between the discharge time t of the load capacitor C1 and the on resistance R of the first switch unit 120 is obtained, so that the discharge time t of the discharge control circuit can be controlled and regulated, and the discharge control circuit can be generally used for the required product equipment with different discharge times.
The utility model further provides a solid state disk, which comprises a load circuit and a discharge control circuit, wherein the specific structure of the discharge control circuit refers to the embodiment, and because the solid state disk adopts all the technical schemes of all the embodiments of the discharge control circuit, the solid state disk at least has all the beneficial effects brought by the technical schemes of the embodiments, and the detailed description is omitted. The load circuit comprises a load capacitor and a load resistor.
The above description of the preferred embodiments of the present utility model should not be taken as limiting the scope of the utility model, but rather should be understood to cover all modifications, variations and adaptations of the present utility model using its general principles and the following detailed description and the accompanying drawings, or the direct/indirect application of the present utility model to other relevant arts and technologies.
Claims (10)
1. A discharge control circuit for controlling a load capacitance of a load circuit to discharge, the discharge control circuit comprising a discharge module comprising:
the first control unit comprises a first control end and a first detection end used for connecting with a power supply;
the first switch unit is electrically connected with the first control end, and the positive electrode of the load capacitor is grounded through the first switch unit;
when the voltage of the first detection end is lower than a preset reference voltage, the first control unit controls the first switch unit to be conducted, so that a rapid discharge loop from the positive electrode of the load capacitor to the ground through the first switch unit is formed; when the voltage of the first detection end is larger than or equal to the preset reference voltage, the first control unit controls the first switch unit to be disconnected.
2. The discharge control circuit of claim 1 wherein the first switching element has a conduction resistance that is substantially less than a resistance of a load resistance of the load circuit.
3. The discharge control circuit of claim 1, wherein the first switching unit comprises a first MOS transistor and a first resistor, a conducting end of the first MOS transistor is electrically connected to the positive electrode of the load capacitor, the other conducting end of the first MOS transistor is grounded, a gate of the first MOS transistor is electrically connected to the first control end, and the first resistor is serially connected to any conducting end of the first MOS transistor.
4. The discharge control circuit of claim 1 wherein the first control unit further comprises a second detection terminal electrically connected to the positive electrode of the load capacitor.
5. The discharge control circuit of claim 4 wherein the first control unit comprises a first control logic subunit and a first voltage comparison subunit and a first conversion subunit;
one input end of the first voltage comparison subunit is the first detection end, and the other input end receives the preset reference voltage input; an input end of the first conversion subunit is the second detection end, the first control logic subunit is electrically connected with the output end of the first voltage comparison subunit and the output end of the first conversion subunit respectively, and the first control end is an output end of the first control logic subunit.
6. The discharge control circuit of claim 4 further comprising a detection module electrically connected to the positive electrode of the load capacitor for detecting the magnitude of the load capacitor; the first control unit is in communication connection with the detection module, or the first control unit and the detection module are in communication connection with the same main control chip.
7. The discharge control circuit of claim 6 wherein the detection module comprises:
the second control unit comprises a second control end, a third detection end, a fourth detection end and a fifth detection end;
the second switch unit is electrically connected with the second control end;
the current detection unit is used for detecting the charging current of the power supply to the load capacitor;
the third detection end is used for being connected with the power supply, the third detection end is electrically connected with the positive electrode of the load capacitor through the second switch unit, the current detection unit is electrically connected with any one of the conducting ends of the second switch unit, the fourth detection end is electrically connected with the output end of the current detection unit, and the fifth detection end is electrically connected with the positive electrode of the load capacitor;
when the voltage of the third detection end reaches the preset reference voltage, the second control unit controls the second switch unit to be conducted; when the voltage of the third detection end is smaller than the preset reference voltage, the second control unit controls the second switch unit to be disconnected; the second control unit controls the charging current of the load capacitor by adjusting the conduction resistance value of the second switch unit.
8. The discharge control circuit of claim 7 wherein the second control unit comprises a second control logic subunit, a second voltage comparison subunit, and a second conversion subunit;
one input end of the second voltage comparison subunit is the third detection end, and the other input end receives the preset reference voltage input; the second control logic subunit is electrically connected with the output end of the second voltage comparison subunit and the output end of the second conversion subunit respectively, and the second control end is an output end of the second control logic subunit.
9. The discharge control circuit of claim 7, wherein the second switching unit comprises a second MOS transistor, one conducting end of the second MOS transistor is electrically connected to the third detecting end, the other conducting end of the second MOS transistor is electrically connected to the positive electrode of the load capacitor, and the gate electrode of the second MOS transistor is electrically connected to the second control end.
10. A solid state disk comprising a load circuit comprising a load capacitor and a load resistor, wherein the solid state disk further comprises the discharge control circuit of any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322179871.1U CN220709959U (en) | 2023-08-14 | 2023-08-14 | Discharge control circuit and solid state disk |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322179871.1U CN220709959U (en) | 2023-08-14 | 2023-08-14 | Discharge control circuit and solid state disk |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220709959U true CN220709959U (en) | 2024-04-02 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202322179871.1U Active CN220709959U (en) | 2023-08-14 | 2023-08-14 | Discharge control circuit and solid state disk |
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| Country | Link |
|---|---|
| CN (1) | CN220709959U (en) |
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2023
- 2023-08-14 CN CN202322179871.1U patent/CN220709959U/en active Active
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