CN220673751U - TypeC power supply path management circuit and device - Google Patents

Abstract

The utility model discloses a typeC power path management circuit and a typeC power path management device, wherein the circuit comprises a power module, a first typeC interface module, a second typeC interface module, a first NMOS switch module, a second NMOS switch module and a discharge control module; the first TypeC interface module is electrically connected with the first NMOS discharge control unit, and the second TypeC interface module is electrically connected with the second NMOS discharge control unit; the first NMOS discharge control unit is electrically connected with the second NMOS discharge control unit, the first NMOS switch module is electrically connected with the external controller and the first NMOS discharge control unit respectively, and the second NMOS switch module is electrically connected with the external controller and the second NMOS discharge control unit respectively. The utility model realizes the power path management based on the NMOS, so that the NMOS can drive the load under the low power condition, and the reliable work of the output load is realized.

Description

TypeC power supply path management circuit and device

Technical Field

The utility model relates to the technical field of power supplies, in particular to a TypeC power supply path management circuit and device.

Background

The power supply is an important component of the electronic device, and it can convert external electric energy into electric energy required by the device, and provide stable and reliable voltage and current for each module of the device. The conversion efficiency of a power supply is an important indicator for measuring the performance of the power supply, and reflects how much power is effectively utilized in the conversion process of the power supply. The power supply inevitably generates certain loss in the conversion process, and is mainly represented on power devices in a circuit, such as a switch tube, a diode and the like. These devices, when turned on and off, produce a certain voltage drop and internal resistance, resulting in current and voltage losses. These losses can be dissipated in the form of thermal energy, which can cause the device to heat and scald, affecting the life and stability of the device, and reducing the conversion efficiency of the power supply.

In order to improve the conversion efficiency of the power supply and reduce the heating value of the device, a common method is to use a suitable switching tube to form a power path management circuit. The power path management circuit is a circuit for controlling the on-off and switching of a power supply from an input end to an output end, and can select an optimal power path according to the working state and the load condition of equipment so as to realize optimal conversion efficiency.

The common switching transistors in the prior art are NMOS (N-channel metal oxide semiconductor field effect transistor) and PMOS (P-channel metal oxide semiconductor field effect transistor). They are all one kind of MOSFET (metal oxide semiconductor field effect transistor) and have the features of low voltage drop, low internal resistance, high switching speed, etc. The on-resistance of the NMOS is lower than that of the PMOS by more than half. However, most power path management circuits still use PMOS as the switching transistor because NMOS has a disadvantage in that its gate voltage must be higher than the source voltage to turn on, whereas PMOS, in contrast, must be lower than the source voltage to turn on. This results in the problem that the NMOS cannot drive the load under low power conditions. For example, when the device is in a standby or sleep state, the output voltage of the power supply may decrease, and if the NMOS is used as the switching tube, a sufficient current may not be supplied to the load, thereby causing the device to fail to operate normally.

In summary, there is no power path management circuit in the prior art that can overcome the drawbacks of NMOS and utilize the advantages thereof. This presents great inconvenience and trouble to the user. Therefore, a new NMOS power path management circuit is urgently needed to solve the above-mentioned problems.

Disclosure of Invention

The utility model provides a typeC power supply path management circuit and device has realized the power supply path management based on NMOS for NMOS can drive the load under low power condition, realizes the reliable work of output load.

In order to solve the technical problems, the application provides a typeC power path management circuit, which comprises a power module, a first typeC interface module, a second typeC interface module, a first NMOS switch module, a second NMOS switch module and a discharge control module; the discharge control module comprises a first NMOS discharge control unit and a second NMOS discharge control unit;

the first TypeC interface module is electrically connected with the first NMOS discharge control unit, and the second TypeC interface module is electrically connected with the second NMOS discharge control unit;

the first NMOS discharge control unit is electrically connected with the second NMOS discharge control unit, and the power supply module is electrically connected with the first NMOS discharge control unit, the second NMOS discharge control unit, the first NMOS switch module and the second NMOS switch module respectively;

the first NMOS switch module is respectively and electrically connected with an external controller and the first NMOS discharge control unit, and the second NMOS switch module is respectively and electrically connected with the external controller and the second NMOS discharge control unit.

Preferably, the power module comprises a power management unit and a boosting unit;

the power management unit is respectively and electrically connected with the first NMOS discharge control unit, the second NMOS discharge control unit and the boosting unit, and the boosting unit is respectively and electrically connected with the first NMOS switch module and the second NMOS switch module.

Preferably, the first NMOS switch module includes a first NMOS transistor and a second NMOS transistor;

the drain electrode of the first NMOS tube is respectively and electrically connected with the power module and the first NMOS discharge control unit, the source electrode of the first NMOS tube is grounded, the grid electrode of the first NMOS tube is respectively and electrically connected with the drain electrode of the second NMOS tube and the power module, the source electrode of the second NMOS tube is grounded, and the grid electrode of the second NMOS tube is electrically connected with the external controller.

Preferably, the second NMOS switch module includes a third NMOS transistor and a fourth NMOS transistor;

the drain electrode of the third NMOS tube is respectively and electrically connected with the power module and the second NMOS discharge control unit, the source electrode of the third NMOS tube is grounded, the grid electrode of the third NMOS tube is respectively and electrically connected with the drain electrode of the fourth NMOS tube and the power module, the source electrode of the fourth NMOS tube is grounded, and the grid electrode of the fourth NMOS tube is electrically connected with the external controller.

Preferably, the first NMOS discharge control unit includes a fifth NMOS transistor and a first diode;

the grid electrode of the fifth NMOS tube is electrically connected with the drain electrode of the first NMOS tube, the source electrode of the fifth NMOS tube is respectively and electrically connected with the first TypeC interface module and the anode of the first diode, and the drain electrode of the fifth NMOS tube is respectively and electrically connected with the cathode of the first diode, the power supply module and the second NMOS switch module.

Preferably, the second NMOS discharge control unit includes a sixth NMOS transistor and a second diode;

the grid electrode of the sixth NMOS tube is electrically connected with the drain electrode of the third NMOS tube, the source electrode of the sixth NMOS tube is electrically connected with the first TypeC interface module and the anode of the second diode respectively, and the drain electrode of the sixth NMOS tube is electrically connected with the cathode of the second diode, the power module and the first NMOS switch module respectively.

Preferably, the first NMOS switch module further includes a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor;

the first end of the first resistor is electrically connected with the drain electrode of the first NMOS tube, and the second end of the first resistor is electrically connected with the power supply module; the first end of the second resistor is electrically connected with the grid electrode of the first NMOS tube, the second end of the second resistor is respectively electrically connected with the drain electrode of the second NMOS tube and the first end of the third resistor, and the second end of the third resistor is electrically connected with the power supply module; the grid electrode of the second NMOS tube is electrically connected with the first end of the fourth resistor, the second end of the fourth resistor is respectively electrically connected with the first end of the fifth resistor and the external controller, and the second end of the fifth resistor is grounded.

Preferably, the second NMOS discharge control unit further includes a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, and a tenth resistor;

the first end of the sixth resistor is electrically connected with the drain electrode of the third NMOS tube, and the second end of the sixth resistor is electrically connected with the power supply module; the first end of the seventh resistor is electrically connected with the grid electrode of the third NMOS tube, the second end of the seventh resistor is electrically connected with the drain electrode of the fourth NMOS tube and the first end of the eighth resistor respectively, and the second end of the eighth resistor is electrically connected with the power supply module; the grid electrode of the fourth NMOS tube is electrically connected with the first end of the ninth resistor, the second end of the ninth resistor is respectively electrically connected with the first end of the tenth resistor and the external controller, and the second end of the tenth resistor is grounded.

In order to solve the technical problem, the application provides a TypeC power path management device, which comprises a TypeC power path management circuit.

The TypeC power path management circuit and the device have the following beneficial effects that the TypeC power path management circuit disclosed by the utility model comprises: the device comprises a power supply module, a first TypeC interface module, a second TypeC interface module, a first NMOS switch module, a second NMOS switch module and a discharge control module; the discharge control module comprises a first NMOS discharge control unit and a second NMOS discharge control unit; when the external controller outputs a first level signal to the first NMOS switch module or outputs a second level signal to the second NMOS switch module, the corresponding first NMOS switch module or second NMOS switch module is conducted; when the first NMOS switch module is turned on, the grid voltage of an NMOS tube in the first NMOS discharge control unit is larger than the source voltage, and the NMOS tube in the first NMOS discharge control unit is turned on, so that the power supply module outputs voltage to a corresponding first load through the first typeC interface module; when the second NMOS switch module is turned on, the grid voltage of the NMOS tube in the second NMOS discharge control unit is larger than the source voltage, and the NMOS tube in the second NMOS discharge control unit is turned on, so that the power supply module outputs voltage to a corresponding second load through the second TypeC interface module. Therefore, the power path management based on the NMOS is realized, so that the NMOS can drive a load under the low-power condition, and the reliable work of the output load is realized.

Drawings

In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the present utility model will be further described with reference to the accompanying drawings and embodiments, in which the drawings in the following description are only some embodiments of the present utility model, and other drawings may be obtained by those skilled in the art without inventive effort:

FIG. 1 is a schematic diagram of a TypeC power path management circuit according to a preferred embodiment of the present utility model;

FIG. 2 is a schematic circuit diagram of a first TypeC interface module of a TypeC power path management circuit in accordance with a preferred embodiment of the present utility model;

FIG. 3 is a schematic circuit diagram of a second TypeC interface module of the TypeC power path management circuit in accordance with the preferred embodiment of the present utility model;

FIG. 4 is a schematic circuit diagram of a first NMOS discharge control unit of a TypeC power path management circuit according to a preferred embodiment of the present utility model;

FIG. 5 is a schematic circuit diagram of a second NMOS discharge control unit of a TypeC power path management circuit according to a preferred embodiment of the present utility model;

fig. 6 is a schematic circuit diagram of a discharge control module of a TypeC power path management circuit according to a preferred embodiment of the present utility model.

Detailed Description

The core of the application is to provide a TypeC power path management circuit and device, and the application realizes the power path management based on NMOS, so that the NMOS can drive a load under a low power condition, and the reliable work of an output load is realized.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a TypeC power path management circuit provided in the present application, which includes a power module 1, a first TypeC interface module 2, a second TypeC interface module 3, a first NMOS switch module 4, a second NMOS switch module 5, and a discharge control module; the discharge control module includes a first NMOS discharge control unit 61 and a second NMOS discharge control unit 62;

the first typeC interface module 2 is electrically connected with the first NMOS discharge control unit 61, and the second typeC interface module 3 is electrically connected with the second NMOS discharge control unit 62;

the first NMOS discharge control unit 61 is electrically connected with the second NMOS discharge control unit 62, and the power module 1 is electrically connected with the first NMOS discharge control unit 61, the second NMOS discharge control unit 62, the first NMOS switch module 4 and the second NMOS switch module 5, respectively;

the first NMOS switch module 4 is electrically connected to the external controller and the first NMOS discharge control unit 61, respectively, and the second NMOS switch module 5 is electrically connected to the external controller and the second NMOS discharge control unit 62, respectively.

In the prior art, common switching transistors include an NMOS (N-channel metal oxide semiconductor field effect transistor) and a PMOS (P-channel metal oxide semiconductor field effect transistor). They are all one kind of MOSFET (metal oxide semiconductor field effect transistor) and have the features of low voltage drop, low internal resistance, high switching speed, etc. The on-resistance of the NMOS is lower than that of the PMOS by more than half. However, most power path management circuits still use PMOS as the switching transistor because NMOS has a disadvantage in that its gate voltage must be higher than the source voltage to turn on, whereas PMOS, in contrast, must be lower than the source voltage to turn on. This results in the problem that the NMOS cannot drive the load under low power conditions. There is no power path management circuit in the prior art that can overcome the disadvantages of NMOS and take advantage of the advantages thereof. This presents great inconvenience and trouble to the user.

Aiming at the defects, the reliable work of the output load under the low-power condition is realized through the cooperation of the power module 1, the first TypeC interface module 2, the second TypeC interface module 3, the first NMOS switch module 4, the second NMOS switch module 5 and the discharge control module.

It is worth to say that, this application is the power route management circuit based on NMOS pipe, and NMOS pipe has low pressure drop, low internal resistance, high switching speed's characteristics, and the on internal resistance of NMOS is more than half lower than the on resistance of PMOS. Therefore, the power of the method is low, and the response speed is high.

Specifically, in this embodiment, the external controller outputs a first level signal to the first NMOS switch module, the first NMOS switch module is turned on, the turn-on voltage is transmitted to the first NMOS discharge control unit, the NMOS transistor in the first NMOS discharge control unit has a gate voltage greater than the source voltage, and the NMOS transistor in the first NMOS discharge control unit is turned on, so that the power module outputs a voltage to a corresponding first load through the first TypeC interface module.

Specifically, in this embodiment, the external controller outputs the second level signal to the second NMOS switch module, the second NMOS switch module is turned on, the turn-on voltage is transmitted to the second NMOS discharge control unit, the gate voltage of the NMOS tube in the second NMOS discharge control unit is greater than the source voltage, and the NMOS tube in the second NMOS discharge control unit is turned on, so that the power module outputs the voltage to the corresponding second load through the second TypeC interface module.

Specifically, the external controller may be provided as an MCU controller, which is not particularly limited herein. Alternatively, the external controller may be implemented by a power manager in the power module, which is not specifically limited herein.

In summary, the utility model provides a typeC power path management circuit, which comprises a power module 1, a first typeC interface module 2, a second typeC interface module 3, a first NMOS switch module 4, a second NMOS switch module 5 and a discharge control module; the discharge control module includes a first NMOS discharge control unit 61 and a second NMOS discharge control unit 62; when the first NMOS switch module 4 is turned on, the gate voltage of the NMOS transistor in the first NMOS discharge control unit 61 is greater than the source voltage, and the NMOS transistor in the first NMOS discharge control unit 61 is turned on, so that the power module 1 outputs a voltage to a corresponding first load through the first TypeC interface module 2; when the second NMOS switch module 5 is turned on, the gate voltage of the NMOS transistor in the second NMOS discharge control unit 62 is greater than the source voltage, and the NMOS transistor in the second NMOS discharge control unit 62 is turned on, so that the power module 1 outputs a voltage to the corresponding second load through the second TypeC interface module 3. Therefore, the power path management based on the NMOS is realized, so that the NMOS can drive a load under the low-power condition, and the reliable work of the output load is realized.

Based on the above embodiments:

as a preferred embodiment, the power module 1 includes a power management unit 11 and a boosting unit 12;

the power management unit 11 is electrically connected to the first NMOS discharge control unit 61, the second NMOS discharge control unit 62, and the boost unit 12 is electrically connected to the first NMOS switch module 4 and the second NMOS switch module 5, respectively.

Specifically, in the present embodiment, the power management unit 11 is provided as a BUCK DC-DC power manager, and the model of the power management unit 11 may be provided as MT3905, and the model of the power management unit 11 is not particularly limited herein.

Specifically, in the present embodiment, the booster unit 12 may be implemented with an existing booster circuit, and is not particularly limited herein.

Referring to fig. 2, fig. 2 is a schematic circuit diagram of a first TypeC interface module 2 provided in the present application.

Referring to fig. 3, fig. 3 is a schematic circuit diagram of a second TypeC interface module 3 provided in the present application.

Referring to fig. 4, fig. 4 is a schematic circuit diagram of a first NMOS discharge control unit 61 provided in the present application.

As a preferred embodiment, the first NMOS switch module 4 includes a first NMOS transistor QP21 and a second NMOS transistor QP22;

the drain electrode of the first NMOS transistor QP21 is electrically connected to the power module 1 and the first NMOS discharge control unit 61, the source electrode of the first NMOS transistor QP21 is grounded, the gate electrode of the first NMOS transistor QP21 is electrically connected to the drain electrode of the second NMOS transistor QP22 and the power module 1, the source electrode of the second NMOS transistor QP22 is grounded, and the gate electrode of the second NMOS transistor QP22 is electrically connected to the external controller.

Referring to fig. 5, fig. 5 is a schematic circuit diagram of a second NMOS discharge control unit 62 provided in the present application.

As a preferred embodiment, the second NMOS switch module 5 includes a third NMOS transistor QP23 and a fourth NMOS transistor QP24;

the drain electrode of the third NMOS transistor QP23 is electrically connected to the power module 1 and the second NMOS discharge control unit 62, the source electrode of the third NMOS transistor QP23 is grounded, the gate electrode of the third NMOS transistor QP23 is electrically connected to the drain electrode of the fourth NMOS transistor QP24 and the power module 1, the source electrode of the fourth NMOS transistor QP24 is grounded, and the gate electrode of the fourth NMOS transistor QP24 is electrically connected to the external controller.

Referring to fig. 6, fig. 6 is a schematic circuit diagram of a discharge control module provided in the present application.

As a preferred embodiment, the first NMOS discharge control unit 61 includes a fifth NMOS transistor QP26A and a first diode DP5;

the gate of the fifth NMOS transistor QP26A is electrically connected to the drain of the first NMOS transistor QP21, the source of the fifth NMOS transistor QP26A is electrically connected to the anodes of the first TypeC interface module 2 and the first diode DP5, and the drain of the fifth NMOS transistor QP26A is electrically connected to the cathode of the first diode DP5, the power supply module 1, and the second NMOS switch module 5, respectively.

As a preferred embodiment, the second NMOS discharge control unit 62 includes a sixth NMOS transistor QP25B and a second diode DP6;

the gate of the sixth NMOS transistor QP25B is electrically connected to the drain of the third NMOS transistor QP23, the source of the sixth NMOS transistor QP25B is electrically connected to the anodes of the first TypeC interface module 2 and the second diode DP6, and the drain of the sixth NMOS transistor QP25B is electrically connected to the cathode of the second diode DP6, the power supply module 1, and the first NMOS switch module 4, respectively.

As a preferred embodiment, the first NMOS switch module further includes a first resistor RP87, a second resistor RP86, a third resistor RP85, a fourth resistor RP84, and a fifth resistor RP92;

a first end of the first resistor RP87 is electrically connected with the drain electrode of the first NMOS tube QP21, and a second end of the first resistor RP87 is electrically connected with the power module 1; the first end of the second resistor RP86 is electrically connected with the grid electrode of the first NMOS tube QP21, the second end of the second resistor RP86 is respectively electrically connected with the drain electrode of the second NMOS tube QP22 and the first end of the third resistor RP85, and the second end of the third resistor RP85 is electrically connected with the power module 1; the gate of the second NMOS transistor QP22 is electrically connected to the first end of the fourth resistor RP84, the second end of the fourth resistor RP84 is electrically connected to the first end of the fifth resistor RP92 and the external controller, and the second end of the fifth resistor RP92 is grounded.

As a preferred embodiment, the second NMOS discharge control unit 62 further includes a sixth resistor RP91, a seventh resistor RP90, an eighth resistor RP89, a ninth resistor RP88, and a tenth resistor RP93;

a first end of the sixth resistor RP91 is electrically connected to the drain of the third NMOS transistor QP23, and a second end of the sixth resistor RP91 is electrically connected to the power module 1; the first end of the seventh resistor RP90 is electrically connected with the grid electrode of the third NMOS tube QP23, the second end of the seventh resistor RP90 is respectively electrically connected with the drain electrode of the fourth NMOS tube QP24 and the first end of the eighth resistor RP89, and the second end of the eighth resistor RP89 is electrically connected with the power module 1; the gate of the fourth NMOS transistor QP24 is electrically connected to the first end of the ninth resistor RP88, the second end of the ninth resistor RP88 is electrically connected to the first end of the tenth resistor RP93 and the external controller, and the second end of the tenth resistor RP93 is grounded.

Specifically, in this embodiment, the external controller outputs the first level signal to the second NMOS transistor QP22, pulls up the gate of the second NMOS transistor QP22, and the second NMOS transistor QP22 is turned on, so that the first NMOS transistor QP21 is turned off, so that the drain voltage of the first NMOS transistor QP21 becomes high, the C1-MOS2 EN outputs the voltage to the first NMOS discharge control unit 61, the gate voltage of the fifth NMOS transistor QP26A in the first NMOS discharge control unit 61 becomes high, so that the gate voltage of the fifth NMOS transistor QP26A is greater than the source voltage, and the fifth NMOS transistor QP26A is turned on, so that the power module 1 outputs the voltage to the corresponding first load through the first TypeC interface module.

Specifically, in this embodiment, the external controller outputs the second level signal to the fourth NMOS transistor QP24, pulls up the gate of the fourth NMOS transistor QP24, and the fourth NMOS transistor QP24 is turned on, so that the third NMOS transistor QP23 is turned off, so that the drain voltage of the third NMOS transistor QP23 becomes high, the C0-MOS2 EN output voltage is output to the second NMOS discharge control unit 62, the gate voltage of the sixth NMOS transistor QP25B in the second NMOS discharge control unit 62 becomes high, the gate voltage of the sixth NMOS transistor QP25B is greater than the source voltage, and the sixth NMOS transistor QP25B is turned on, so that the power module outputs the voltage to the corresponding first load through the first TypeC interface module.

The utility model also provides a TypeC power path management device, a TypeC power path management circuit who includes.

For an introduction of a TypeC power path management circuit provided in the present application, please refer to the above embodiment, and the description is omitted herein.

It should be noted that in this specification the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (9)

1. The typeC power path management circuit is characterized by comprising a power supply module, a first typeC interface module, a second typeC interface module, a first NMOS switch module, a second NMOS switch module and a discharge control module; the discharge control module comprises a first NMOS discharge control unit and a second NMOS discharge control unit;

the first TypeC interface module is electrically connected with the first NMOS discharge control unit, and the second TypeC interface module is electrically connected with the second NMOS discharge control unit;

the first NMOS discharge control unit is electrically connected with the second NMOS discharge control unit, and the power supply module is electrically connected with the first NMOS discharge control unit, the second NMOS discharge control unit, the first NMOS switch module and the second NMOS switch module respectively;

the first NMOS switch module is respectively and electrically connected with an external controller and the first NMOS discharge control unit, and the second NMOS switch module is respectively and electrically connected with the external controller and the second NMOS discharge control unit.

2. The TypeC power path management circuit of claim 1, wherein said power module comprises a power management unit and a boost unit;

the power management unit is respectively and electrically connected with the first NMOS discharge control unit, the second NMOS discharge control unit and the boosting unit, and the boosting unit is respectively and electrically connected with the first NMOS switch module and the second NMOS switch module.

3. The TypeC power path management circuit of claim 1, wherein said first NMOS switch module comprises a first NMOS transistor and a second NMOS transistor;

the drain electrode of the first NMOS tube is respectively and electrically connected with the power module and the first NMOS discharge control unit, the source electrode of the first NMOS tube is grounded, the grid electrode of the first NMOS tube is respectively and electrically connected with the drain electrode of the second NMOS tube and the power module, the source electrode of the second NMOS tube is grounded, and the grid electrode of the second NMOS tube is electrically connected with the external controller.

4. The TypeC power path management circuit of claim 1, wherein said second NMOS switch module comprises a third NMOS transistor and a fourth NMOS transistor;

the drain electrode of the third NMOS tube is respectively and electrically connected with the power module and the second NMOS discharge control unit, the source electrode of the third NMOS tube is grounded, the grid electrode of the third NMOS tube is respectively and electrically connected with the drain electrode of the fourth NMOS tube and the power module, the source electrode of the fourth NMOS tube is grounded, and the grid electrode of the fourth NMOS tube is electrically connected with the external controller.

5. A TypeC power path management circuit according to claim 3, wherein said first NMOS discharge control unit comprises a fifth NMOS transistor and a first diode;

the grid electrode of the fifth NMOS tube is electrically connected with the drain electrode of the first NMOS tube, the source electrode of the fifth NMOS tube is respectively and electrically connected with the first TypeC interface module and the anode of the first diode, and the drain electrode of the fifth NMOS tube is respectively and electrically connected with the cathode of the first diode, the power supply module and the second NMOS switch module.

6. The TypeC power path management circuit of claim 4, wherein said second NMOS discharge control unit comprises a sixth NMOS transistor and a second diode;

the grid electrode of the sixth NMOS tube is electrically connected with the drain electrode of the third NMOS tube, the source electrode of the sixth NMOS tube is electrically connected with the first TypeC interface module and the anode of the second diode respectively, and the drain electrode of the sixth NMOS tube is electrically connected with the cathode of the second diode, the power module and the first NMOS switch module respectively.

7. A TypeC power path management circuit according to claim 3, wherein said first NMOS switch module further comprises a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor;

the first end of the first resistor is electrically connected with the drain electrode of the first NMOS tube, and the second end of the first resistor is electrically connected with the power supply module; the first end of the second resistor is electrically connected with the grid electrode of the first NMOS tube, the second end of the second resistor is respectively electrically connected with the drain electrode of the second NMOS tube and the first end of the third resistor, and the second end of the third resistor is electrically connected with the power supply module; the grid electrode of the second NMOS tube is electrically connected with the first end of the fourth resistor, the second end of the fourth resistor is respectively electrically connected with the first end of the fifth resistor and the external controller, and the second end of the fifth resistor is grounded.

8. The TypeC power path management circuit of claim 4, wherein said second NMOS discharge control unit further comprises a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, and a tenth resistor;

the first end of the sixth resistor is electrically connected with the drain electrode of the third NMOS tube, and the second end of the sixth resistor is electrically connected with the power supply module; the first end of the seventh resistor is electrically connected with the grid electrode of the third NMOS tube, the second end of the seventh resistor is electrically connected with the drain electrode of the fourth NMOS tube and the first end of the eighth resistor respectively, and the second end of the eighth resistor is electrically connected with the power supply module; the grid electrode of the fourth NMOS tube is electrically connected with the first end of the ninth resistor, the second end of the ninth resistor is respectively electrically connected with the first end of the tenth resistor and the external controller, and the second end of the tenth resistor is grounded.

9. A TypeC power path management apparatus comprising a TypeC power path management circuit as claimed in any one of claims 1 to 8.