CN220672566U - Power semiconductor module and device - Google Patents

Abstract

The utility model discloses a power semiconductor module and equipment, wherein the power semiconductor module comprises: an upper radiator and a lower radiator; a substrate package assembly located between the upper heat spreader and the lower heat spreader; and the limiting piece is arranged between the upper radiator and the lower radiator so that the upper radiator is parallel to the lower radiator. The module and the device can ensure the parallelism of the upper radiator and the lower radiator, and realize the accurate control of the height of the module, thereby ensuring that the size of the packaged module meets the requirements and facilitating the installation effect of the application end of the module.

Description

Power semiconductor module and device

Technical Field

The present utility model relates to the field of semiconductor technologies, and in particular, to a power semiconductor module and apparatus.

Background

As power semiconductor modules are developed toward high power and high integration, heat generation problems become an increasingly prominent problem. The power semiconductor device generates a large amount of heat during operation, and if the heat cannot be effectively dissipated, the temperature of the device is increased, the performance is reduced and even damaged. Therefore, the demand for heat dissipation performance is also increasing. In the prior art, some progress has been made in the design of heat dissipation for power semiconductor modules. The traditional heat dissipation modes comprise single-sided heat dissipation, single-sided pinfin heat dissipation, double-sided pinfin heat dissipation and the like. Among them, the double sided pinfin heat sink is widely used in power semiconductor modules due to its large heat dissipation surface area and channels.

However, the conventional double sided pinfin radiator has difficulty in precisely controlling the parallelism of the double sided radiator after the assembly is completed, which may result in the disqualification of the size of the final packaged module, affecting the installation effect of the module use end.

Disclosure of Invention

The present utility model aims to solve at least one of the technical problems existing in the prior art. Therefore, a first object of the present utility model is to provide a power semiconductor module, which can ensure the parallelism between the upper radiator and the lower radiator, and realize the precise control of the module height, so as to ensure that the size of the package module meets the requirement, and facilitate the installation effect of the module using end.

A second object of the utility model is to propose a device.

In order to achieve the above object, a power semiconductor module according to an embodiment of a first aspect of the present utility model includes: a power chip substrate assembly, an upper heat sink, and a lower heat sink, the power chip substrate assembly being located between the upper heat sink and the lower heat sink; and the limiting piece is arranged between the upper radiator and the lower radiator so that the upper radiator and the lower radiator are mutually parallel.

According to the power semiconductor module provided by the embodiment of the utility model, the upper radiator and the lower radiator keep consistent interval and parallel relation in the vertical direction due to the existence of the limiting piece based on the position constraint of the limiting piece, the accurate control of the position and the size of the upper radiator and the lower radiator can realize the parallel alignment of the two radiators, and the uniform and consistent gap between the two radiators is ensured, so that the accurate control of the height of the module is realized, the size of the packaged module meets the requirement, and the installation effect of the use end of the module is facilitated.

In some embodiments, the upper heat spreader includes a first heat conductive plate and a first pin fin disposed on the first heat conductive plate; the lower radiator comprises a second heat conducting plate and second pin fins arranged on the second heat conducting plate; the first heat conducting plate and the second heat conducting plate are oppositely arranged, and the power chip substrate assembly is located between the first heat conducting plate and the second heat conducting plate, so that the opposite surfaces of the first heat conducting plate and the second heat conducting plate are parallel to each other.

In some embodiments, the limiting member is located at a side of the power chip substrate assembly, and the limiting member is disposed at corresponding edge positions of the upper heat sink and the lower heat sink, so that stable support can be provided, precise control of the size and the gap is facilitated, and the chip layout is not disturbed, so that the chip layout is more free and flexible and is not limited by the limiting member.

In some embodiments, the stop comprises: the first limiting block is positioned on the first side of the power chip substrate assembly and is arranged between the corresponding first edge positions of the upper radiator and the lower radiator along the length direction of the module; the second limiting block is positioned on the second side of the power chip substrate assembly and is arranged between the corresponding second edge positions of the upper radiator and the lower radiator along the length direction of the module; the first limiting block and the second limiting block are identical in height; wherein a first side of the power chip substrate assembly is opposite a second side of the power chip substrate assembly. By arranging the first limiting block and the second limiting block on different sides of the power chip substrate assembly, limiting control of the power semiconductor module in the module length direction can be achieved.

In some embodiments, the first limiting block is one or more, the second limiting block is one or more, and the first limiting blocks and/or the second limiting blocks are arranged at intervals, so that greater flexibility and adaptability can be provided to meet the limiting requirements of power semiconductor modules with different sizes and shapes.

In some embodiments, the stop comprises: the third limiting block is positioned on a third side of the power chip substrate assembly and is arranged between corresponding third edge positions of the upper radiator and the lower radiator along the width direction of the module; a fourth stopper located at a fourth side of the power chip substrate assembly and disposed between corresponding fourth edge positions of the upper and lower heat sinks in the module width direction; the heights of the third limiting block, the fourth limiting block, the first limiting block and the second limiting block are uniform; wherein the third side of the power chip substrate assembly is opposite the fourth side of the power chip substrate assembly. By arranging the third and fourth limiting blocks on different sides of the power chip substrate assembly, limiting control of the power semiconductor module in the module width direction can be achieved.

In some embodiments, the third limiting block is one or more, the fourth limiting block is one or more, and the third limiting blocks and/or the fourth limiting blocks are arranged at intervals, so that greater flexibility and adaptability can be provided to meet the limiting requirements of power semiconductor modules with different sizes and shapes.

In some embodiments, the stop is one of a copper block and a silver block.

In some embodiments, the power chip substrate assembly comprises: the upper substrate packaging body is connected with the lower substrate packaging body, and the upper substrate packaging body and the lower substrate packaging body are oppositely arranged; the upper radiator is arranged on the upper substrate packaging body, and the lower radiator is arranged on the lower substrate packaging body.

In some embodiments, the upper substrate package includes: the front side of the upper substrate is provided with a first chip circuit layer; the first chip is arranged on the first chip circuit layer in a building mode; an upper substrate terminal connected with the first chip circuit layer; the lower substrate package includes: a lower substrate, wherein a second chip circuit layer is arranged on the front surface of the lower substrate; the second chip is arranged on the second chip circuit layer in a building mode; a lower substrate terminal connected with the second chip circuit layer; the front of the upper substrate and the front of the lower substrate are arranged oppositely, a supporting block is arranged between the upper substrate and the lower substrate, and the first chip and the second chip are arranged at intervals.

In some embodiments, the upper substrate package includes: the front side of the upper substrate is provided with a first chip circuit layer; an upper substrate terminal connected with the first chip circuit layer; the lower substrate package includes: a lower substrate, wherein a second chip circuit layer is arranged on the front surface of the lower substrate; a lower substrate terminal connected with the second chip circuit layer; the power chip substrate assembly further comprises a first chip and a second chip, wherein the first chip and the second chip are respectively arranged on the first chip circuit layer or the second chip circuit layer; the front of the upper substrate and the front of the lower substrate are arranged oppositely, a supporting block is arranged between the upper substrate and the lower substrate, and the first chip and the second chip are arranged at intervals.

In some embodiments, the first chip and the second chip are staggered.

To achieve the above object, an apparatus according to an embodiment of the second aspect of the present utility model comprises at least one power semiconductor module according to the above embodiment.

According to the device provided by the embodiment of the utility model, by adopting the power semiconductor module disclosed by the embodiment of the utility model, the upper radiator and the lower radiator can be ensured to be parallel, and the accurate control of the height of the module is realized, so that the dimension of the packaging module is ensured to meet the requirement, and the problem of unqualified dimension is avoided.

Additional aspects and advantages of the utility model will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the utility model.

Drawings

The foregoing and/or additional aspects and advantages of the utility model will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:

fig. 1 is a schematic diagram of a power semiconductor module according to one embodiment of the utility model;

fig. 2 is a side view of a power semiconductor module according to one embodiment of the utility model;

FIG. 3 is a front view of a power chip substrate assembly according to one embodiment of the utility model;

fig. 4 is a front view of an upper substrate package according to an embodiment of the present utility model;

fig. 5 is a side view of an upper substrate package lead end according to one embodiment of the utility model;

fig. 6 is a front view of a lower substrate package according to an embodiment of the present utility model;

FIG. 7 is a side view of a lower substrate package lead end according to one embodiment of the utility model;

fig. 8 is a schematic diagram of a packaged power semiconductor module according to one embodiment of the utility model;

fig. 9 is a lead side test diagram of a packaged power semiconductor module according to one embodiment of the utility model;

fig. 10 is a block diagram of an apparatus according to one embodiment of the utility model.

Reference numerals:

the apparatus 100;

a power semiconductor module 1;

an upper radiator 10; a lower radiator 20; a power chip substrate assembly 30; a stopper 40;

an upper substrate package 31; a lower substrate package 32;

an upper substrate 311; a first chip 312; a first chip circuit layer 313; an upper substrate terminal 314; a support block 315; a lower substrate 321; a second chip 322; a second chip circuit layer 323; lower substrate terminal 324.

Detailed Description

Embodiments of the present utility model will be described in detail below, by way of example with reference to the accompanying drawings.

A power semiconductor module according to an embodiment of the first aspect of the present utility model is described below with reference to fig. 1 to 9.

Fig. 1 is a schematic view of a power semiconductor module according to an embodiment of the present utility model, and as shown in fig. 1, a power semiconductor module 1 includes: an upper heat spreader 10, a lower heat spreader 20, a power chip substrate assembly 30, and a limiter 40.

The upper heat sink 10 may refer to a heat sink located at the top of or above the power semiconductor module 1, and the lower heat sink 20 may refer to a heat sink located at the bottom of or below the power semiconductor module 1. These heat sinks may be made of a material having good heat dissipation properties, such as an aluminum alloy or a copper alloy, for effectively dissipating heat generated from the power semiconductor device. In some embodiments, the heat sink may have a Pinfin structure, which is a heat dissipation structure having a fine fin shape, which may increase the surface area of the heat sink and improve the heat dissipation effect. This structure can increase the heat exchange area between the heat and the surrounding environment, thereby enhancing the heat dissipation performance. Other shapes of heat dissipation structures than pinfin structures may be used to achieve similar effects.

The power chip substrate assembly 30 is located between the upper heat spreader 10 and the lower heat spreader 20, and serves as a support and a fixture. The power chip substrate assembly 30 may be composed of a plurality of components such as an upper substrate, a lower substrate, and lead terminals. These components may be sintered, welded, glued or otherwise joined together to form a package structure.

In addition, the structural design of the power chip substrate assembly 30 requires consideration of a number of factors, such as space utilization efficiency, heat dissipation, signal transmission, and electrical isolation. Optimizing the design of the package structure can improve the overall performance and reliability of the module. At the same time, the power chip substrate assembly 30 is also provided with sufficient mechanical strength and stability to ensure reliability and stability of the entire power semiconductor module 1 during use.

In some embodiments, as shown in fig. 1 and 2, a stopper 40 is provided between the upper and lower heat sinks 10 and 20 for ensuring that the upper and lower heat sinks 10 and 20 are aligned in parallel to maintain a good heat dissipation effect. The spacing member 40 may be a metal block, such as a copper block or silver block, or the like, that is secured to the power chip substrate assembly 30. These metal blocks form a limit between the upper radiator 10 and the lower radiator 20 by means of the radiator plate holders provided at the upper and lower radiators, so as to ensure the parallel arrangement of the two radiators. The stopper 40 may function to ensure that it maintains a fixed position between the upper heat sink 10 and the lower heat sink 20 by limiting the range of movement of the power chip substrate assembly 30. Therefore, the parallel alignment of the two radiators can be achieved by precisely controlling the position and the size of the limiting member 40, and the problem that the parallelism of the two radiators is difficult to precisely control after the assembly of the conventional double sided pinfin radiator is completed is solved.

According to the power semiconductor module 1 in the embodiment of the utility model, based on the position constraint of the limiting piece 40, the existence of the limiting piece 40 enables the upper radiator 10 and the lower radiator 20 to keep consistent interval and parallel relation in the vertical direction, and because the limiting piece 40 is positioned on the side surface, the accurate control of the position and the size of the limiting piece can realize the parallel alignment of the two radiators, ensure the uniform and consistent gap between the two radiators, thereby realizing the accurate control of the height of the module, ensuring the size of the packaging module to meet the requirement, and facilitating the installation effect of the use end of the module.

As shown in fig. 2, the upper heat spreader 10 includes a first heat conductive plate 11 and first pin fins 12 provided to the first heat conductive plate 11; the lower heat sink 20 includes a second heat conductive plate 21 and second pin fins 22 provided to the second heat conductive plate 21; the first heat conductive plate 11 is disposed opposite to the second heat conductive plate 21, and the power chip substrate assembly 30 is located between the first heat conductive plate 11 and the second heat conductive plate 21 such that opposite faces of the first heat conductive plate 11 and the second heat conductive plate 21 are parallel to each other. The gap between the upper radiator and the lower radiator is ensured to be uniform and consistent, so that the accurate control of the height of the module is realized.

As shown in fig. 1 and 2, the stopper 40 is located at a side of the power chip substrate assembly 30, and the stopper 40 is disposed at corresponding edge positions of the upper and lower heat sinks 10 and 20. The reason for providing the limiting member 40 at the edge position of the radiator is as follows:

first, locating the stop 40 at the edge position better secures the heat sink and provides stable support. The edge position is closer to the fixed structure than the middle position of the radiator, so that the movement and shaking of the radiator can be more effectively restrained, and the stability of the radiator can be maintained. Second, the edge locations typically have well-defined boundaries and contours, facilitating precise control of the dimensions and gaps. By locating the stop 40 at the edge position, a uniform gap between the heat sinks can be more easily achieved, ensuring that they remain parallel and at a consistent spacing. In addition, the positioning of the stopper 40 at the edge position can avoid the interference to the chip layout to the maximum extent. Since the chip is generally located in the central area of the heat sink, the placement of the limiting member 40 at the edge position can ensure free space in the chip area, so that the layout of the chip is more free and flexible, and is not limited by the limiting member 40.

In some embodiments, the limiter 40 comprises: the first limiting block and the second limiting block.

The first limiting block is located on a first side of the power chip substrate assembly 30, i.e., on one side surface of the power chip substrate assembly 30, and is disposed between corresponding first edge positions of the upper heat spreader 10 and the lower heat spreader 20 along the module length direction, and the second limiting block is located on a second side of the power chip substrate assembly 30, i.e., on the other side surface of the power chip substrate assembly 30, and is disposed between corresponding second edge positions of the upper heat spreader 10 and the lower heat spreader 20 along the module length direction. And the heights of the first limiting block and the second limiting block are consistent, namely, the two limiting blocks with the same height are arranged on two sides of the module, so that the upper radiator and the lower radiator are arranged in parallel.

In some embodiments, the first and second stop blocks may be secured in various ways, such as bolts, dowel pins, clamps, and the like. Their size and shape can be adjusted according to design requirements and the characteristics of the assembly. In addition, the materials of the first stopper and the second stopper are selected in consideration of mechanical strength, stability and heat resistance thereof to ensure that they can withstand and maintain a desired force and position.

Through setting up the first stopper of highly uniform and second stopper, realized the spacing control to power semiconductor module 1 at module length direction. The positions of the first stopper and the second stopper are set between the edge positions of the upper radiator 10 and the lower radiator 20, ensuring the position fixation of the two radiators in the module length direction. At the same time, the first side and the second side of the power chip substrate assembly 30 are opposite, ensuring the arrangement of the stoppers on different sides. Such a design ensures a stable and accurate position control of the power semiconductor module 1 in the module length direction.

In some embodiments, the first limiting block may be one or more, the second limiting block may be one or more, and the plurality of first limiting blocks and/or the second limiting blocks are arranged at intervals, so that the heights of the plurality of first limiting blocks and the plurality of second limiting blocks are uniform. This spacing provides greater flexibility and adaptability to meet the spacing requirements of power semiconductor modules 1 of different sizes and shapes. Through adjusting the interval between the stopper, can adapt to the dimensional change on the different module length direction. The arrangement of the intervals enables the position of the limiting block to be adjusted according to specific requirements so as to meet specific design requirements. Furthermore, the arrangement interval between the plurality of stoppers can increase the structural stability of the power semiconductor module 1. The spacing between the stops provides additional support and fixation points to make alignment between the heat sinks more stable. Through increasing the quantity and the interval of stopper, can strengthen the fixity and the shock resistance of module, make it can bear bigger power and vibration, avoided possible deformation or not hard up to keep the uniformity of height and size of module.

Furthermore, in some embodiments, the limiter 40 further comprises: the third limiting block and the fourth limiting block.

Wherein the third stopper is located at a third side of the power chip substrate assembly 30 and is disposed between corresponding third edge positions of the upper and lower heat sinks 10 and 20 in the module width direction. The fourth stopper is located at the fourth side of the power chip substrate assembly 30 and is disposed between corresponding fourth edge positions of the upper and lower heat sinks 10 and 20 in the module width direction. And the third limiting block, the fourth limiting block, the first limiting block and the second limiting block are uniform in height, namely limiting blocks with uniform heights are respectively arranged on the periphery of the module, so that the upper radiator and the lower radiator can be kept parallel.

In some embodiments, the third and fourth stop blocks may be secured in various ways, such as bolts, dowel pins, clamps, etc. Their size and shape can be adjusted according to design requirements and the characteristics of the assembly. In addition, the materials of the third stopper and the fourth stopper are selected in consideration of mechanical strength, stability and heat resistance thereof to ensure that they can withstand and maintain a desired force and position.

Through setting up the third stopper and the fourth stopper with first spacing and the high unanimity of second stopper, set up the stopper of high unanimity promptly respectively around the module, realized the spacing control at module width direction to power semiconductor module 1. The positions of the third stopper and the fourth stopper are set between the edge positions of the upper radiator 10 and the lower radiator 20, ensuring the positional fixation of the two radiators in the module width direction. At the same time, the third side of the power chip substrate assembly 30 is opposite to the fourth side, ensuring the arrangement of the limit blocks on different sides, such a design ensuring the stability and accurate position control of the power semiconductor module 1 in the module width direction.

The first limiting block and the second limiting block realize symmetrical limiting effects in the module length direction, and the third limiting block and the fourth limiting block realize symmetrical limiting effects in the module width direction, so that limiting forces of the power chip substrate assembly 30 in the module length direction and the module width direction can be balanced through the design. This helps to maintain an equilibrium state between the upper and lower heat sinks 10 and 20, avoiding offset or tilting, thereby providing a stable limiting effect. And, the symmetrical arrangement of the spacing members 40 helps to maintain an even heat conduction between the upper and lower heat sinks 10 and 20. Through the fixed position of stopper, can ensure that the clearance between the radiator is even and unanimous to promote the even transmission and the giving off of heat, improve the radiating effect.

In some embodiments, the third limiting block is one or more, the fourth limiting block is one or more, the plurality of third limiting blocks and/or the fourth limiting blocks are arranged at intervals, and the plurality of third limiting blocks and the fourth limiting blocks are uniform in height with the first limiting block and the second limiting block. As such, this spacing arrangement provides greater flexibility and adaptability to meet the spacing requirements of power semiconductor modules 1 of different sizes and shapes. Through adjusting the interval between the stopper, can adapt to the dimensional change in the different module width directions. The arrangement of the intervals enables the position of the limiting block to be adjusted according to specific requirements so as to meet specific design requirements. Furthermore, the arrangement interval between the plurality of stoppers can increase the structural stability of the power semiconductor module 1. The spacing between the stops provides additional support and fixation points to make alignment between the heat sinks more stable. Through increasing the quantity and the interval of stopper, can strengthen the fixity and the shock resistance of module, make it can bear bigger power and vibration, avoided possible deformation or not hard up to keep the uniformity of height and size of module.

In some embodiments, the limiting member 40 is one of a copper block and a silver block, because a large amount of heat is generated during the operation of the power semiconductor module 1, and it is necessary to efficiently conduct and dissipate the heat to keep the temperature of the module within a controllable range. Copper and silver are both good heat conducting materials with high thermal conductivity and good thermal conductivity properties that can rapidly transfer heat from the module to the heat sink and help the heat sink dissipate heat effectively. Therefore, copper or silver blocks are selected as the limiting members 40 to ensure that the heat of the module is effectively conducted and dissipated, keeping the module within a suitable operating temperature range.

Fig. 3 is a front view of a power chip substrate assembly according to one embodiment of the utility model, as shown in fig. 3, a power chip substrate assembly 30 includes: an upper substrate package 31 and a lower substrate package 32.

The upper substrate package 31 is located above the power semiconductor module 1, and the lower substrate package 32 is located below the power semiconductor module 1. They may be secured together by soldering to form a unitary power chip substrate assembly 30. The upper substrate package 31 is disposed opposite to the lower substrate package 32, i.e., they are disposed opposite to each other in the vertical direction.

The upper heat spreader 10 is disposed on the upper substrate package 31, and the lower heat spreader 20 is disposed on the lower substrate package 32. The heat sink is disposed on the substrate package to facilitate improved heat dissipation. This is because the power semiconductor device generates a large amount of heat during operation, and the heat sink is directly disposed on the substrate package to achieve tighter thermal coupling, thereby accelerating heat transfer and dissipation. This helps to maintain the temperature of the power semiconductor device within a controllable range, improving the reliability and performance of the module.

In some embodiments, the upper heat spreader 10 and the upper substrate package 31 may be connected using a solder layer, and likewise, the lower heat spreader 20 and the lower substrate package 32 may be connected using a solder layer. The solder layer may be a layer of thermally conductive glue, solder or other thermally conductive material for thermal contact and mechanical fixation between the heat spreader and the substrate package. Through the use of the soldering layer, a good heat conduction path is formed between the heat spreader and the substrate package, thereby efficiently transferring and dissipating heat.

It should be noted that the specific solder layers and connection patterns may vary from embodiment to embodiment. Instead of a solder layer, other suitable connection means, such as screws, clamping means, etc., may be used to ensure a secure connection of the upper heat spreader 10 to the upper substrate package 31. Such a design may ensure that the heat spreader remains in good contact with the power chip substrate assembly 30 during operation, achieving an efficient heat dissipation effect.

The structure of the upper substrate package will be specifically described with reference to fig. 4 and 5.

Wherein fig. 4 is a front view of an upper substrate package according to an embodiment of the present utility model, and fig. 5 is a lead terminal side view of the upper substrate package according to an embodiment of the present utility model. As shown in fig. 4 to 5, the upper substrate package 31 includes: an upper substrate 311, a first chip 312, and an upper substrate terminal 314.

The first chip circuit layer 313 is disposed on the front surface of the upper substrate 311, and the first chip circuit layer 313 may be any suitable circuit layer material, including but not limited to a copper circuit layer. In addition to copper, the circuit layer material may also include aluminum, gold, silver, and the like. The selection of appropriate materials depends on the specific application requirements and design considerations.

In some embodiments, the back surface of the upper substrate 311 is further provided with an insulating layer and a heat dissipation layer. The insulating layer may be a layer of insulating material located on the front side of the upper substrate 311, i.e., near the first chip circuit layer 313. Its function is to provide electrical insulation and isolation, preventing electrical currents from shorting or interfering between the chip circuit layers and other layers. The insulating layer plays an important role in protecting the circuit and improving the electrical performance in the power semiconductor module 1. The heat sink layer may be a layer of copper material located below the insulating layer. The main function of the semiconductor device is to provide a heat dissipation function, and heat generated by the power semiconductor device is effectively conducted and dissipated to the surrounding environment through the heat conducting copper material. The heat sink layer may exchange heat with an external environment via a heat sink or other heat sink device to maintain the temperature of the power semiconductor device within a controllable range.

In some embodiments, the first chip 312 may be a SIC (Si licon Carbide Chip, silicon carbide) chip, an IGBT (Insulated Gate Bipolar Transistor ), or other similar component. The SIC chip is a semiconductor device based on silicon carbide material, and has higher working temperature capability, lower conduction and switching loss, higher power density and higher switching speed compared with the traditional silicon chip. IGBTs are power semiconductor devices that combine the characteristics of field effect transistors and bipolar transistors, and have excellent performance in high voltage and high current applications, and are widely used in power control and switching applications. The first chip 312 is disposed on the first chip circuit layer 313, and may be arranged on the upper substrate 311 by sintering, soldering, or bonding.

As shown in fig. 5, in some embodiments the upper substrate terminals 314 may be fine leads or pads of metal wires or conductive material that are connected to the first chip circuit layer 313 by metal wires, solder or other connection means that establish electrical connection between the first chip 312 and external circuitry, enabling the transmission of electrical signals and power, enabling the first chip 312 to be effectively connected and in communication with external circuitry or components.

The structure of the lower substrate package 32 is specifically described below with reference to fig. 6 to 7.

Wherein fig. 6 is a front view of a lower substrate package according to one embodiment of the present utility model, and fig. 7 is a lead end side view of the lower substrate package according to one embodiment of the present utility model. As shown in fig. 6 to 7, the lower substrate package 32 includes: a lower substrate 321, a second chip 322, and lower substrate terminals 324.

The second chip circuit layer 323 is disposed on the front surface of the lower substrate 321, and the second chip circuit layer 323 may be any suitable circuit layer material, including but not limited to a copper circuit layer. In addition to copper, the circuit layer material may also include aluminum, gold, silver, and the like. The selection of appropriate materials depends on the specific application requirements and design considerations.

In some embodiments, the back surface of the lower substrate 321 is also provided with an insulating layer and a heat dissipation layer. The insulating layer may be a layer of insulating material on the front side of the lower substrate 321, i.e., adjacent to the second chip circuit layer 323, for providing electrical insulation and isolation, preventing electrical current from shorting or interfering between the chip circuit layer and other layers. The heat dissipation layer may be a layer of copper material located below the insulating layer for providing a heat dissipation function.

In some embodiments, the second chip 322 may also be a SIC (Sil icon Carbide Chip, silicon carbide) chip, an IGBT (Insulated Gate Bipolar Transistor ) or other similar component. The second chip 322 is disposed on the first chip circuit layer 313 and may be arranged on the lower substrate 321 by sintering, soldering, or bonding.

As shown in fig. 9, in some embodiments the lower substrate terminals 324 may be fine wires or pads of metal wires or conductive material that are connected to the second chip circuit layer 323 by metal wires, solder or other connection means that establish electrical connection between the second chip 322 and external circuitry, enabling the transmission of electrical signals and power, enabling the second chip 322 to be effectively connected and in communication with external circuitry or components.

In some embodiments, the front surface of the upper substrate 311 is disposed opposite to the front surface of the lower substrate 321, which are supported and fixed therebetween by the support blocks 315. This structure can keep the relative positions of the upper substrate 311 and the lower substrate 321 stable. The supporting block 315 may be a copper block or other supporting conductive heat dissipation device, and may be arranged above the chip by sintering, welding or bonding. A solder layer is then added over the support blocks 315 to achieve a stronger connection and better heat transfer.

In some embodiments, the first chip 312 and the second chip 322 are spaced between the upper substrate 311 and the lower substrate 321. That is, the first chip 312 and the second chip 322 are spaced between the upper and lower substrates 321 to form a stacked structure. The space can be effectively utilized by the mode of interval arrangement, electric connection and signal transmission between chips are realized, and the reliability and flexibility of the module are improved.

In other embodiments, the first chip 312 and the second chip 322 may also be provided on the same substrate side. Specifically, the upper substrate package 31 includes an upper substrate 311 and an upper substrate terminal 314. A first chip circuit layer 313 is disposed on the front surface of the upper substrate 311; the upper substrate terminal 314 is connected to the first chip circuit layer 313; the lower substrate package 32 includes a lower substrate 321 and a lower substrate terminal 324, and a second chip circuit layer 323 is disposed on the front surface of the lower substrate 321; the lower substrate terminal 324 is connected to the second chip circuit layer 323.

The power chip substrate assembly 30 further includes a first chip 312 and a second chip 322, where the first chip 312 and the second chip 322 are both disposed on the first chip circuit layer 313 or are both disposed on the second chip circuit layer 323; that is, the first chip 312 and the second chip 322 may be disposed on the upper substrate, the lower substrate, or one of the substrates, as in the first chip 312, and the second chip 322 may be disposed on the other substrate.

Wherein, the front of the upper substrate 311 is opposite to the front of the lower substrate 321, a supporting block 315 is disposed between the upper substrate 311 and the lower substrate 321, and the first chip 312 and the second chip 322 are disposed at intervals, so as to avoid short circuit and realize electrical connection and signal transmission between the chips.

Further, in the embodiment, the first chips 312 and the second chips 322 are staggered, so that uniformity of heat dissipation can be improved, and heat concentration can be avoided.

In summary, as shown in fig. 8 and 9, based on the double-sided pinfin radiator structure, the movement range of the power chip substrate assembly 30 is limited by arranging the limiting member 40 on the side surface of the power chip substrate assembly 30, so that the power chip substrate assembly 30 maintains a fixed position between the upper radiator 10 and the lower radiator 20, and the existence of the limiting member 40 maintains the upper radiator 10 and the lower radiator 20 in a consistent spaced and parallel relationship in the vertical direction, and since the limiting member 40 is located on the side surface, the accurate control of the position and the size of the limiting member can realize the parallel alignment of the two radiators, ensure the uniform and consistent gap between the two radiators, thereby realizing the accurate control of the module height, ensuring that the size of the packaged module meets the requirements, and facilitating the installation effect of the module at the use end. And moreover, the chips are distributed on the upper side and the lower side, so that a more uniform heat dissipation effect is realized, and the performance of the module is improved. In addition, the upper substrate terminal and the lower substrate terminal are led out, so that the use of an electric switching device is reduced, and the reliability of the module is improved.

An apparatus according to an embodiment of the present utility model is described below with reference to fig. 10.

Fig. 10 is a block diagram of a device according to one embodiment of the utility model, as shown in fig. 10, the device 100 comprising at least one power semiconductor module 1 as described in the above embodiments.

The device 100 according to the embodiment of the present utility model may be a power electronic device, such as an inverter, a rectifier, a frequency converter, an electric drive system, an electric vehicle controller, or the like. These devices 100 are used to process high power electrical signals and to achieve efficient power conversion. By integrating the power semiconductor module 1, the apparatus 100 can realize efficient and reliable power circuit control and heat dissipation management to meet the requirements of various application fields, such as industrial control, energy conversion, transportation, and the like.

According to the device 100 of the embodiment of the present utility model, by adopting the power semiconductor module 1 described in the above embodiment, it is ensured that the upper heat sink 10 is parallel to the lower heat sink 20, and precise control of the module height is achieved, so that the size of the packaged module is ensured to meet the requirements, and the installation effect of the module at the use end is facilitated.

In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the utility model. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples.

While embodiments of the present utility model have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the utility model, the scope of which is defined by the claims and their equivalents.

Claims (12)

1. A power semiconductor module, comprising:

a power chip substrate assembly, an upper heat sink, and a lower heat sink, the power chip substrate assembly being located between the upper heat sink and the lower heat sink;

the limiting piece is arranged between the upper radiator and the lower radiator so that the upper radiator and the lower radiator are parallel to each other;

the power chip substrate assembly includes: the upper substrate packaging body is connected with the lower substrate packaging body, and the upper substrate packaging body and the lower substrate packaging body are oppositely arranged;

the upper radiator is arranged on the upper substrate packaging body, and the lower radiator is arranged on the lower substrate packaging body.

2. The power semiconductor module of claim 1, wherein,

the upper radiator comprises a first heat conducting plate and a first pin fin arranged on the first heat conducting plate;

the lower radiator comprises a second heat conducting plate and second pin fins arranged on the second heat conducting plate;

the first heat conducting plate and the second heat conducting plate are oppositely arranged, the power chip substrate assembly is located between the first heat conducting plate and the second heat conducting plate, and the limiting piece is located between the first heat conducting plate and the second heat conducting plate, so that the opposite surfaces of the first heat conducting plate and the second heat conducting plate are parallel to each other.

3. The power semiconductor module of claim 1, wherein the stop is located on a side of the power chip substrate assembly and the stop is disposed at corresponding edge locations of the upper and lower heat sinks.

4. A power semiconductor module according to claim 3, wherein the limiting member comprises:

the first limiting block is positioned on the first side of the power chip substrate assembly and is arranged between corresponding first edge positions of the upper radiator and the lower radiator along the length direction of the module;

a second stopper located at a second side of the power chip substrate assembly and disposed between corresponding second edge positions of the upper and lower heat sinks in the module length direction;

the first limiting block and the second limiting block are identical in height;

wherein a first side of the power chip substrate assembly is opposite a second side of the power chip substrate assembly.

5. The power semiconductor module according to claim 4, wherein the first limiting block is one or more, the second limiting block is one or more, and a plurality of the first limiting blocks and/or the second limiting blocks are arranged at intervals.

6. The power semiconductor module of claim 4, wherein the limiting member comprises:

a third stopper located at a third side of the power chip substrate assembly and disposed between corresponding third edge positions of the upper and lower heat sinks in a module width direction;

a fourth stopper located at a fourth side of the power chip substrate assembly and disposed between corresponding fourth edge positions of the upper and lower heat sinks in the module width direction;

the heights of the third limiting block, the fourth limiting block, the first limiting block and the second limiting block are uniform;

wherein the third side of the power chip substrate assembly is opposite the fourth side of the power chip substrate assembly.

7. The power semiconductor module according to claim 6, wherein the third limiting block is one or more, the fourth limiting block is one or more, and a plurality of the third limiting blocks and/or the fourth limiting blocks are arranged at intervals.

8. The power semiconductor module of claim 1, wherein the limiting member is one of a copper block and a silver block.

9. The power semiconductor module of claim 1, wherein,

the upper substrate package includes:

the front side of the upper substrate is provided with a first chip circuit layer;

the first chip is arranged on the first chip circuit layer in a building mode;

an upper substrate terminal connected with the first chip circuit layer;

the lower substrate package includes:

a lower substrate, wherein a second chip circuit layer is arranged on the front surface of the lower substrate;

the second chip is arranged on the second chip circuit layer in a building mode;

a lower substrate terminal connected with the second chip circuit layer;

the front of the upper substrate and the front of the lower substrate are arranged oppositely, a supporting block is arranged between the upper substrate and the lower substrate, and the first chip and the second chip are arranged at intervals.

10. The power semiconductor module of claim 1, wherein,

the upper substrate package includes:

the front side of the upper substrate is provided with a first chip circuit layer;

an upper substrate terminal connected with the first chip circuit layer;

the lower substrate package includes:

a lower substrate, wherein a second chip circuit layer is arranged on the front surface of the lower substrate;

a lower substrate terminal connected with the second chip circuit layer;

the power chip substrate assembly further comprises a first chip and a second chip, wherein the first chip and the second chip are respectively arranged on the first chip circuit layer or the second chip circuit layer;

the front of the upper substrate and the front of the lower substrate are arranged oppositely, a supporting block is arranged between the upper substrate and the lower substrate, and the first chip and the second chip are arranged at intervals.

11. The power semiconductor module of claim 9 or 10, wherein the first chip and the second chip are staggered.

12. An apparatus comprising at least one power semiconductor module according to any one of claims 1-11.