CN220652010U - Semiconductor die mounting substrate and semiconductor device - Google Patents

Semiconductor die mounting substrate and semiconductor device Download PDF

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Publication number
CN220652010U
CN220652010U CN202321996447.XU CN202321996447U CN220652010U CN 220652010 U CN220652010 U CN 220652010U CN 202321996447 U CN202321996447 U CN 202321996447U CN 220652010 U CN220652010 U CN 220652010U
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China
Prior art keywords
tie bar
die
die pad
semiconductor
mounting substrate
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CN202321996447.XU
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Chinese (zh)
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D·维特洛
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STMicroelectronics SRL
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STMicroelectronics SRL
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Priority claimed from US18/224,701 external-priority patent/US20240038636A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49565—Side rails of the lead frame, e.g. with perforations, sprocket holes

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The present disclosure relates to a semiconductor die mounting substrate and a semiconductor device. A semiconductor die mounting substrate comprising: a plurality of die pads having a first surface, a second surface opposite the first surface and further having tie bars protruding from each die pad; wherein each tie bar has an intermediate split position; and wherein each tie bar has a hollow portion at each intermediate split location, the hollow portion defining a channel-shaped cross-sectional profile at the intermediate split location. With embodiments of the present disclosure, a tie bar that is easier to cut may be provided without compromising its stiffness.

Description

Semiconductor die mounting substrate and semiconductor device
Technical Field
The present specification relates to semiconductor devices.
The solutions described herein may be applied to packaged Integrated Circuits (ICs), for example in packages that include a leadframe with exposed pads.
Background
In the current manufacturing process of semiconductor devices, multiple devices fabricated simultaneously in a chain or ribbon are then separated into individual devices in a final "singulation" step.
Package singulation is the last step in the assembly process: once the protective packages are molded to complete the packages, each individual package is separated from the rest of the chain or belt.
This involves mechanically cutting (e.g., via a blade) tie bars in a leadframe strip (ribbon) that are common to devices in a chain or ribbon. Mechanical dicing causes stresses that may be on the basis of leadframe/die (package) separation. This is an undesirable effect that may lead to premature failure during reliability testing or during the operational lifetime of the device.
Conventional lead frames include uniform, e.g., rectangular tie bars having a constant thickness. This is the thickness of the copper tape (e.g., 0.2 mm) that makes up the leadframe.
The use of thinner tie bars may facilitate cutting during singulation, thereby reducing stresses that may exist on the basis of leadframe/die (package) separation. However, the use of thinner tie bars increases the risk of die pad tilting during assembly.
There is a need in the art to address the above-described problems.
Disclosure of Invention
It is an object of the present disclosure to provide a semiconductor die mounting substrate and a semiconductor device that at least partially address the above-mentioned problems of the prior art.
An aspect of the present disclosure provides a semiconductor die mounting substrate comprising: a plurality of die pads having a first surface, a second surface opposite the first surface and further having tie bars protruding from each die pad; wherein each tie bar has an intermediate split position; and wherein each tie bar has a hollow portion at each intermediate split location, the hollow portion defining a channel-shaped cross-sectional profile at the intermediate split location.
According to one or more embodiments, a hollow portion is provided in a surface of each tie bar extending from the second surface of the die pad.
According to one or more embodiments, wherein each tie bar has a length in a longitudinal direction extending away from the die pad, and wherein the hollow portion extends over a portion of the length in the longitudinal direction.
According to one or more embodiments, wherein each tie bar has an hourglass shape in the longitudinal direction, the hourglass shape having a centrally narrowed waist portion, and wherein the hollow portion is provided at the centrally narrowed waist portion.
In accordance with one or more embodiments, wherein each tie bar protrudes from a recessed portion of a die pad, the die pad has a lateral groove located laterally of the tie bar.
In accordance with one or more embodiments, wherein the semiconductor die mounting substrate is a tape substrate comprising a plurality of die pads distributed along a length of the tape substrate, wherein each tie bar protrudes from a die pad in a direction of the length of the tape substrate.
Another aspect of the present disclosure provides a semiconductor device including: a semiconductor die mounting substrate comprising a die pad having a first surface and a second surface opposite the first surface, and further comprising tie bar residues protruding from the die pad toward a distal singulation site; a semiconductor die mounted at a first surface of the die pad; and a package molded onto the semiconductor die mounted at the first surface of the die pad; wherein the tie bar residues each have a hollow portion at the distal split position; wherein the tie bar residues each have a channel-shaped cross-sectional profile at the distal segmentation location.
According to one or more embodiments, wherein a hollow portion is provided in a surface of each tie bar extending from the second surface of the die pad.
According to one or more embodiments, wherein each tie bar has a length in a longitudinal direction extending away from the die pad, and wherein the hollow portion extends over a portion of the length in the longitudinal direction.
In accordance with one or more embodiments, wherein each tie bar protrudes from a recessed portion of a die pad, the die pad has a lateral groove located laterally of the tie bar.
Embodiments of the present disclosure advantageously provide tie bars that are easier to cut without compromising their stiffness.
Drawings
One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:
fig. 1 is a plan view from the front or top side of a semiconductor device during fabrication;
fig. 2 is a plan view of the back or bottom surface of the semiconductor device of fig. 1;
fig. 3 is a plan view of the back or bottom surface of the semiconductor device of fig. 1 and 2, showing a later stage of the assembly process;
fig. 4 is a view of the portion of fig. 1 indicated by arrow IV, which is reproduced on an enlarged scale, with various elements removed for clarity;
FIG. 5 is a graph comparing the characteristics of a conventional tie bar and the tie bars described herein; and
fig. 6 is a side view of a semiconductor device as is described herein.
Detailed Description
Corresponding numerals and symbols in the various drawings generally indicate corresponding parts unless otherwise indicated.
The drawings are for clarity of illustration of related aspects of the embodiments and are not necessarily drawn to scale.
The edges of features depicted in the drawings do not necessarily represent the termination of the range of features.
In the following description, one or more specific details are set forth in order to provide a thorough understanding of examples of the embodiments described herein. Embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.
Reference in the framework of this specification to "one embodiment" or "an embodiment" is intended to indicate that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in one embodiment" that may occur in one or more points of the present specification do not necessarily refer to the same embodiment.
Furthermore, in one or more embodiments, the particular conformations, structures, or features may be combined in any suitable manner.
The headings/reference numerals used herein are provided for convenience only and thus do not limit the scope of protection or the scope of the embodiments.
For simplicity and ease of explanation, like parts or elements are denoted by like reference numerals throughout the various figures, and corresponding descriptions will not be repeated for each figure.
The semiconductor device contemplated herein includes a substrate (leadframe) 12, the substrate 12 including one or more die pads 12A, the die pads 12A having disposed thereon one or more semiconductor chips or dies 14 plus an array of conductive leads 12B.
As used herein, "chip" and "die" will be considered synonymous. For simplicity, a single die pad 12A is shown having a single integrated circuit semiconductor chip or die 14 mounted thereon.
The designation "leadframe" (or "leadframe") (see, for example, the united states patent and trademark office's USPC consolidated vocabulary) refers to a metal frame that provides support for an integrated circuit chip or die, as well as electrical leads that interconnect the die or integrated circuits in the chip to other components or contacts.
Essentially, the leadframe includes an array of conductive structures (or leads, e.g., 12B) extending inwardly from the contoured location in the direction of the semiconductor chip or die (e.g., 14), forming an array of conductive structures from a die pad (e.g., 12A) configured with at least one semiconductor chip or die 14 attached thereto. This may be accomplished by conventional means such as a die attach adhesive (e.g., a die attach film or DAF).
The leadframe 12 described herein may be of a pre-molded type, i.e., a leadframe type that includes an engraved metal (e.g., copper) structure that includes a die pad 12A and leads 12B formed by etching a metal sheet, and that includes empty spaces filled with resin 12C "pre-molded" over the engraved metal structure.
The semiconductor devices contemplated herein also include conductive structures (e.g., wires in a wire bond pattern) that couple the semiconductor chip(s) 14 to the wires 12B (external pads) in the substrate 12.
For simplicity, such wire bond patterns are not visible in the figures.
An insulating encapsulation (e.g., resin) 16 is molded over the assembly to shape to complete the plastic body of the device.
As an (at least partial) alternative to wire bonding patterns as previously discussed, a solution as described herein may include conductive formations provided via Laser Direct Structuring (LDS) of packages of LDS material, as taught, for example, by: U.S. patent publication: 2018/0342453A1, 2019/01015287A 1, 2020/0203264A1, 2020/031274A 1, 2021/0050226A1, 2021/0050299A1, 2021/0183748A1, or 2021/0305203A1 (all of which are incorporated herein by reference) are examples of using LDS technology.
As shown in the side view of fig. 6, the device 10 contemplated herein is intended to be mounted on a substrate S, such as a Printed Circuit Board (PCB), using, for example, solder material (not visible in the figures).
The device structures discussed so far are conventional in the art, which makes it unnecessary to provide a more detailed description here.
The present specification relates to a manufacturing process of a semiconductor device in which a plurality of devices are manufactured simultaneously to be finally separated into individual devices in a dividing step.
To this end, a device chain or tape is fabricated using, for example, a tape-like leadframe 12 (a portion of which is visible in fig. 1-3) with dies or chips 14 arranged onto respective die pads 12A. These die pads are coupled to the tape structure via so-called tie bars 20.
Once the plastic body of the device is completed by molding the insulating package 16 (see fig. 3), the individual devices 10 are separated from the chain or tape in a singulation step where the tie bars 20 are severed (e.g., via a rotary blade cut) at the cut line/plane T.
The segmentation discussed so far is also conventional in the art, which makes it unnecessary to provide a more detailed description here.
In summary, this assembly process includes providing a semiconductor die mounting substrate (e.g., a planar leadframe 12) that includes a plurality of die pads 12A having opposing first and second surfaces and tie bars 20 protruding (radially) from the die pads 12A (in the plane of the substrate 12). The tie bar has a longitudinal direction (X20).
The semiconductor die 14 is mounted at the first surface of the die pad 12A, and the package 16 is molded onto the semiconductor die 14 mounted at the first surface of the die pad 12A such that the plurality of semiconductor devices 10 are coupled to each other via tie bars 20 protruding from the die pad 12A.
As discussed, the encapsulation 16 may be: an insulating resin (e.g., epoxy) molded onto the semiconductor die 14 mounted at the first surface of the die pad 12A and incorporating (embedding) a wire bond pattern of wires electrically coupling each die 14 with wires in a corresponding array of wires 12B of the leadframe 12; or laser machining (e.g., laser direct structuring, LDS) and (electroless/electrolytic) metal growth may be applied to the laser activatable material thereon to provide conductive structures (vias/traces) that electrically couple each die 14 with leads in a corresponding array of leads 12B of leadframe 12 (see the aforementioned U.S. patent publication).
Finally, the rod 20 is cut transversely to the longitudinal direction X20 of the rod 20 at an intermediate dividing position. Thus, the semiconductor device 10 is divided into individual semiconductor devices.
As shown, the semiconductor die mounting substrate 12 is a tape substrate that includes a plurality of die pads 12A distributed along the length of the tape substrate 12, with tie bars 20 protruding from the plurality of die pads 12A, with a longitudinal direction X20 extending along the length of the tape substrate.
As can be seen in fig. 4, the tie bars 20 may have an hourglass shape with narrowed waist portions, for example in a plane parallel to the top and bottom surfaces of the lead frame, and the cut is made along a cut line T in the middle of the waist portions.
As discussed, stresses caused by mechanical dicing may cause the leadframe 12 to separate from the package 16; this may undesirably lead to premature failure during reliability testing or operational life of the device 10.
The conventional leadframe 12 includes a uniform, e.g., rectangular tie bar 20 having a constant thickness: this is the thickness (e.g., 0.2 mm) of the metal strip (typically copper strip) from which the leadframe 12 is fabricated.
Reducing the (uniform) thickness of the rectangular tie bars facilitates dicing at line T, thereby compromising the stability of die pad 12A.
In the solution as discussed herein, these problems are solved by forming (bussing) channel-shaped (U-shaped) cross-sections on the tie bars 20, for example channel-shaped (U-shaped) cross-sections formed at least at their intermediate portions (e.g. at narrowed waist portions) in planes perpendicular to the top and bottom surfaces of the lead frame, which intermediate portions are intended to be cut during singulation after moulding.
That is, in the solution as discussed herein, the tie bars 20 have hollow portions 20A at intermediate split locations. The tie bars 20 thus have a channel-shaped cross-sectional profile at the intermediate dividing positions.
Fig. 4, which is a view of the portion of fig. 1 indicated by arrow IV reproduced on an enlarged scale with various elements such as the pre-molded resin 12C removed for clarity, shows that the tie bars 20 of the examples presented herein still have an "envelope" thickness equal to the thickness (e.g., 0.2 mm) of the metal tape from which the leadframe 12 is fabricated.
Due to the presence of the cavity 20A, the tie bar 20 of the example presented herein has a hollow channel shape at its intermediate section (U-shape is an example of such a channel shape).
The cavity 20A may be created by an imprinting or etching process, for example, during leadframe fabrication.
Advantageously, the cavity 20A does not extend over the entire length of the tie rod 20 (in the longitudinal direction X20), but only at a middle section of the tie rod 20, for example at the location where cutting is expected to occur during singulation (see plane T in fig. 3).
During the splitting, the tie bars 20 are cut at approximately half their length (at plane T of fig. 3).
In the enlarged view of fig. 4, half of the tie bars 20 that may result from such cutting are shown in solid lines, while the other half are shown in dashed lines; the halves are separated from each other in a segmentation step.
The enlarged view of fig. 4 highlights the overall (longitudinal) hourglass shape of the tie bars 20 shown therein, with the cavity 20A advantageously extending (only) at the waist of the central narrowing of the hourglass-shaped tie bars 20.
The enlarged view of fig. 4 also illustrates the cavity 20A such that its channel shape is open at the back or bottom side of the leadframe 12 (opposite the front or top surface on which the die 14 is mounted).
That is, the tie bars 20 have hollow portions 20A at intermediate dividing positions, in which the channel-shaped cross-sectional profile opens at the (second) surface of the die pad 12A opposite to the (first) surface on which the die 14 is mounted.
Although advantageous, this arrangement is not mandatory, as the cavity 20A may cause the channel shape to open at the front or top side of the leadframe 12 on which the die 14 is mounted.
The enlarged view of fig. 4 also illustrates a channel-shaped tie bar 20 protruding from the body of the lead frame 12 from its recessed portion, i.e., having two channels (notches) 20B on both sides of the tie bar 20, and extending transversely to the plane of the lead frame 12 at the sides of the tie bar 20.
It was found that the hollow (channel-shaped, e.g., U-shaped) tie bars 20 as illustrated in fig. 4 provide higher stiffness (higher moment of inertia) than tie bars of the same cross-sectional area of constant (full) cross-section, thus providing improved support for the die pad to avoid tilting/bending.
FIG. 5 is a graph showing the following characteristics (moment of inertia-. Mu.m 4 Cross-sectional area of tie bar- μm 2 ): a hollow (channel-shaped or U-shaped) tie rod 20 (curve labeled I), a conventional tie rod of constant (complete) cross-section (curve labeled II), as described herein.
The chart of fig. 5 shows that providing a recess or cavity 20A in the intermediate portion of the tie rod 20 results in: has a higher moment of inertia for the same cross-sectional area (cross-sectional area of the intermediate portion cut during the division) and, in unison, has the same moment of inertia for a smaller cross-sectional area (cross-sectional area of the intermediate portion cut during the division).
The smaller cross-sectional area translates to lower cutting forces (and thus lower stresses) involved in singulation, while maintaining sufficient bending stiffness to support the associated die pad 12A from tilting/bending.
The solution described herein contributes to achieve the dual advantages of: higher moment of inertia, and thus higher stiffness and improved support for die pads, resists tilting/bending; and reducing the cross-sectional area, making cutting easier at the time of division while reducing the division stress.
Fig. 6 shows that the channel shape or U-shape of the tie bars 20 will appear through the remainder of the tie bars (which may be a package including a leadframe with exposed pads) exposed at the sides (flank) of the package of the device 10 after singulation.
Two tie bars 20 at both (lateral) sides of the die pad 12A are illustrated in the figure.
The two pairs of tie bars (i.e., four tie bars 20 for each die pad 12A) symmetrically disposed at opposite sides of the die pad are of course merely exemplary and not limiting. Of course, other arrangements are possible, such as one tie bar and two bars asymmetrically arranged at opposite sides of the die pad (i.e., three tie bars 20 for each die pad 12A).
Thus, the tie bars 20 as discussed herein facilitate tie bars having thinner (easier to cut) while avoiding any increased risk of die pad tilting, because the channel-shaped or U-shaped cross-section provides a higher moment of inertia on the tie bars 20 as compared to a rectangular/square cross-sectional shape.
At the same time, the stamped/etched tie bars 20 will reduce the forces/stresses involved in separating the individual packages 10 from the chains/straps during the final step of the assembly process.
One or more embodiments relate to a method.
One or more embodiments also relate to a corresponding substrate (e.g., a leadframe strip or tape for manufacturing semiconductor devices).
One or more embodiments also relate to a corresponding semiconductor device.
The solution proposed herein comprises a substrate, such as a leadframe, in which the tie bars have a channel-shaped (U-shaped) cross section at least at their intermediate portions, which are cut during singulation after molding.
For example, such a channel or (inverted) U-shape may be formed on the tie bars using an imprinting or etching process during leadframe fabrication.
Thus, a higher rigidity (higher moment of inertia) of the tie rod can be achieved as compared to a tie rod having a constant cross section. This provides improved support of the die pad against tilting/bending. At the same time, the channel-shaped or U-shaped tie bar will be more easily cut during singulation.
In the solutions presented herein, embossing or etching grooves in the leadframe tie bars facilitates providing a channel-shaped or U-shaped cross section in the middle portions of these tie bars. After mounting a semiconductor chip or die on a die pad in a leadframe and molding a package thereon, individual package units may be singulated from the leadframe by cutting through channel-shaped (U-shaped) intermediate portions of the tie bars.
Visual inspection of the resulting package sides will reveal the presence of such channel shapes or U-shapes in the remaining tie bars, which remain exposed at the package sides.
An aspect of the present disclosure provides a method comprising: mounting a semiconductor die at a first surface of each of a plurality of die pads in a semiconductor die mounting substrate, each die pad having a second surface opposite the first surface and further having tie bars protruding from the die pads; molding a package onto each semiconductor die mounted at a first surface of each of a plurality of die pads to form a plurality of semiconductor devices coupled via tie bars protruding from the die pads; dicing each tie bar at the intermediate dicing location to divide the plurality of semiconductor devices into individual semiconductor devices; and wherein each tie bar has a hollow portion at the intermediate dividing position, the hollow portion defining a channel-shaped cross-sectional profile at the intermediate dividing position.
In accordance with one or more embodiments, a hollow portion is provided in a surface of each tie bar extending from the second surface of the die pad.
According to one or more embodiments, wherein each tie bar has a length in a longitudinal direction extending away from the die pad, and wherein the hollow portion extends over a portion of the length in the longitudinal direction.
According to one or more embodiments, wherein each tie bar has an hourglass shape in the longitudinal direction, the hourglass shape having a centrally narrowed waist portion, and wherein the hollow portion is provided at the centrally narrowed waist portion.
In accordance with one or more embodiments, wherein each tie bar protrudes from a recessed portion of a die pad, the die pad has a lateral groove located laterally of the tie bar.
In accordance with one or more embodiments, wherein the semiconductor die mounting substrate is a tape substrate comprising a plurality of die pads distributed along a length of the tape substrate, wherein each tie bar protrudes from a die pad in a direction of the length of the tape substrate.
According to one or more embodiments, the method further comprises performing an embossing operation to create the hollow portion at the intermediate split location.
According to one or more embodiments, further comprising performing an etching operation to create the hollow portion at the intermediate split location.
Another aspect of the present disclosure provides a method comprising: providing a leadframe comprising a plurality of die pads, each die pad having a first surface opposite a second first surface, and further having tie bars protruding from the die pads; wherein providing the leadframe includes providing a hollow portion at each tie bar at an intermediate split location between the die pads, the hollow portion defining a channel-shaped cross-sectional profile at the intermediate split location; mounting a semiconductor die to the first surface of each die pad; encapsulating the leadframe and semiconductor die in an encapsulation; and dividing by cutting through the package and the tie bars at the intermediate dividing positions.
According to one or more embodiments, wherein the providing the lead frame further comprises providing each tie bar with an hourglass shape in a longitudinal direction of the tie bar at the intermediate dividing position, the hourglass shape comprising an intermediate narrowed waist portion at the hollow portion.
Without prejudice to the underlying principles, the details and the embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the scope of the protection.
The claims are an integral part of the technical teaching provided herein regarding the embodiments.
The scope of protection is determined by the appended claims.

Claims (10)

1. A semiconductor die mounting substrate comprising:
a plurality of die pads having a first surface, a second surface opposite the first surface and further having tie bars protruding from each die pad;
wherein each tie bar has an intermediate split position; and
wherein each tie bar has a hollow portion at each intermediate split location defining a channel-shaped cross-sectional profile at the intermediate split location.
2. The semiconductor die mounting substrate of claim 1 wherein the hollow portion is disposed in a surface of each tie bar extending from the second surface of the die pad.
3. The semiconductor die mounting substrate of claim 1 wherein each tie bar has a length in a longitudinal direction extending away from the die pad, and wherein the hollow portion extends over a portion of the length in the longitudinal direction.
4. The semiconductor die mounting substrate of claim 3 wherein each tie bar has an hourglass shape in the longitudinal direction, the hourglass shape having a middle narrowed waist portion, and wherein the hollow portion is disposed at the middle narrowed waist portion.
5. The semiconductor die mounting substrate of claim 1 wherein each tie bar protrudes from a recessed portion of the die pad, the die pad having a lateral recess laterally of the tie bar.
6. The semiconductor die mounting substrate of claim 1 wherein the semiconductor die mounting substrate is a tape substrate comprising the plurality of die pads distributed along a length of the tape substrate, wherein each tie bar protrudes from the die pad in a direction of the length of the tape substrate.
7. A semiconductor device, comprising:
a semiconductor die mounting substrate comprising a die pad having a first surface and a second surface opposite the first surface, and further comprising tie bar residues protruding from the die pad toward a distal singulation site;
a semiconductor die mounted at the first surface of the die pad; and
a package molded onto the semiconductor die mounted at the first surface of the die pad;
wherein the tie bar residues each have a hollow portion at the distal split position;
wherein the tie bar residues each have a channel-shaped cross-sectional profile at the distal segmentation location.
8. The semiconductor device of claim 7, wherein the hollow portion is disposed in a surface of each tie bar extending from the second surface of the die pad.
9. The semiconductor device of claim 7, wherein each tie bar has a length in a longitudinal direction extending away from the die pad, and wherein the hollow portion extends over a portion of the length in the longitudinal direction.
10. The semiconductor device of claim 7, wherein each tie bar protrudes from a recessed portion of the die pad, the die pad having a lateral groove laterally of the tie bar.
CN202321996447.XU 2022-07-28 2023-07-27 Semiconductor die mounting substrate and semiconductor device Active CN220652010U (en)

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US18/224,701 US20240038636A1 (en) 2022-07-28 2023-07-21 Method of manufacturing semiconductor devices, corresponding substrate and semiconductor device
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