CN220627010U

CN220627010U - Power supply circuit and server

Info

Publication number: CN220627010U
Application number: CN202322054763.1U
Authority: CN
Inventors: 陆天恒; 樊澳锋; 江川
Original assignee: TP Link Technologies Co Ltd
Current assignee: TP Link Technologies Co Ltd
Priority date: 2023-08-01
Filing date: 2023-08-01
Publication date: 2024-03-19
Anticipated expiration: 2033-08-01

Abstract

The utility model provides a power supply circuit and a server, wherein the power supply circuit comprises: the switching on and shutting down module and the signal holding module; the power on/off module is used for generating a power on signal when the main board to be powered on is started, and transmitting the power on signal to the signal holding module; the signal holding module is used for continuously outputting a power-on signal to the power supply in a preset duration when receiving the starting signal so as to enable the power supply to supply power to the main board to be powered. When the main board to be powered is started, the generated starting signal is transmitted to the signal holding module through the starting and stopping module, and the power-on signal is continuously output to the power supply within a preset duration when the signal holding module receives the starting signal, so that the power supply continuously supplies power to the main board to be powered. Compared with the prior art, the utility model can continuously supply power to the main board to be powered in the data initialization time, ensures the normal starting of the main board to be powered, and prolongs the service life.

Description

Power supply circuit and server

Technical Field

The present utility model relates to the field of power supply technologies for devices, and in particular, to a power supply circuit and a server.

Background

At present, when the existing power supply supplies power to the server, the user generally directly powers on the server through the power supply after pressing a power-on button, but because the server needs a period of data initialization time from powering on to completely starting, if the user presses the power-off button during the period, the power supply suddenly stops supplying power to the server, the data in the server are easily damaged, and the service life of the server is lower.

The foregoing is provided merely for the purpose of facilitating understanding of the technical solutions of the present utility model and is not intended to represent an admission that the foregoing is prior art.

Disclosure of Invention

The utility model mainly aims to provide a power supply circuit and a server, and aims to solve the technical problems that in the prior art, when a power supply suddenly stops supplying power to the server in the data initialization time of the server, the server data is easy to damage and the service life is short.

To achieve the above object, the present utility model proposes a power supply circuit including: the switching on and shutting down module and the signal holding module;

the signal holding module is respectively connected with the on-off module and a power supply, and the power supply is connected with a main board to be powered;

the power-on/off module is used for generating a power-on signal when the main board to be powered is started, and transmitting the power-on signal to the signal holding module;

and the signal holding module is used for continuously outputting a power-on signal to the power supply in a preset duration when the starting-up signal is received, so that the power supply supplies power to the main board to be powered.

Optionally, the power-on module includes: a key unit and a switching unit;

the switching unit is respectively connected with the key unit and the signal holding module;

the key unit is used for receiving key signals input from the outside and transmitting the key signals to the switching unit;

the switching unit is used for converting the key signal into the starting signal and transmitting the starting signal to the signal holding module.

Optionally, the key unit includes: a key and a first resistor;

the input pin of the key is connected with a power supply, the output pin of the key is respectively connected with the first end of the first resistor and the switching unit, and the second end of the first resistor is grounded.

Optionally, the switching unit includes: the first MOS tube and the second resistor;

the grid electrode of the first MOS tube is connected with the output pin of the key, the drain electrode of the first MOS tube is connected with the power supply, the source electrode of the first MOS tube is respectively connected with the signal holding module and the first end of the second resistor, and the second end of the second resistor is grounded.

Optionally, the signal holding module includes: a delay chip and a third resistor;

the power pin of the delay chip is connected with the power supply, the input pin of the delay chip is connected with the source electrode of the first MOS tube, the grounding pin of the delay chip is grounded, the output pin of the delay chip is connected with the first end of the third resistor, and the second end of the third resistor is connected with the power supply.

Optionally, the power supply circuit further includes: a level conversion module;

the level conversion module is respectively connected with the signal holding module and the power supply;

the signal holding module is further used for transmitting the power-on signal to the level conversion module;

the level conversion module is used for carrying out level conversion on the power-on signal and transmitting the converted power-on signal to a power supply so that the power supply supplies power to the main board to be powered.

Optionally, the level conversion module includes: the second MOS tube, the fourth resistor and the fifth resistor;

the drain electrode of the second MOS tube is connected with the power supply, the source electrode of the second MOS tube is connected with the first end of the fourth resistor, the second end of the fourth resistor is grounded, the grid electrode of the second MOS tube is connected with the signal holding module, the grid electrode of the second MOS tube is also connected with the second end of the fifth resistor, and the first end of the fifth resistor is connected with the power supply.

Optionally, the power supply circuit further includes: a power conversion module;

the power supply conversion module is respectively connected with the power supply, the on-off module, the signal holding module and the level conversion module;

the power conversion module is used for converting the voltage provided by the power supply and transmitting the converted voltage to the on-off module, the signal holding module and the level conversion module respectively for power supply.

Optionally, the power conversion module includes: the conversion chip, the first capacitor, the second capacitor and the third capacitor;

the input pin of the conversion chip is connected with the enabling pin of the conversion chip, the input pin of the conversion chip is also connected with the first end of the first capacitor and the power supply, the second end of the first capacitor is grounded, the grounding pin of the conversion chip is grounded, the bypass pin of the conversion chip is connected with the first end of the second capacitor, the second end of the second capacitor is grounded, the output pin of the conversion chip is connected with the first end of the third capacitor, the second end of the third capacitor is grounded, and the output pin of the conversion chip is also connected with the switch module, the signal holding module and the level conversion module respectively.

In addition, in order to achieve the above object, the present utility model also proposes a server comprising a main board to be powered and a power supply circuit as described above.

The utility model provides a power supply circuit and a server, wherein the power supply circuit comprises: the switching on and shutting down module and the signal holding module; the signal holding module is respectively connected with the on-off module and a power supply, and the power supply is connected with a main board to be powered; the power-on/off module is used for generating a power-on signal when the main board to be powered is started, and transmitting the power-on signal to the signal holding module; and the signal holding module is used for continuously outputting a power-on signal to the power supply in a preset duration when the starting-up signal is received, so that the power supply supplies power to the main board to be powered. When the main board to be powered is started, the generated starting signal is transmitted to the signal holding module through the starting and stopping module, and the power-on signal is continuously output to the power supply within a preset duration when the signal holding module receives the starting signal, so that the power supply continuously supplies power to the main board to be powered. Compared with the existing method that the power failure of the main board to be powered is easy to cause data damage in the data initialization time, the method and the device can continuously power the main board to be powered in the data initialization time, ensure the normal starting of the main board to be powered, and prolong the service life.

Drawings

In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present utility model, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a first embodiment of a power supply circuit according to an embodiment of the present utility model;

fig. 2 is a schematic circuit diagram of a power on/off module in a first embodiment of a power supply circuit according to an embodiment of the present utility model;

fig. 3 is a schematic circuit diagram of a signal holding module in a first embodiment of a power supply circuit according to an embodiment of the present utility model;

fig. 4 is a schematic structural diagram of a second embodiment of a power supply circuit according to an embodiment of the present utility model;

fig. 5 is a schematic circuit diagram of a level shift module in a second embodiment of a power supply circuit according to an embodiment of the present utility model;

fig. 6 is a schematic circuit diagram of a power conversion module in a second embodiment of a power supply circuit according to an embodiment of the present utility model.

Reference numerals illustrate:

the achievement of the objects, functional features and advantages of the present utility model will be further described with reference to the accompanying drawings, in conjunction with the embodiments.

Detailed Description

It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the utility model.

The following description of the embodiments of the present utility model will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present utility model are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.

Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present utility model.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a first embodiment of a power supply circuit according to an embodiment of the present utility model.

Based on fig. 1, a first embodiment of the power supply circuit of the present utility model is presented.

In this embodiment, the power supply circuit includes: a power on/off module 1 and a signal holding module 2;

the signal holding module 2 is respectively connected with the on-off module 1 and the power supply 3, and the power supply 3 is connected with the main board 4 to be powered.

It should be noted that, the power supply circuit provided in this embodiment may be applied in a scenario of supplying power to a server, or may be applied in a scenario of supplying power to other servers, which is not limited in this embodiment.

It can be understood that the power supply 3 may be a power supply required for the server to operate, and the embodiment may use an advanced technology extension (Advanced Technology eXtended Power Supply, ATX) power supply or a common redundancy (Common Redundant Power Supply, CRPS) power supply, and of course may also be other power supplies, where the main board 4 to be powered may be a main board in the server to be powered, and in this embodiment, the power supply 3 may output 12V voltage through a 12V power supply port to supply power to the main board 4 to be powered (12V power supply in fig. 1), and of course may also be other voltage values, which is not limited in this embodiment.

It should be understood that, the power on/off module 1 is configured to generate a power on signal when the main board 4 to be powered is started, and transmit the power on signal to the signal holding module 2; the signal holding module 2 is configured to continuously output a power-on signal to the power supply 3 within a preset duration when the power-on signal is received, so that the power supply 3 supplies power to the motherboard 4 to be powered.

It should be noted that, when the user needs to start the main board 4 to be powered, the power on/off module 1 may generate a power on signal, and the starting mode may be that the user presses a power on button, in this embodiment, the power on/off module 1 may be provided with the power on button, and the user starts the main board 4 to be powered by pressing the power on button, which may be other starting modes, however, the present embodiment is not limited thereto.

It can be understood that, as shown in fig. 1, the signal holding module 2 may be connected to a PSON pin of the power supply 3 (PSON in fig. 1), so that when the signal holding module 2 receives a power-on signal, a power-on signal may be continuously generated and output to the power supply 3, so that the power supply 3 continuously provides 12V power for the main board 4 to be powered, and thus the main board 4 to be powered continuously receives a power supply completion start in a data initialization time. The preset time period can be set according to practical situations, and the embodiment can set the preset time period to 5 minutes for explanation, but is not limited thereto.

It should be emphasized that, during the preset period, the signal holding module 2 may continuously output the power-on signal, if the user presses the power-off button to close the main board 4 to be powered, the signal holding module 2 may further keep outputting the power-on signal, so that the power supply 3 does not stop supplying power to the main board 4 to be powered, thereby implementing protection for data initialization of the main board 4 to be powered.

It should be understood that the signal holding module 2 can continuously output the power-on signal through a delay relay, and of course, the signal holding module can also be in a single chip microcomputer mode, which is not limited in this embodiment.

In a specific implementation, when the user presses the power-on button, it indicates that the user wants to start the main board 4 to be powered on at this time, the power-on/off module 1 may generate a power-on signal and transmit the power-on signal to the signal holding module 2, and when the signal holding module 2 receives the power-on signal, the power-on signal may be continuously output to the power supply 3 within 5 minutes, so that the power supply 3 may continuously supply power to the main board 4 to be powered on within 5 minutes, during which, even if the user presses the power-off button, the signal holding module 2 may continuously output the power-on signal, after 5 minutes, the signal holding module 2 may stop outputting the power-on signal, and if the user presses the power-off button at this time, the signal holding module 2 may output the power-off signal to the power supply 3, so that the power supply 3 stops supplying power to the main board 4 to be powered on, thereby implementing protection of the main board 4 to be powered on.

Further, in order for the on-off module 1 to generate the on-off signal, as further shown in fig. 1, in this embodiment, the on-off module includes: a key unit 11 and a switching unit 12;

wherein the switching unit 12 is connected with the key unit 11 and the signal holding module 2 respectively;

the key unit 11 is configured to receive a key signal input from the outside, and transmit the key signal to the switching unit 12;

the switching unit 12 is configured to convert the key signal into the power-on signal, and transmit the power-on signal to the signal holding module 2.

Note that, the key unit 11 may be a unit formed by keys, but in order to realize that the key unit 11 can be turned on or turned off, in this embodiment, the user can realize that the key unit is turned on by pressing a short time and turned off by pressing a long time, and the specific time is 8 seconds according to this embodiment, but other times and other ways of realizing the power on or off are also possible, which is not limited in this embodiment.

It can be understood that the user can press the key to make the key unit 11 receive the key signal and transmit the key signal to the switching unit 12, and the switching unit 12 converts the key signal into a power-on signal and transmits the power-on signal to the signal holding module 2.

Further, referring to fig. 2, fig. 2 is a schematic circuit diagram of a power on/off module in a first embodiment of a power supply circuit according to an embodiment of the present utility model.

As shown in fig. 2, the key unit 11 includes: a key SW1 and a first resistor R1;

the input pin of the key SW1 is connected to a power supply, the output pin of the key SW1 is connected to the first end of the first resistor R1 and the switching unit 12, and the second end of the first resistor R1 is grounded.

It should be noted that, the input pins of the key SW1 may be the first pin of the key SW1 and the second pin of the key SW1, and the first pin of the key SW1 is connected to the second pin of the key SW1 and then connected to a 5V power supply (pwr_5vsb in fig. 2), where the 5V power supply may be provided by the power supply 3, or may be provided by other power supplies, which is not limited in this embodiment.

It can be understood that the output pins of the key SW1 may be the third pin of the key SW1 and the fourth pin of the key SW1, and the third pin of the key SW1 is connected to the fourth pin of the key SW1 and then connected to the switching unit 12.

It should be understood that, in this embodiment, the output pin of the key SW1 is further connected to the first resistor R1 and then grounded, so that the output pin of the key SW1 is pulled down, thereby preventing the generation of an invalid level and improving the reliability and stability of the circuit.

In a specific implementation, when the key SW1 is pressed for a short time, the key SW1 may switch on the switching unit 12 and the 5V power to generate a key signal, the output pin of the key SW1 transmits the generated key signal to the switching unit 12, and when the key SW1 is pressed for a long time, the key SW1 may continuously switch on the switching unit 12 and the 5V power, and the output pin of the key SW1 may continuously transmit the generated key signal to the switching unit 12.

Further, the switching unit 12 includes: the first MOS transistor MOS1 and the second resistor R2;

the grid electrode of the first MOS tube MOS1 is connected with the output pin of the key SW1, the drain electrode of the first MOS tube MOS1 is connected with the power supply, the source electrode of the first MOS tube MOS1 is respectively connected with the signal holding module 2 and the first end of the second resistor R2, and the second end of the second resistor R2 is grounded.

It should be noted that, the first MOS transistor MOS1 may be an N-channel MOS transistor, and the drain of the first MOS transistor MOS1 may be connected to a 3.3V power supply (pwr—3v3sb), where the 3.3V power supply may be provided by the power supply 3, or may be provided by other power supplies, which is not limited in this embodiment.

It can be understood that the source of the first MOS transistor MOS1 may be connected to the signal holding module 2 (SW in fig. 2), and the generated power-on signal may be transmitted to the signal holding module 2 through the source of the first MOS transistor MOS 1.

In a specific implementation, after a gate of the first MOS transistor MOS1 receives a short-pressed key signal, a source and a drain of the first MOS transistor MOS1 are turned on, and the source of the first MOS transistor MOS1 can transmit a generated start-up signal to the signal holding module 2 through a 3.3V power supply; after the gate of the first MOS transistor MOS1 receives the long-pressed key signal, the source of the first MOS transistor MOS1 may continuously transmit the generated shutdown signal to the signal holding module 2 until the key SW1 is no longer pressed.

Further, referring to fig. 3, fig. 3 is a schematic circuit diagram of a signal holding module in a first embodiment of a power supply circuit according to an embodiment of the present utility model.

As shown in fig. 3, in the present embodiment, the signal holding module 2 includes: a delay chip U1 and a third resistor R3;

the power pin of the delay chip U1 is connected with the power supply, the input pin of the delay chip U1 is connected with the source electrode of the first MOS tube MOS1, the grounding pin of the delay chip U1 is grounded, the output pin of the delay chip U1 is connected with the first end of the third resistor R3, and the second end of the third resistor R3 is connected with the power supply 3.

It should be understood that the delay chip U1 may be a micro controller unit (Microcontroller Unit, MCU), the specific model may be CMS8S5880, the power pin of the delay chip U1 may be a ninth pin of the delay chip U1, may be connected to a 3.3V power supply (pwr_3v3sb in fig. 3), the input pin of the delay chip U1 may be a second pin of the delay chip U1, may be connected to the source of the first MOS transistor MOS1 (SW in fig. 3) to receive the power-on signal, the ground pin of the delay chip U1 may be a seventh pin of the delay chip U1, the output pin of the delay chip U1 may be a nineteenth pin of the delay chip U1, the second end of the third resistor R3 may be connected to the power supply 3 (en_sys# in fig. 3), and the generated power-up signal may be transmitted to the power supply 3.

It should be further noted that, the input pin of the delay chip U1 may further receive a shutdown signal output by the source of the first MOS transistor MOS1, and transmit the generated down signal to the power supply 3 through the third resistor R3, so that the power supply 3 stops supplying power to the motherboard 4 to be powered.

It should be emphasized that, because the power-on signal and the power-off signal received by the input pin of the delay chip U1 are both high levels, the embodiment can write a program into the delay chip U1, that is, the power-on signal can be the high level when the short time is identified, the output pin of the delay chip U1 continuously outputs the power-on signal for 5 minutes to the power supply 3, the power-off signal can be the high level when the long time is identified, and the output pin of the delay chip U1 can output the power-off signal to the power supply 3.

It is understood that the third pin of the delay chip U1 may be a control pin of the delay chip U1, may be connected to the second end of the sixth resistor R6 and the first end of the seventh resistor R7 (pwr_ctrl in fig. 3), the first end of the sixth resistor R6 may be connected to a 3.3V power supply (pwr_3v3sb in fig. 3), the second end of the seventh resistor R7 may be grounded, the fourth pin of the delay chip U1 may be a reset pin of the delay chip U1, may be connected to the second end of the eighth resistor R8 and the first end of the fourth capacitor C4 (RST in fig. 3), the first end of the eighth resistor R8 may be connected to a 3.3V power supply (pwr_3v3sb in fig. 3), and the second end of the fourth capacitor C4 may be grounded.

It should be understood that, if the power-up signal and the power-down signal output by the delay chip U1 are both at high level, in order to make the power supply 3 identify whether power supply needs to be started or stopped, the power supply 3 may record the number of times of receiving the high level, that is, when the power-up signal at the high level is received for the first time, it may indicate that power supply is started, and when the power-down signal at the high level is received again, it may indicate that power supply is ended; if the power-up signal and the power-down signal output by the delay chip U1 are both low, the number of times of receiving the low level can be recorded in the power-up power supply 3, that is, when the power-up signal of the low level is received for the first time, the power-up signal can be started, and when the power-down signal of the low level is received again, the power-down signal can be stopped, and if the power-up signal and the power-down signal output by the delay chip U1 are both low, the power-up signal and the power-down signal can be started, and if the power-up signal and the power-down signal are both low, the power-up signal and the power-down signal are both required to be started, and the above example is only convenient to understand, and can be other implementation modes, and the embodiment is not limited.

In a specific implementation, when the input pin of the delay chip U1 receives a short-pressed power-on signal, the output pin of the delay chip U1 may continuously output a power-on signal to the power supply 3, and when the input pin of the delay chip U1 receives a long-pressed power-off signal, the output pin of the delay chip U1 may output a power-off signal to the power supply 3.

In this embodiment, when the server needs to be started, the user presses the key SW1 for a short time, so that the key unit receives the key signal, and converts the key signal into the startup signal through the switching unit 12, and then transmits the startup signal to the signal holding module 2, the signal holding module 2 can continuously output the power-on signal to the POSN pin of the power supply 3 within 5 minutes after receiving the short-pressed startup signal, and further, even if the key SW1 is pressed again within 5 minutes, the signal holding module 2 continuously outputs the power-on signal until the end of 5 minutes, if the key SW1 is pressed again for a long time, the key unit 11 can continuously output the key signal to the switching unit 12, and can be converted into the shutdown signal through the switching unit 12 and then continuously transmit the shutdown signal to the signal holding module 2, and the signal holding module 2 can be shut down after receiving the long-pressed shutdown signal, thereby protecting the normal startup of the server and prolonging the service life.

Referring to fig. 4, fig. 4 is a schematic structural diagram of a second embodiment of a power supply circuit according to an embodiment of the present utility model.

Considering that if the power up signal and the power down signal output by the delay chip U1 are both at high level, but the power supply 3 is valid when receiving low level, that is, the PSON pin of the power supply 3 may be at high level of 5V when not receiving low level, and may be at low level of 0V when receiving low level, in order to enable the power supply to start and stop supplying power, as shown in fig. 4, in this embodiment, the power supply circuit further includes: a level conversion module 5;

wherein the level conversion module 5 is respectively connected with the signal holding module 2 and the power supply 3;

the signal holding module 2 is further configured to transmit the power-on signal to the level conversion module 5;

the level conversion module 5 is configured to level-convert the power-up signal, and transmit the converted power-up signal to the power supply 3, so that the power supply 3 supplies power to the motherboard 4 to be powered.

When the level conversion module 5 receives the high-level power-on signal, the high-level power-on signal may be converted into the low-level power-on signal, and the converted power-on signal may be transmitted to the power supply 3; when the level conversion module 5 receives the high-level down signal, the high-level down signal can be converted into the low-level down signal, and the converted up signal is transmitted to the power supply 3, so that the power supply 3 can receive the low level when the delay chip U1 outputs the high-level down signal.

Further, referring to fig. 5, fig. 5 is a schematic circuit diagram of a level shift module in a second embodiment of a power supply circuit according to an embodiment of the present utility model;

as shown in fig. 5, the level shift module 5 includes: the second MOS transistor MOS2, the fourth resistor R4 and the fifth resistor R5;

the drain electrode of the second MOS transistor MOS2 is connected to the power supply 3, the source electrode of the second MOS transistor MOS2 is connected to the first end of the fourth resistor R4, the second end of the fourth resistor R4 is grounded, the gate electrode of the second MOS transistor MOS2 is connected to the signal holding module 2, the gate electrode of the second MOS transistor MOS2 is further connected to the second end of the fifth resistor R5, and the first end of the fifth resistor R5 is connected to the power supply.

It can be understood that the drain electrode of the second MOS transistor MOS2 may be connected to the PSON pin of the power supply 3 (pson# in fig. 5), the gate electrode of the second MOS transistor MOS2 may be connected to the second end of the third resistor R3 in the signal holding module 2 (en_sys# in fig. 5), when the gate electrode of the second MOS transistor MOS2 receives the high-level power-up signal, the source electrode and the drain electrode of the second MOS transistor MOS2 are turned on, the drain electrode of the second MOS transistor MOS2 may output the low-level power-up signal to the power supply 3, and when the gate electrode of the second MOS transistor MOS2 receives the high-level power-down signal, the drain electrode of the second MOS transistor MOS2 may output the low-level power-down signal to the power supply 3.

It should be emphasized that, because the level of the power-on signal is converted in this embodiment, and then when the delay chip U1 fails, the output pin of the delay chip U1 may be in a low level state due to the failure, and then the power supply 3 may misidentify that the power supply needs to be stopped at this time to damage the main board 4 to be powered, and through the level conversion module 5, when the gate of the second MOS transistor MOS2 receives the low level, the source and the drain of the second MOS transistor MOS2 may still be disconnected, the drain of the second MOS transistor MOS2 is not transmitted to the power supply 3 in a low level, the PSON pin of the power supply 3 is still in a 5V high level state, the power supply 3 still maintains a power supply state, and then when the delay chip U1 fails, the power supply 3 may not cut off the power supply of the main board 4 to be powered due to the damage of the delay chip U1, and further protect the main board 4 to be powered.

Further, with continued reference to fig. 4, in order to achieve power supply to the power on/off module 1, the signal holding module 2, and the level conversion module 5, in this embodiment, the power supply circuit further includes: a power conversion module 6. The power conversion module 6 is respectively connected with the power supply 3, the power on/off module 1, the signal holding module 2 and the level conversion module 5, and the power conversion module 6 is configured to convert a voltage provided by the power supply 3 and transmit the converted voltage to the power on/off module 1, the signal holding module 2 and the level conversion module 5 for power supply.

It should be noted that, the power conversion module 6 may be connected to a 5V power supply port of the power supply 3, so as to receive the 5V voltage provided by the power supply 3, convert the 5V voltage into 3.3V voltage, and transmit the 3.3V voltage to the switching unit 12, the signal holding module 2, and the level conversion module 5 in the switching module 1; meanwhile, since the voltage required by the key unit 11 is 5V, the key unit 11 can be directly connected with the 5V power supply port of the power supply 3 to be powered.

Further, referring to fig. 6, fig. 6 is a schematic circuit diagram of a power conversion module in a second embodiment of a power supply circuit according to an embodiment of the present utility model; as shown in fig. 6, in the present embodiment, the power conversion module 6 includes: the conversion chip U2, the first capacitor C1, the second capacitor C2 and the third capacitor C3;

the input pin of the conversion chip U2 is connected with the enable pin of the conversion chip U2, the input pin of the conversion chip U2 is further connected with the first end of the first capacitor C1 and the power supply 3, the second end of the first capacitor C1 is grounded, the grounding pin of the conversion chip U2 is grounded, the bypass pin of the conversion chip U2 is connected with the first end of the second capacitor C2, the second end of the second capacitor C2 is grounded, the output pin of the conversion chip U2 is connected with the first end of the third capacitor C3, the second end of the third capacitor C3 is grounded, and the output pin of the conversion chip U2 is further connected with the switch module 1, the signal holding module 2 and the level conversion module 5.

It is understood that the model of the conversion chip U2 may be ldo_tmi6030-33, but may be other models, which is not limited in this embodiment.

It should be understood that the input pin of the conversion chip U2 may be the first pin of the conversion chip U2, the enable pin of the conversion chip U2 may be the third pin of the conversion chip U2, the first pin and the third pin of the conversion chip U2 may be connected to the 5V power supply port of the power supply 3 (pwr_5vsb in fig. 6) to receive the 5V voltage, the ground pin of the conversion chip U2 is the second pin, the bypass pin of the conversion chip U2 is the fourth pin of the conversion chip U2, the output pin of the conversion chip U2 is the fifth pin of the conversion chip U2, and the fifth pin of the conversion chip U2 may be connected to the drain electrode of the first MOS transistor MOS1 in the switching unit 12, the power pin of the delay chip U1 in the signal holding module 2, the first end of the fifth resistor R5 in the level conversion module 5, the first end of the sixth resistor R6, and the first end of the eighth resistor R8 (pwr_3v3 SB in fig. 6).

In a specific implementation, the power conversion module 6 can convert the 5V voltage provided by the power supply 3 into the voltage required by the operation of the switching unit 12, the signal holding module 2 and the level conversion module 5, so that the power supply does not need to be reset, and the cost is saved.

According to the embodiment, the level conversion can be realized through the level conversion module 5, and the protection of the main board 4 to be powered is realized when the delay chip U1 fails through the level conversion module 5, so that the service life is further prolonged; meanwhile, the 5V voltage provided by the power supply 3 is directly converted into the required voltage through the power supply conversion module 6, so that the cost is saved.

To achieve the above object, the present utility model also proposes a server comprising a motherboard 4 to be powered and a power supply circuit as described above. The specific structure of the main board 4 to be powered and the power supply circuit refers to the above embodiments, and since the server adopts all the technical solutions of all the embodiments, at least has all the beneficial effects brought by the technical solutions of the embodiments, and will not be described in detail herein.

The foregoing description is only of the preferred embodiments of the present utility model, and is not intended to limit the scope of the utility model, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.

Claims

1. A power supply circuit, the power supply circuit comprising: the switching on and shutting down module and the signal holding module;

the power on/off module is used for generating a power on signal when the main board to be powered on is started, and transmitting the power on signal to the signal holding module, wherein the power on signal is a signal for starting the main board to be powered on;

the signal holding module is used for continuously outputting a power-on signal to the power supply in a preset duration when the starting-up signal is received, so that the power supply supplies power to the main board to be powered;

the signal holding module includes: a delay chip;

the input pin of the delay chip is connected with the on-off module, and the output pin of the delay chip is connected with the power supply;

the input pin of the delay chip is used for receiving the starting signal, and the output pin of the delay chip is used for transmitting the generated power-on signal to the power supply.

2. The power supply circuit of claim 1, wherein the power-on module comprises: a key unit and a switching unit;

3. The power supply circuit according to claim 2, wherein the key unit includes: a key and a first resistor;

4. A power supply circuit as claimed in claim 3, characterized in that the switching unit comprises: the first MOS tube and the second resistor;

5. The power supply circuit of claim 4, wherein the signal holding module further comprises: a third resistor;

6. The power supply circuit of claim 1, wherein the power supply circuit further comprises: a level conversion module;

7. The power supply circuit of claim 6, wherein the level shifting module comprises: the second MOS tube, the fourth resistor and the fifth resistor;

8. The power supply circuit of claim 6, wherein the power supply circuit further comprises: a power conversion module;

9. The power supply circuit of claim 8, wherein the power conversion module comprises: the conversion chip, the first capacitor, the second capacitor and the third capacitor;

10. A server, characterized in that it comprises a motherboard to be powered and a power supply circuit according to any of claims 1 to 9.