CN220553441U - Packaging structure of power chip - Google Patents
Packaging structure of power chip Download PDFInfo
- Publication number
- CN220553441U CN220553441U CN202322193779.0U CN202322193779U CN220553441U CN 220553441 U CN220553441 U CN 220553441U CN 202322193779 U CN202322193779 U CN 202322193779U CN 220553441 U CN220553441 U CN 220553441U
- Authority
- CN
- China
- Prior art keywords
- copper
- metal layer
- power chip
- ubm
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 8
- 229910052802 copper Inorganic materials 0.000 claims abstract description 58
- 239000010949 copper Substances 0.000 claims abstract description 58
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 51
- 229910052751 metal Inorganic materials 0.000 claims abstract description 31
- 239000002184 metal Substances 0.000 claims abstract description 31
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 16
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052709 silver Inorganic materials 0.000 claims description 10
- 239000004332 silver Substances 0.000 claims description 9
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 8
- 239000010931 gold Substances 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 230000002265 prevention Effects 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 9
- 238000003466 welding Methods 0.000 abstract description 5
- 239000000463 material Substances 0.000 abstract description 2
- 238000007789 sealing Methods 0.000 abstract description 2
- 230000002349 favourable effect Effects 0.000 abstract 1
- 238000005245 sintering Methods 0.000 description 6
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910001080 W alloy Inorganic materials 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000001351 cycling effect Effects 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- -1 silver ions Chemical class 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical group [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
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- Wire Bonding (AREA)
Abstract
The utility model discloses a packaging structure of a power chip, which comprises the power chip, wherein a top metal layer is arranged on a wafer of the power chip, a UBM metal layer is deposited on the top metal layer, a copper column is arranged on the UBM metal layer, and a copper bonding wire or a copper clamp is bonded on the top surface of the copper column. According to the utility model, the UBM metal layer is arranged on the top metal layer, the copper column is arranged on the UBM layer, and the copper bonding wires are bound on the copper column, so that the problems in the prior art can be solved, the damage to the power chip is reduced, the binding yield is improved, the copper column is favorable for reducing the dynamic thermal impedance of the package, the current sharing performance is better, the heat conduction is faster, and the temperature difference of a single chip is smaller; the problem of fatigue of the welding points of the aluminum welding lines in the prior art is avoided, and the reliability and consistency are greatly improved; compared with the scheme of binding copper bonding wires on the DTS in the prior art, electromigration of copper columns cannot occur, and reliability and consistency are greatly improved; the sealing process of the utility model greatly reduces the difficulty and the cost in the aspects of equipment, process, materials and the like.
Description
Technical Field
The utility model relates to the technical field of power modules, in particular to a packaging structure of a power chip.
Background
In the current power module or power device package structure, as shown in fig. 2, most of the package structure is bonded by aluminum wires/aluminum strips or copper wires or soldered by copper clips. Because Al pad is softer, binding a blister copper wire is easy to damage a chip, so that the Al pad is bound with an aluminum wire or an aluminum belt or an aluminum-clad copper wire, and because the resistivity of aluminum is larger, the current carrying capacity of the aluminum binding wire is not better than that of the copper binding wire, and the application of the aluminum binding wire in high current density is limited. In addition, the bonding of aluminum bond wires to Al pads is prone to solder joint fatigue at power cycling (seconds), resulting in reliability problems.
In response to the problems associated with the structure of FIG. 2, some manufacturers (e.g., heraeus et al) have proposed hot press sintering DTS (a copper foil and sintered silver structure) on power chips, as shown in FIG. 3, followed by roughening copper wires (5-20 mils). But face the following technical problems: 1. the hot-pressed sintering DTS process is immature, and DTS is easy to fall off or deviate during sintering, so that the yield is reduced; 2. the Pad with smaller size such as Gate and the like can not sinter DTS and bind copper wires, and is still bound by aluminum wires, so that the reliability problem exists; 3. the DTS size is generally smaller than the Al pad size, and sintered silver at the edge of the DTS after sintering is not compact enough, so that the effective area of a bonding wire is reduced, the number or the wire diameter of the bonding wire is reduced, and the current carrying capacity is reduced; 4. the sintered silver is subjected to high-temperature high-humidity high-current density for a long time, and electromigration of silver ions between top metal layers can occur, so that leakage or short circuit failure can be caused; 5. the high thermal compression sintering equipment and DTS result in higher packaging costs.
Disclosure of Invention
The utility model aims to: the utility model aims to provide a packaging structure of a power chip so as to solve the problems in the prior art.
The technical scheme is as follows: the utility model discloses a packaging structure of a power chip, which comprises the power chip, wherein a top metal layer is arranged on a wafer of the power chip, a UBM metal layer is deposited on the top metal layer, a copper column is arranged on the UBM metal layer, and a copper bonding wire or a copper clamp is bonded on the top surface of the copper column.
Wherein the top metal layer is one of aluminum, copper, silver and gold, or one of alloys of aluminum, copper, silver and gold.
Wherein the thickness of the copper column is 5-300 microns.
Wherein the diameter of the copper bonding wire is 50-500 micrometers.
The beneficial effects are that: compared with the prior art, the utility model has the following beneficial effects:
1. by arranging the UBM metal layer on the top metal layer and arranging the copper column on the UBM layer, and binding copper bonding wires on the copper column, the problems in the prior art can be solved, the damage to the power chip is reduced, and the binding yield is improved;
2. the copper column is beneficial to reducing the dynamic thermal impedance of the package, has better flow equalization property, faster heat conduction and smaller temperature difference of a single chip;
3. the problem of fatigue of the welding points of the aluminum welding lines in the prior art is avoided, and the reliability and consistency are greatly improved;
4. compared with the scheme of binding copper bonding wires on the DTS in the prior art, electromigration of copper columns cannot occur, and reliability and consistency are greatly improved;
5. compared with the scheme of binding copper wires on DTS in the prior art, the sealing process disclosed by the utility model has the advantages that the difficulty is greatly reduced, and the cost is also greatly reduced in the aspects of equipment, process, materials and the like.
Drawings
FIG. 1 is a schematic diagram of the structure of the present utility model;
FIG. 2 is a schematic diagram of a conventional power module package;
fig. 3 is a schematic structural diagram of a conventional power module package.
Detailed Description
The technical scheme of the utility model is further described below with reference to specific embodiments.
Term interpretation: UBM metal layer: an under bump metal layer is deposited.
Example 1
As shown in fig. 1, the package structure of a power chip of the present utility model includes a power chip 1, a top metal layer 2 is disposed on a wafer of the power chip 1, a UBM metal layer 3 is deposited on the top metal layer 2, a copper pillar 4 is disposed on the UBM metal layer 3, a copper wire 5 is bonded to a top surface of the copper pillar 4, and a diameter of the copper wire 5 is 50-500 micrometers. The top metal layer 2 may be a metal or alloy of aluminum, copper, silver, gold, etc., and the copper pillars 4 have a thickness of 5-300 microns.
The top surface of the copper column 4 can be bonded with a copper clamp to replace the copper bonding wire 5.
Example 2
The top metal layer 2 may be sputter formed on the wafer; the UBM metal layer is a titanium tungsten alloy or copper metal layer formed by sputtering, the thickness is not more than 1 micrometer, and the UBM metal layer has the functions of: as a seed layer for electroplating copper pillars 4. Subsequent unwanted UBM regions may be etched away; the copper pillars 4 are usually electroplated with copper, and the electroplated copper structure can be used as a powerful support for bonding copper bonding wires to prevent the bonding process from damaging the chip. The cost of forming the copper column 4 by electroplating is low, the process is mature, and the modes of chemical plating, sputtering and the like can also be adopted, but the method does not comprise a DTS (Die top system) hot-pressing sintering mode; the copper bonding wires 5 with the diameter of 50-500 microns can bear large current, the process is mature, the reliability is good, and the modes of carrying out laser copper welding clips (clips) on the copper columns 4 and the like are not excluded to replace the copper bonding wires; in addition, the upper surface of the copper column 4 can be plated with an oxidation-resistant layer such as Ag, ni/Au or Ni/Pd/Au, so as to prevent the surface oxidation of the copper column 4 from affecting the bonding quality.
The foregoing is only a preferred embodiment of the present utility model, but the scope of the present utility model is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the technical scope of the present utility model should be included in the scope of the present utility model.
Claims (5)
1. The utility model provides a packaging structure of power chip, includes power chip, its characterized in that: and a top metal layer is arranged on the wafer of the power chip, a UBM metal layer is deposited on the top metal layer, a copper column is arranged on the UBM metal layer, and a copper bonding wire or a copper clamp is bonded on the top surface of the copper column.
2. The package structure of a power chip according to claim 1, wherein: and an oxidation prevention layer is arranged on the upper surface of the copper column.
3. The package structure of a power chip according to claim 1, wherein: the top metal layer is one of aluminum, copper, silver and gold or one of alloys of aluminum, copper, silver and gold.
4. The package structure of a power chip according to claim 1, wherein: the thickness of the copper column is 5-300 microns.
5. The package structure of a power chip according to claim 1, wherein: the diameter of the copper bonding wire is 50-500 microns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322193779.0U CN220553441U (en) | 2023-08-15 | 2023-08-15 | Packaging structure of power chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322193779.0U CN220553441U (en) | 2023-08-15 | 2023-08-15 | Packaging structure of power chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220553441U true CN220553441U (en) | 2024-03-01 |
Family
ID=90009502
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202322193779.0U Active CN220553441U (en) | 2023-08-15 | 2023-08-15 | Packaging structure of power chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220553441U (en) |
-
2023
- 2023-08-15 CN CN202322193779.0U patent/CN220553441U/en active Active
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| GR01 | Patent grant |