EP0470210A1 - Low inductance encapsulated package including a semiconductor chip - Google Patents

Low inductance encapsulated package including a semiconductor chip

Info

Publication number
EP0470210A1
EP0470210A1 EP90917818A EP90917818A EP0470210A1 EP 0470210 A1 EP0470210 A1 EP 0470210A1 EP 90917818 A EP90917818 A EP 90917818A EP 90917818 A EP90917818 A EP 90917818A EP 0470210 A1 EP0470210 A1 EP 0470210A1
Authority
EP
European Patent Office
Prior art keywords
lead
chip
contact pad
bonding
conductive bumps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP90917818A
Other languages
German (de)
French (fr)
Inventor
Constantine Alois Neugebauer
Robert Joseph Satriano
James Francis Burgess
Donald Leland Watrous
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Publication of EP0470210A1 publication Critical patent/EP0470210A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05171—Chromium [Cr] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0616—Random array, i.e. array with no symmetry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Definitions

  • the present invention relates to the field of packages for semiconductor devices and packaged devices, and more particularly, to the field of non-hermetic packages and non-hermetically packaged devices.
  • the back side of the chip containing the power device is soldered to a package base which comprises one of the terminals of the final packaged device.
  • a package base which comprises one of the terminals of the final packaged device.
  • an insulating layer is disposed between the package base and the back of the chip.
  • the contact pads on the top or front surface of the chip are then connected by wire bonds to a lead frame which is held in proper relation to the package base and chip.
  • the chip, the wire bonds and a portion of the top side leads or terminals are encapsulated in an insulating material such as epoxy or other materials.
  • wire bonding the upper surface lead frame to the contact pads of the device is because wire bonding machinery can easily compensate for any misalignment in the bonding of the chip to the package base.
  • Such packages have the disadvantage that the wire bonds require a significant space above the chip pads to be encapsulated in the epoxy material to protect those wire bond leads.
  • the wire bonds are normally made with round wire on the order of about 1 mil (0.025 mm) in diameter for low power integrated circuits or low power leads and about 30-40 mils (0.76-1.02 mm) in diameter for power or high current devices and about 0.3-0.5 inch (0.76-1.27 cm) long.
  • a primary object of the present invention is to provide a non-hermetic package which has very low inductance.
  • Another object of the present invention is to provide a non-hermetic package which is free of wire bonds and of problems associated with die attach inaccuracy.
  • a semiconductor device package in which relatively wide leads are bonded directly to the contact pads on the upper surface of the device. This may preferably be done prior to bonding the chip to the package base since chip alignment with the package base is less crucial than top electrode alignment with the contact pads.
  • the leads are solderless bonded to the contact pads using thermocompression bonding.
  • Figures 1-7 illustrate successive steps in the process of packaging a semiconductor device in accordance with the present invention.
  • Figure 1 illustrates a semiconductor chip having contact pads on the upper surface thereof;
  • Figure 2 illustrates the chip of Figure 1 with conductive bumps bonded to the contact pads
  • Figure 3 illustrates a top side lead frame for use in connection with the chip of Figure 2;
  • Figure 4 illustrates a back side or package base lead frame for use with the chip of Figure 2;
  • Figure 5 illustrates the chip of Figure 2 bonded to both the top side and back side lead frames
  • Figure 6 illustrates the structure of Figure 5 after encapsulation of the device in an insulating material
  • Figure 7 illustrates the completed encapsulated device after it has been excised from the lead frames; and Figure 8 is a cross-section through the completed device of Figure 7 taken along the line 8-8.
  • FIG. 7 perspective view
  • FIG. 8 perspective cross-section view
  • a power semiconductor device is shown generally at 10.
  • This device comprises a semiconductor body 12 having uniform metallization 14 disposed in ohmic contact with its lower surface.
  • Two different contact pads 16 and 18 are disposed on the upper surface of the device or chip. These contact pads are spaced apart by a gap 17 between them.
  • the power semiconductor device is a field effect transistor
  • the metallization 14 is normally the drain contact
  • the contact pad 16 is normally the source contact
  • the contact pad 18 is the gate contact.
  • the semiconductor device is an MCT
  • the metallization 14 and the contact pad 16 are the main current electrodes and the contact pad 18 is the gate contact.
  • Contact pads 16 and 18 are typically aluminum in such devices and thus not directly solderable with common solders. It is common practice to provide a solderable metal as the exposed surface of the back side metallization 14 in order that the device may be soldered to a package base or heat sink. If desired, it is also possible to form a solderable metallization as a surface layer on the aluminum contact pads on the upper surface of the device. However, to do so requires additional process steps with the attendant time and yield considerations. In accordance with the present invention, the contact pads 16 and 18 may be either solderable or non-solderable.
  • each of the conductive bumps 30 is a gold "disk" having a smoothly curving upper surface.
  • Each of these gold bumps may preferably be formed in accordance with the teachings of U.S. Patent 4,750,666 to Neugebauer et al., which is incorporated herein by reference. As is explained in more detail therein, a gold wire bonder is used to form these bumps.
  • a gold ball is formed on the end of the gold wire and bonded to the contact pad 16 or 18 in the same fashion as it would be bonded if a gold wire bond were being formed.
  • the wire is held fixed and the bonding head is moved laterally to shear the wire from the bump. This leaves a bump with a substantially smooth, pancake-like upper surface.
  • the wire may be broken by pulling vertically or melting. A pigtail of wire may be left on the bump, so long as it does not interfere with the subsequent steps in the assembly process.
  • Conductive bumps other than gold may be employed, if desired.
  • Gold bumps are preferred at this time because of the well established techniques for gold wire bonding which are easily modified to provide gold bumps and because for thermocompression bonding, it is easier to bond to the gold bumps than to flat metallization.
  • the use of gold bumps is also preferred because there is no yield loss at the wafer level.
  • chromium/copper metallization could be used with its attendant yield loss during processing at the wafer level if solder bonding were being used.
  • the size of the gold bumps 30 is somewhat dependent on the diameter of the gold wire employed in creating the gold bumps. With gold wire which is 1 mil (0.025 mm) in diameter, a bump about 3 mils (0.075 mm) in diameter at the pad surface and about 1 mil (0.025 mm) high is produced. The use of larger diameter wire provides a larger diameter, taller bump.
  • the individual gold bumps 30 are preferably produced by an automatic wire bonding machine which has been programmed to position the bumps in the desired locations. A wire bonding machine such as the K&S Model 1419 is very effective for this purpose, since it is externally programmable with the program in use depending on the disk inserted in its disk drive.
  • This machine is rated to produce two wire bonds per second and is capable of forming more gold bumps per second since each wire bond requires that the machine head contact the chip or its package twice, whereas forming a gold bump requires only one contact.
  • a very effective production process results, especially since use of gold bumps makes the provision of a solderable metallization on the pads 16 and 18 unnecessary.
  • Other bonding machines may also be utilized.
  • a gold flash may be provided on the contact pads 16 and 18.
  • a barrier layer such as chromium may be deposited on the aluminum prior to gold deposition to prevent the formation of gold/aluminum intermetallics at elevated temperatures.
  • a barrier layer such as chromium may be deposited on the aluminum prior to gold deposition to prevent the formation of gold/aluminum intermetallics at elevated temperatures.
  • One form of gold/aluminum intermetallic is the so-called "purple plague”.
  • a top surface lead frame 40 is shown in Figure 3.
  • a lead frame typically includes the leads for a plurality of devices (often 5 to 10) in a single strip in order to provide easily handled and manipulated components and to facilitate gang bonding in which a plurality of chips are bonded during each bonding step.
  • This lead frame includes portions 42 which hold the leads in their desired location until after encapsulation of the device and two leads or terminals 46 and 48, each having a bonding portion 46b and 48b, respectively, which is configured for bonding to the contact pads 16 and 18, respectively.
  • the terminals 46 and 48 are coined at the edge of the contact portions 46b and 48b, respectively, to raise the terminals 46 and 48 above the semiconductor chip where they extend laterally beyond the chip to reduce the risk of voltage breakdown between the terminals 46 and 48 and the back metallization on the semiconductor chip.
  • a lead frame 50 for the back side of the semiconductor chip is shown in Figure .
  • the frame 50 includes linking portions 52 which hold together the terminal portions 54 which form part of the final packaged device.
  • the chip 12 will be bonded by its back side metallization 14 to a bonding portion 54b of the terminal 54.
  • This bonding portion is preferably defined by the presence of a solder layer 56 to which the metallization 14 will be soldered during package assembly.
  • the chip 10 is shown positioned on the lead frame 50 with the lead frame 40 positioned on top of the chip.
  • the lead frame 40 is preferably bonded to the contact pads 16 and 18 by thermocompression bonding to the gold conductive bumps 30 disposed on those contact pads. This bonding is preferably performed prior to bonding the chip to the lead frame 50 in order that the lead frame 40 may be accurately aligned with the contact pads by use of a fixture which accurately positions the chip 10 relative to the lead frame 40.
  • the lead frame 40 with the attached chip 10 is positioned on the lead frame 50 with the metallization 14 on the back side of the chip disposed in alignment with the solder layer 56 on the frame portion 54b.
  • the combined structure is then heated to the melting point of the solder and cooled to bond the chip to the base lead frame 50.
  • the lead frames 40 and 50 and the associated chips which are bonded thereto are placed in a transfer molding fixture and the chip, the contact portions 46b and 48b and a portion of the terminals 46 and 48 are encapsulated within an insulating material such as epoxy 60 in Figure 6 in a manner which is well known in the art.
  • the epoxy 60 preferably bonds to a ledge in the back side terminal 54 without coating the bottom surface of the terminal 54 in order that direct contact may be provided between the terminal 54 and a heat sink.
  • the encapsulation may extend across that back surface of the terminal 54 under the chip with the extension of the terminal beyond the encapsulation being relied on for heat sinking.
  • the encapsulated chip is excised from the lead frames in the normal manner in this art to leave the encapsulated chip shown in Figure 7 with the upper surface terminals 96 and 98 extending laterally to the left in the figure and the bottom or back terminal 94 extending forward and backward in the figure.
  • Figure 8 is a cross-section through the finished device of Figure 7 taken along the line 8-8.
  • the ledge on the bottom terminal 54 with which the encapsulation 60 interlocks may be seen along the edges and is shown most clearly in the enlargement at the lower left in the figure.
  • the bonding portions 46b and 48b of the ' top surface terminals are direct bonded to the contact pads 16 and 18 by the gold conductive bumps 30.
  • One of these alternatives is to provide a gold flash on one or both of the bonding surfaces and provide a direct thermocompression bond between the electrode and the contact pad without the presence of the gold bumps.
  • a further alternative is to employ solder to bond the leads 46b and 48b to the gold bumps 30 without the use of thermocompression bonding.
  • the preferred thermocompression bonding of the upper leads to the contact pads avoids any concern about those leads becoming displaced during soldering of the chip to the bottom terminal 54.
  • the resulting package is a lightweight, low inductance package which is free of magnetic materials.
  • solder layer 56 may be omitted, the chip may be solderless bonded to the backside lead frame 50 to provide a solderless package with its attendant advantages.
  • solderless bond or "solderless bonded” means without solder, i.e. a direct bond.
  • solderless bonded includes thermocompression bonded, ultrasonically bonded, thermosonically bonded, diffusion bonded, cold welded, resistance welded, laser welded, spot welded and any other similar bonding process.
  • solderless bonding can be done by providing gold or other appropriate surface layers on metallization 14 and lead frame 50 or by use of gold conductive bumps bonded to either one or both of them as may be preferred.
  • the resulting all-thermocompression bonded package has the advantage that no de-bonding will occur even in the event that the device should be locally heated to the melting point of solder. While the use of a lead frame is preferred because of the resulting ease of handling and assembly, individual leads may be used instead, if desired. If desired, the terminals 46 and 48 may be bent or formed to extend vertically from the encapsulation 60 prior to encapsulation. This may be done either prior to or subsequent to bonding the lead frame 40 to the chip, but is preferably done as part of the process of fabricating the lead frame 40.

Abstract

Un module (90) à dispositif semi-conducteur encapsulé non hermétique comprend des sorties plates et larges (46b, 48b) liées aux pastilles de contact (16, 18) de la surface supérieure du dispositif. Ces sorties sont de préférence liées sans brasage à ces pastilles de contact.A module (90) with a non-hermetic encapsulated semiconductor device comprises flat and wide outlets (46b, 48b) linked to the contact pads (16, 18) of the upper surface of the device. These outputs are preferably linked without soldering to these contact pads.

Description

LOW INDUCTANCE ENCAPSULATED PACKACT INCLUDING A SEMICONDUCTOR CHIP
Related Applications This application relates to applications Serial No. (RD-18,934) filed , entitled "Hermetic
Package Having a Lead Extending Through an Aperture in the Package Lid and Packaged Semiconductor Chip", by V.A.K. Temple et al., application Serial No. (RD-19,320) , filed , entitled "High Current Hermetic Package
Having a Lead Extending Through the Package Lid and a Packaged Semiconductor Chip" by CA. Neugebauer et al. and
Serial No. (RD-19,321), filed , entitled "High Current Hermetic Package Including an Internal Foil and Having a Lead Extending Through the Package Lid and a Packaged Semiconductor Chip" by CA. Neugebauer et al.
Each of these related applications is incorporated herein by reference.
Background of the invention
Field of the Invention The present invention relates to the field of packages for semiconductor devices and packaged devices, and more particularly, to the field of non-hermetic packages and non-hermetically packaged devices.
Background information Semiconductor devices have been packaged in a vast variety of package configurations. These include both hermetic (gas-tight) and non-hermetic (gas-permeable) packages. In general, hermetic packages are more complicated to fabricate than non-hermetic packages with the result that hermetically packaged devices cost substantially more than non-hermetically packaged devices. In many applications, low cost is more important than hermeticity with the result that many devices are packaged and sold in non-hermetic packages.
In a typical non-hermetic package, the back side of the chip containing the power device is soldered to a package base which comprises one of the terminals of the final packaged device. Where isolation is desired from the package base, an insulating layer is disposed between the package base and the back of the chip. The contact pads on the top or front surface of the chip are then connected by wire bonds to a lead frame which is held in proper relation to the package base and chip. Thereafter, the chip, the wire bonds and a portion of the top side leads or terminals are encapsulated in an insulating material such as epoxy or other materials. One of the reasons for wire bonding the upper surface lead frame to the contact pads of the device is because wire bonding machinery can easily compensate for any misalignment in the bonding of the chip to the package base. Such packages have the disadvantage that the wire bonds require a significant space above the chip pads to be encapsulated in the epoxy material to protect those wire bond leads. Further, the wire bonds are normally made with round wire on the order of about 1 mil (0.025 mm) in diameter for low power integrated circuits or low power leads and about 30-40 mils (0.76-1.02 mm) in diameter for power or high current devices and about 0.3-0.5 inch (0.76-1.27 cm) long.
Consequently, they exhibit a significant inductance which can adversely affect the ability of the power device to operate in a desired manner at high frequencies.
There is a need for a low inductance non-hermetic package for semiconductor devices which is suitable for use with power devices and in high frequency systems. Ob-iects of the Invention Accordingly, a primary object of the present invention is to provide a non-hermetic package which has very low inductance.
Another object of the present invention is to provide a non-hermetic package which is free of wire bonds and of problems associated with die attach inaccuracy.
Summary of the Invention The above and other objects which will become apparent from the specification as a whole, including the drawings, are accomplished in accordance with a preferred embodiment of the present invention by a semiconductor device package in which relatively wide leads are bonded directly to the contact pads on the upper surface of the device. This may preferably be done prior to bonding the chip to the package base since chip alignment with the package base is less crucial than top electrode alignment with the contact pads. In accordance with one embodiment of the invention, the leads are solderless bonded to the contact pads using thermocompression bonding.
Brief Description of the Drawings The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of practice, together with further objects and advantages thereof, may best be understood by reference to the following description taken in connection with the accompanying drawings in which:
Figures 1-7 illustrate successive steps in the process of packaging a semiconductor device in accordance with the present invention; In particular, Figure 1 illustrates a semiconductor chip having contact pads on the upper surface thereof;
Figure 2 illustrates the chip of Figure 1 with conductive bumps bonded to the contact pads; Figure 3 illustrates a top side lead frame for use in connection with the chip of Figure 2;
Figure 4 illustrates a back side or package base lead frame for use with the chip of Figure 2;
Figure 5 illustrates the chip of Figure 2 bonded to both the top side and back side lead frames;
Figure 6 illustrates the structure of Figure 5 after encapsulation of the device in an insulating material;
Figure 7 illustrates the completed encapsulated device after it has been excised from the lead frames; and Figure 8 is a cross-section through the completed device of Figure 7 taken along the line 8-8.
Detailed Description A completed packaged semiconductor device in accordance with one embodiment of the present invention is illustrated generally at 90 in Figures 7 (perspective view) and 8 (perspective cross-section view) . The component parts and the process of assembling the package 90 will now be described in connection with Figures 1-8.
In Figure 1, a power semiconductor device is shown generally at 10. This device comprises a semiconductor body 12 having uniform metallization 14 disposed in ohmic contact with its lower surface. Two different contact pads 16 and 18 are disposed on the upper surface of the device or chip. These contact pads are spaced apart by a gap 17 between them. Where the power semiconductor device is a field effect transistor, the metallization 14 is normally the drain contact, the contact pad 16 is normally the source contact and the contact pad 18 is the gate contact. When the semiconductor device is an MCT, the metallization 14 and the contact pad 16 are the main current electrodes and the contact pad 18 is the gate contact.
Contact pads 16 and 18 are typically aluminum in such devices and thus not directly solderable with common solders. It is common practice to provide a solderable metal as the exposed surface of the back side metallization 14 in order that the device may be soldered to a package base or heat sink. If desired, it is also possible to form a solderable metallization as a surface layer on the aluminum contact pads on the upper surface of the device. However, to do so requires additional process steps with the attendant time and yield considerations. In accordance with the present invention, the contact pads 16 and 18 may be either solderable or non-solderable.
The process of packaging this device begins by forming conductive bumps 30 on the contact pads 16 and 18 as shown in Figure 2. Although the bumps 30 are shown laid out in an orderly array, they may be randomly positioned, if desired. In a preferred embodiment, each of the conductive bumps 30 is a gold "disk" having a smoothly curving upper surface. Each of these gold bumps may preferably be formed in accordance with the teachings of U.S. Patent 4,750,666 to Neugebauer et al., which is incorporated herein by reference. As is explained in more detail therein, a gold wire bonder is used to form these bumps. First, a gold ball is formed on the end of the gold wire and bonded to the contact pad 16 or 18 in the same fashion as it would be bonded if a gold wire bond were being formed. However, once the bump has been bonded to the contact pad, rather than releasing the wire for movement through the bonding head (while the bonding head moves to the location where the other end of the wire bond is to be attached) as is done in forming a wire bond, the wire is held fixed and the bonding head is moved laterally to shear the wire from the bump. This leaves a bump with a substantially smooth, pancake-like upper surface. Alternatively, the wire may be broken by pulling vertically or melting. A pigtail of wire may be left on the bump, so long as it does not interfere with the subsequent steps in the assembly process. Conductive bumps other than gold may be employed, if desired. Gold bumps are preferred at this time because of the well established techniques for gold wire bonding which are easily modified to provide gold bumps and because for thermocompression bonding, it is easier to bond to the gold bumps than to flat metallization. The use of gold bumps is also preferred because there is no yield loss at the wafer level. Alternatively, chromium/copper metallization could be used with its attendant yield loss during processing at the wafer level if solder bonding were being used.
The size of the gold bumps 30 is somewhat dependent on the diameter of the gold wire employed in creating the gold bumps. With gold wire which is 1 mil (0.025 mm) in diameter, a bump about 3 mils (0.075 mm) in diameter at the pad surface and about 1 mil (0.025 mm) high is produced. The use of larger diameter wire provides a larger diameter, taller bump. The individual gold bumps 30 are preferably produced by an automatic wire bonding machine which has been programmed to position the bumps in the desired locations. A wire bonding machine such as the K&S Model 1419 is very effective for this purpose, since it is externally programmable with the program in use depending on the disk inserted in its disk drive. This machine is rated to produce two wire bonds per second and is capable of forming more gold bumps per second since each wire bond requires that the machine head contact the chip or its package twice, whereas forming a gold bump requires only one contact. Thus, a very effective production process results, especially since use of gold bumps makes the provision of a solderable metallization on the pads 16 and 18 unnecessary. Other bonding machines may also be utilized. Alternatively, a gold flash may be provided on the contact pads 16 and 18. If desired, a barrier layer such as chromium may be deposited on the aluminum prior to gold deposition to prevent the formation of gold/aluminum intermetallics at elevated temperatures. One form of gold/aluminum intermetallic is the so-called "purple plague". A top surface lead frame 40 is shown in Figure 3.
As is well known in the power device art, a lead frame typically includes the leads for a plurality of devices (often 5 to 10) in a single strip in order to provide easily handled and manipulated components and to facilitate gang bonding in which a plurality of chips are bonded during each bonding step. This lead frame includes portions 42 which hold the leads in their desired location until after encapsulation of the device and two leads or terminals 46 and 48, each having a bonding portion 46b and 48b, respectively, which is configured for bonding to the contact pads 16 and 18, respectively. The terminals 46 and 48 are coined at the edge of the contact portions 46b and 48b, respectively, to raise the terminals 46 and 48 above the semiconductor chip where they extend laterally beyond the chip to reduce the risk of voltage breakdown between the terminals 46 and 48 and the back metallization on the semiconductor chip.
A lead frame 50 for the back side of the semiconductor chip is shown in Figure . The frame 50 includes linking portions 52 which hold together the terminal portions 54 which form part of the final packaged device.
The chip 12 will be bonded by its back side metallization 14 to a bonding portion 54b of the terminal 54. This bonding portion is preferably defined by the presence of a solder layer 56 to which the metallization 14 will be soldered during package assembly.
In Figure 5, the chip 10 is shown positioned on the lead frame 50 with the lead frame 40 positioned on top of the chip. The lead frame 40 is preferably bonded to the contact pads 16 and 18 by thermocompression bonding to the gold conductive bumps 30 disposed on those contact pads. This bonding is preferably performed prior to bonding the chip to the lead frame 50 in order that the lead frame 40 may be accurately aligned with the contact pads by use of a fixture which accurately positions the chip 10 relative to the lead frame 40. Thereafter, the lead frame 40 with the attached chip 10 is positioned on the lead frame 50 with the metallization 14 on the back side of the chip disposed in alignment with the solder layer 56 on the frame portion 54b. The combined structure is then heated to the melting point of the solder and cooled to bond the chip to the base lead frame 50.
Thereafter, the lead frames 40 and 50 and the associated chips which are bonded thereto are placed in a transfer molding fixture and the chip, the contact portions 46b and 48b and a portion of the terminals 46 and 48 are encapsulated within an insulating material such as epoxy 60 in Figure 6 in a manner which is well known in the art. The epoxy 60 preferably bonds to a ledge in the back side terminal 54 without coating the bottom surface of the terminal 54 in order that direct contact may be provided between the terminal 54 and a heat sink. However, if desired, the encapsulation may extend across that back surface of the terminal 54 under the chip with the extension of the terminal beyond the encapsulation being relied on for heat sinking.
Thereafter, the encapsulated chip is excised from the lead frames in the normal manner in this art to leave the encapsulated chip shown in Figure 7 with the upper surface terminals 96 and 98 extending laterally to the left in the figure and the bottom or back terminal 94 extending forward and backward in the figure. Figure 8 is a cross-section through the finished device of Figure 7 taken along the line 8-8. In Figure 8, the ledge on the bottom terminal 54 with which the encapsulation 60 interlocks may be seen along the edges and is shown most clearly in the enlargement at the lower left in the figure. It will be noted, that the bonding portions 46b and 48b of the' top surface terminals are direct bonded to the contact pads 16 and 18 by the gold conductive bumps 30.
Several alternatives are possible for the bonding of the terminals 46b and 48b to the contact pads 16 and 18. One of these alternatives is to provide a gold flash on one or both of the bonding surfaces and provide a direct thermocompression bond between the electrode and the contact pad without the presence of the gold bumps. A further alternative is to employ solder to bond the leads 46b and 48b to the gold bumps 30 without the use of thermocompression bonding. The preferred thermocompression bonding of the upper leads to the contact pads avoids any concern about those leads becoming displaced during soldering of the chip to the bottom terminal 54. The resulting package is a lightweight, low inductance package which is free of magnetic materials.
If desired, the solder layer 56 may be omitted, the chip may be solderless bonded to the backside lead frame 50 to provide a solderless package with its attendant advantages. As used in this specification and the appended claims, "solderless bond" or "solderless bonded" means without solder, i.e. a direct bond. Thus, "solderless bonded" includes thermocompression bonded, ultrasonically bonded, thermosonically bonded, diffusion bonded, cold welded, resistance welded, laser welded, spot welded and any other similar bonding process. Such solderless bonding can be done by providing gold or other appropriate surface layers on metallization 14 and lead frame 50 or by use of gold conductive bumps bonded to either one or both of them as may be preferred. The resulting all-thermocompression bonded package has the advantage that no de-bonding will occur even in the event that the device should be locally heated to the melting point of solder. While the use of a lead frame is preferred because of the resulting ease of handling and assembly, individual leads may be used instead, if desired. If desired, the terminals 46 and 48 may be bent or formed to extend vertically from the encapsulation 60 prior to encapsulation. This may be done either prior to or subsequent to bonding the lead frame 40 to the chip, but is preferably done as part of the process of fabricating the lead frame 40.
While the invention has been described in detail herein in accord with certain preferred embodiments thereof, many modifications and changes therein may be effected by those skilled in the art. Accordingly, it is intended by the appended claims to cover all such modifications and changes as fall within the true spirit and scope of the invention.

Claims

WHAT IS CLAIMED IS:
1. A packaged semiconductor chip comprising: a first contact pad disposed on a first major surface of said chip and a second contact pad disposed on a second major surface thereof; a first relatively wide flat lead bonded to said first contact pad; a second relatively wide flat lead bonded to said second contact pad; and insulating material encapsulating said chip and a portion of said second lead.
2. The packaged chip recited in claim 1 wherein: the bond between said second lead and said second contact pad includes a plurality of conductive bumps extending between said second contact pad and said second lead.
3. The packaged chip recited in claim 2 wherein the bond between said second lead and said conductive bumps is a solderless bond.
4. The packaged chip recited in claim 2 wherein the bonds between said second lead and said conductive bumps and between said conductive bumps and said second contact pad are solderless bonds.
5. The packaged chip recited in claim 1 wherein: said insulating material also encapsulates a portion of said first lead.
6. The packaged chip recited in claim 1 further comprising: a third contact pad disposed on said second major surface of said chip; and a third relatively wide, substantially flat lead bonded to said third contact pad.
7. The packaged chip recited in claim 6 wherein: said bond between said third lead and said third contact pad comprises a plurality of conductive bumps extending between said third lead and said third contact pad.
8. The packaged chip recited in claim 7 wherein: said bond between said third lead and said conductive bumps is a solderless bond.
9. The packaged chip recited in claim 8 wherein: said conductive bumps comprise gold.
10. The packaged chip recited in claim 7 wherein: the bond between said second lead and said second contact pad is a solderless bond; and the bond between said third lead and said third contact pad is a solderless bond.
11. The packaged chip recited in claim 10 wherein: said conductive bumps comprise gold.
12. A method of packaging a semiconductor chip comprising: providing a semiconductor chip having a first contact pad on a first surface thereof and a second contact pad on a second surface thereof; forming an array of conductive bumps on each contact pad on said second surface of said semiconductor chip; providing first and second conductive lead frames, said second lead frame including an individual lead for each contact pad on said second surface of said chip, each of said leads having a bonding portion configured for bonding to the corresponding bonding pad on said second surface of said semiconductor chip; aligning said bonding portions of said second lead frame with said contact pads on said second surface; bonding said bonding portions of said second lead frame to said conductive bumps without solder; bonding said first lead frame to said first contact pad; encapsulating said chip and a portion of each lead of said second lead frame in an insulating material; and excising said encapsulated chip and said leads from said lead frames.
13. The method recited in claim 12 wherein the step of encapsulating further includes: encapsulating a portion of each lead of said first lead frame in said insulating material.
14. A method of packaging a semiconductor chip comprising: providing a semiconductor chip having a first contact pad on a first surface thereof and a second contact pad on a second surface thereof; forming an array of conductive bumps on each contact pad on said second surface of said semiconductor chip; providing a conductive lead frame system including (D a second surface portion including an individual second surface lead for each electrically separate contact pad on said second surface of said chip, each of said second surface leads having a bonding portion configured for bonding to the corresponding bonding pad on said second surface of said semiconductor chip and (2) a first surface portion including a first surface lead for said contact pad on said first surface; aligning said bonding portions of said second surface leads with said contact pads on said second surface; bonding said bonding portions of said second surface leads to said conductive bumps without solder; bonding said first contact pad on said first surface of said chip to said first surface lead; encapsulating said chip and a portion of each second surface lead in an insulating material; and excising said encapsulated chip and said leads from said lead frame system.
15. The method recited in claim 14 wherein the step of encapsulating further includes: encapsulating a portion of each first surface lead of said lead frame system in said insulating material.
EP90917818A 1989-07-03 1990-06-12 Low inductance encapsulated package including a semiconductor chip Withdrawn EP0470210A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US37564089A 1989-07-03 1989-07-03
US375640 1989-07-03

Publications (1)

Publication Number Publication Date
EP0470210A1 true EP0470210A1 (en) 1992-02-12

Family

ID=23481697

Family Applications (1)

Application Number Title Priority Date Filing Date
EP90917818A Withdrawn EP0470210A1 (en) 1989-07-03 1990-06-12 Low inductance encapsulated package including a semiconductor chip

Country Status (3)

Country Link
EP (1) EP0470210A1 (en)
JP (1) JPH04503283A (en)
WO (1) WO1991000617A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6249041B1 (en) * 1998-06-02 2001-06-19 Siliconix Incorporated IC chip package with directly connected leads
US6720642B1 (en) 1999-12-16 2004-04-13 Fairchild Semiconductor Corporation Flip chip in leaded molded package and method of manufacture thereof
DE10157362B4 (en) * 2001-11-23 2006-11-16 Infineon Technologies Ag Power module and method for its production
JP4722757B2 (en) * 2006-04-19 2011-07-13 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
US9859680B2 (en) 2013-12-17 2018-01-02 Lasermax, Inc. Shock resistant laser module
US9373566B2 (en) * 2014-03-19 2016-06-21 Infineon Technologies Austria Ag High power electronic component with multiple leadframes

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4117508A (en) * 1977-03-21 1978-09-26 General Electric Company Pressurizable semiconductor pellet assembly
US4647959A (en) * 1985-05-20 1987-03-03 Tektronix, Inc. Integrated circuit package, and method of forming an integrated circuit package

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9100617A1 *

Also Published As

Publication number Publication date
JPH04503283A (en) 1992-06-11
WO1991000617A1 (en) 1991-01-10

Similar Documents

Publication Publication Date Title
US5135890A (en) Method of forming a hermetic package having a lead extending through an aperture in the package lid and packaged semiconductor chip
US5028987A (en) High current hermetic package having a lead extending through the package lid and a packaged semiconductor chip
US5103290A (en) Hermetic package having a lead extending through an aperture in the package lid and packaged semiconductor chip
US9847280B2 (en) Method for manufacturing semiconductor device
US5166773A (en) Hermetic package and packaged semiconductor chip having closely spaced leads extending through the package lid
US7157799B2 (en) Semiconductor die package including carrier with mask and semiconductor die
US5844304A (en) Process for manufacturing semiconductor device and semiconductor wafer
US4835120A (en) Method of making a multilayer molded plastic IC package
US6764880B2 (en) Semiconductor package and fabricating method thereof
US6762079B2 (en) Methods for fabricating dual loc semiconductor die assembly employing floating lead finger structure
KR100497974B1 (en) Semiconductor device and manufacturing method thereof
KR101469770B1 (en) Power device package and method of fabricating the same
US7820489B2 (en) Method of manufacturing semiconductor apparatus
EP2058857A2 (en) IC chip package with directly connected leads
JP2006520103A (en) Flip chip coated metal stud bumps made of coated wire
US8354692B2 (en) Vertical semiconductor power switch, electronic component and methods of producing the same
US5105536A (en) Method of packaging a semiconductor chip in a low inductance package
KR950000205B1 (en) Lead frame and semiconductor device using the same
JP2779620B2 (en) Method for housing cage of semiconductor device and integrated circuit inside plastic package
US5018002A (en) High current hermetic package including an internal foil and having a lead extending through the package lid and a packaged semiconductor chip
US5209390A (en) Hermetic package and packaged semiconductor chip having closely spaced leads extending through the package lid
EP0470210A1 (en) Low inductance encapsulated package including a semiconductor chip
GB2261547A (en) Semiconductor device with bonding pads at the edge
JP3670625B2 (en) Semiconductor device and manufacturing method thereof
KR100422608B1 (en) Stack chip package

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19910226

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB IT

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN

18W Application withdrawn

Withdrawal date: 19920316